Flyback Chris Basso APEC Seminar 2011

The Dark Side of Flyback
Converters
Presented by Christophe Basso
Senior Scientist
IEEE Senior Member
1 • Chris Basso – APEC 2011

Course Agenda
 The Flyback Converter

 The Parasitic Elements
 How These Parasitics Affect your Design?
 Current-Mode is the Most Popular Scheme
 Fixed or Variable Frequency?
 More Power than Needed
 The Frequency Response
 Compensating With the TL431

What is the Subject?
 There has been numerous seminars on Flyback converters
 Seminars are usually highly theoretical – link to the market?
 Industrial requirements usually not covered: standby, over power…
 This 3-hour seminar will shed lights on less covered topics:
 Why the converter delivers more power than expected? Solutions?
 Books talk about compensation with op amps, I have a TL431!
 The origin of the Right-Half Plane Zero, how do I deal with it?
 Quasi-resonant converters presence increases, how do they work?
 In a 3-hour course, we are just scratching the surface…!

The Flyback, a Popular Structure
 The flyback converter is widely used in consumer products
 Ease of design, low-cost, well-known structure
 Poor EMI signature, bulky transformer, practical up to 150 W
DVD player
Set-top box
flyback  10 – 35 W
Charger
Notebook
Netbook

An Isolated Buck-Boost
 The flyback converter is derived from the buck-boost cell
2 7 8
11
drv SW1 L C
Vout 1 N C Vout
D
Vin 1 4 Vin Vin
5 9 12
D Vout gnd gnd
L C drv
D drv
a b SW1 c SW1
buck-boost buck-boost flyback

ground referenced input referenced isolated ground referenced
 The addition of a transformer brings:

• Up or down scale Vin
Vin -k.Vin
• Isolation
+ • Polarity change
• More than 1 output

The Turn-on Event
 The power switch turns on: current ramps up in Lp, D is blocked
 NVin Vout ip t 
Vin
I peak  I valley  ton
Ip I peak Lp
IC
.
Vin Lp . I valley
CCM
ton
Vin I sec  0 Vin
I peak  ton
I peak Lp
N  Ns N p
0V
DCM
SW
PIV  Vin N  Vout Vin ton
Reverse voltage on the diode Son 
Lp
 The current increases in the inductor in relationship to Vin and Lp

 The output capacitor supplies the load on its own
Simplified, no leakage

Applying Volt-Second Balance, CCM
 The power switch turns off: D conducts, Vout "flies" back
Vout vLp(t)
IC Apply volt-second balance

Ip N Vin
.
Vout N Lp .
Vin Vout/N
ton = DTsw toff = (1-D)Tsw
Reflected
voltage
Vout
VDS ,off  Vin   Vin  Vr
N
Vout Nton NDTsw ND

   dc transfer function in CCM
Vin toff 1  D  Tsw 1  D
Applying Volt-Second Balance, DCM
 In DCM, when Lp is fully depleted D opens: Vout reflection is lost
vLp(t)
IC Apply volt-second balance
I sec  0
Vin
.
0V Lp DT
.
Vin
Vout /N
ton = DTsw toff = (1-D)Tsw
VDS ,off  Vin
Vout Rload
D From the buck-boost:
Vin 2 L p Fsw
Vout Rload
D
dc transfer function in DCM NVin 2 L p N 2 Fsw

Flyback, Typical Waveforms
 Below is a simple flyback converter, without parasitics
X2
XFMR
RATIO = -0.1 D1
6 1
Vout
Lp
. 3
Cout Rload
2.2m Ls 470u 2
. IC = 10
5
IIn
Vin Vds
100
D
4 2
X1
PSW1
V2 RON = 10m
ROFF = 1Meg
S
V2 4 0 PULSE 0 5 0 10n 10n 3u 10u
 It will run open loop for simplicity, Vout  8 V

No parasitics

Flyback, Typical Waveforms, CCM
1.60
Ipeak Iin(t)
iin in amperes
1.20
Ivalley Input current
plot1
800m
400m
0 1
1.15 Epeak
I L
i(lp) in amperes
1.05 ILp(t)
Evalley
plot2
950m
850m
Inductor current
2
750m
250 Diode blocks

Vout N  Vin Vout N
vds in volts
190 3
Vin
plot3
130
70.0
Drain voltage
10.0
VDS(t)
8.89
4
vout in volts
8.87
plot4
8.85
Output voltage
8.83
8.81
Output cap.
refueling
Output capacitor
supplies the load
Vout(t)
16.0
id(d1) in amperes
12.0 Ipeak / N Id(t)

Diode current
plot5
8.00 5
4.00
0
3.002m 3.006m 3.010m 3.014m 3.018m
time in seconds
CCM flyback – no parasitics

Flyback, Typical Waveforms, DCM
400m
iin in amperes
300m
Ipeak Iin(t) Input current
Plot1
200m
100m
0 1
400m
i(lp) in amperes
DCM (core reset) Epeak

300m I L ILp(t)
Inductor current
Plot2
200m
100m
Evalley = 0
0 2
400
Vout N  Vin Diode blocks
Vout N VDS(t)
vds in volts
300
Plot3
200
Vin Drain voltage
100 3
0
12.648
4
vout in volts
12.644
Plot4
12.640 Output voltage

12.636 Output capacitor
12.632
Output cap.
refueling supplies the load Vout(t)
3.00
id(d1) in amperes
2.00 Ipeak / N Id(t)

Diode current
Plot5
1.00
0 5
-1.00
3.002m 3.006m 3.010m 3.014m 3.018m
time in seconds
DCM flyback – no parasitics

Energy Transfer in CCM and DCM
 The primary inductance, Lp, stores and releases energy
1
ELp ,valley  L p I valley 2 Initially stored energy
2
1
EL p , peak  L p I peak 2 Stored energy at ton
2
1 1 1
ELp , accu  L p I peak  L p I valley  L p  I peak 2  I valley 2 
2 2
Accumulated energy at Tsw
2 2 2
 Power (W) is energy (J) averaged over time (s):

Eta, the efficiency
1
Pout 
2
 
I peak 2  I valley 2 L p Fsw CCM
1
Pout  I peak 2 L p Fsw DCM, Ivalley = 0
2

Course Agenda


Considering Parasitic Elements
 The transformer and the MOSFET include parasitics
X2
D1
rLf XFMR
1n5819
250m RATIO = -0.1
9 6 1
Vout
Lp
. 3
Cout
{Lp} Ls 470u
. IC = 10
IIn Rload
7
2
2
Lleak Resr
5
{Leak} 150m
Vin X1
100 PSW1
RON = 10m
ROFF = 1Meg Vds
4 8
parameters
Clump Lp=2.2m
Dbody
V2 100p
k=0.02
Leak=Lp*k
V2 4 0 PULSE 0 5 0 10n 10n 3u 10u
With parasitics

Considering Parasitic Elements, CCM
800m
Ipeak Iin(t)
iin in amperes
400m
Input current
plot1
0 1
-400m
-800m
950m
ILp(t)
i(lp) in amperes
850m
Inductor current
plot2
750m
650m 2
550m
770
Leakage Vout  Vf  N  Vin  Vleak VDS(t)
vds in volts
570 inductance
Vin Drain voltage
plot3
370 contribution
170 3
-30.0
9.60
vout in volts
9.00
Output voltage
plot4
8.40 4
7.80
7.20
Vout(t)
16.0
id(d1) in amperes
12.0 Id(t) Diode current

plot5
8.00
5
4.00
0
3.002m 3.006m 3.010m 3.014m 3.018m
time in seconds
CCM mode – with parasitics

Considering Parasitic Elements, DCM
300m
iin in amperes
200m Ipeak Iin(t) Input current

plot1
100m
0
1
-100m
300m DCM (core reset)

ILp(t)
i(lp) in amperes
200m
Inductor current
plot2
100m
0
2
-100m
370 Leakage
inductance Vout  Vf  N  Vin  Vleak
vds in volts
270
contribution Vin Drain voltage
plot3
170
3
70.0
-30.0 VDS(t)
13.0
Diode blocks here Vout(t)
vout in volts
12.8
Output voltage
plot4
12.6
12.4
12.2 4
4.00
Id(t)
id(d1) in amperes
3.00
Diode current
plot5
2.00
1.00
0 5
3.002m 3.007m 3.012m 3.017m 3.022m
time in seconds
DCM mode – with parasitics

Who Are the Stray Elements?
 The study of the drain node reveals a LC network
Vbulk Vbulk
. .
. Lp .
lleak
Coss
Simplified view
Lp primary inductor
lleak leakage inductor
Coss output capacitance

The MOSFET COSS is a Non-Linear Device
 The capacitor value changes with its bias voltage
CD 0
COSS VDS  
 VDS 
1  
 V0 
CD0 is the cap. for VDS = V0
1
 As bias affects the capacitor value: W  COSSVDS 2
2

As the Voltage Decreases, COSS Value Changes
 The brutal discharge generates switching losses
dVC  t  t
IC IC  t   C W   I C  t VC  t   dt
dt 0
D dVDS  t 
t VDS
VC COSS W  C VDS  t   dt   C VDS VDS  dVDS
0 dt 0
S
MOSFET
CD 0 V0 2
COSS VDS   W  VDS 3 2CD 0 V0
VDS 3
At turn-off
 The energy lost is smaller with the non-linear variation!

Using the Raw COSS is an … Overkill
 Re-compute the capacitor from the MOSFET data-sheet
VD 0
CD 0
 The classical equation gives:
1
W  COSSVDS 2  0.5  400 p  1002  2 µJ or 200 mW @ 100 kHz
2
 The updated equation gives: Overkill
2 2
W  VDS 3 2CD 0 V0   1003 2  400 p  10  843 nJ
3 3
or 84 mW @ 100 kHz = 58% reduction

The Leakage Inductance
 The coupling in a transformer is not perfect
Closed path
in the air Leakage flux
Closed path
Leakage flux in the air
 Some induction lines couple in the air: leakage flux

An Equivalent Transformer Model
 For a two-winding transformer, the model is simple:
 Two leakage inductors
 One magnetizing inductor
lleak1 lleak2
primary Lp secondary
1:N
 This is commonly known as the "PI" model

The Transformer Scales the Primary Current
 In a perfect transformer, we have:
1: N
Ip . . I sec 
Ip
N
Primary Secondary
 The turns ratio is usually normalized to the primary

Divide by Np Np Ns
N p : Ns : 1: N
Np Np
N p  100 . .
1: 0.25 1 250m
N s  25

The Leakage Term also Stores Energy
 At turn-on, the primary current flows in both lleak and Lp
Lp
I p t  I p t 
1
lleak Wleak  lleak I p 2
Vin 2
Vin
Son 
L p  lleak N=1
 During the on-time, both Lp and lleak store energy

Where does the Current Flow?
 At turn-off, the energy stored in Lp is dumped in the output cap.
I lleak  t 
Lp Vout  t 
I Lp  t 
I Lp  t   I lleak  t 
lleak
Vin
I lleak  t 
Clump
 The leakage inductor current fills up the drain lump capacitor

Watch out for the Maximum Excursion!
 As the diode conducts, Vout reflects over Lp
Flyback Characteristic
Vout  V f voltage impedance
N
VDS ,max  Vin 
Vout Vf I lleak
peak
I lleak  t  N Clump
lleak
Vin
800
600
400
I lleak  t  200
0
Clump
VDS  t 
 The voltage on the drain increases dangerously!

We Need to Clamp that Voltage
 MOSFETs have a voltage limit they can fly up to: BVDSS
 A clamping circuit has been installed to respect a margin
Vout  V f
Vclamp Vclamp
N
Lp
lleak
D D Vin  Vclamp
BVDSS  600 V

Resetting the Leakage Inductance
 Because of the clamp action, a voltage appears across lleak
Vlleak  Vclamp  Vout  V f  I L p  t   I lleak  t 
Vclamp Lp Vout  t 
I Lp  t 
I lleak  t 
lleak Vlleak
I lleak  t 
Vclamp  Vout  V f 
Slleak 
lleak
 This voltage forces a reset of the leakage inductance

Do we Need a Quick Reset?
 When current flows in lleak, it is diverted from the secondary
I lleak  t  I L p  t   I lleak  t 
Lp
I Lp  t 
I lleak  t 
lleak
At the switch opening:
I lleak  t 
I Lp  t   I lleak  t 
I sec  t   0
 The leakage current delays the occurrence of the sec. current

lleak Delays the Secondary Current
 The leakage inductor reduces the peak secondary current
I t  I p I sec
I peak
I L p , I lleak I p t  Primary and

secondary currents.
I valley
I lleak I sec  t 
t
ton t toff  t
 The "stolen" energy is dissipated as heat in the clamping network

 Less energy is transmitted to the secondary side

A Reduced Secondary-Side Current
 We can calculate the leakage inductor reset time t
Vclamp  Vout  V f 
I t  I sec Slleak 
lleak
I peak I peak lleak I peak
t  
Slleak Vclamp  Vout  V f 
I p t 
N1 I peak Nlleak I peak
t  
Slleak NVclamp  Vout  V f 
I lleak  t 
 
 
I peak I peak  lleak 1 
t I sec   Ssec t  1
N N  Lp NVclamp 
 1 
t V  V 
 out f 
lleak NVclamp I peak
 1.8%,  1.5 I sec   3.6%
Lp Vout  V f N

Typical Example Simulation Results
260m
ILp(t) Ipeak = 236 mA I’peak = 210 mA
ilp in amperes
180m
plot1
100m Primary current

20.0m 2
-60.0m
t = 480 ns
260m
Ileak(t)
illeak in amperes
180m
Leakage inductor
Plot3
100m
20.0m 0 3 current
-60.0m
trr
2.50
Id,peak=2.1 A Id(t)
id1 in amperes
1.90
plot2
1.30
Sec. current
700m
100m
11% decrease! 4
280
200
VDS(t)
vds in volts
Drain voltage
Plot4
120
1
40.0
-40.0
3.011m 3.015m 3.019m 3.023m 3.027m
time in seconds

A Ringing Appears as the Diode Blocks
Vout  V f
 As the clamp diode blocks, the drain returns to Vin 
N
Vin
Vr
. An oscillation
. Vout takes place
1: N
lleak t lleak is reset
I lleak  t   0
Clump Vin  Vclamp  Vr 1

f 
2 lleak Clump

The Primary Inductor also Rings in DCM
 When Lp is reset, the capacitor voltage returns to Vin
Vin
0V
. An oscillation
. takes place
1: N
Lp is reset
lleak
Vin
Clump Vin  Vr
1
f 
2 L p  lleak  Clump

Course Agenda


How these Parasitics Affect your Design?
 The leakage inductor induces a large spike at turn-off
 This voltage excursion must be kept under control
V
BVDSS
Vclamp 15%
Vin
t
 The lump capacitor on the drain brings switching losses

 Is there a way to switch on again when discharged?
VDS  Vin
Vin Vin
VDS  Vin
VDS  t  VDS  t 
Asynchronous switching Synchronous switching
Fixed frequency Variable frequency

Protecting the Power MOSFET
 A vertical MOSFET features a buried parasitic NPN transistor
 The collector-base junction of this transistor forms the body-diode
 This « diode » can accept to avalanche in certain conditions
 Do NOT use this diode as a Transient Voltage Suppressor
 Adopt a safety coefficient kD when chosing the maximum VDS(t)

 15% derating is usually selected
drain
kD = 0.85
gate
BVDSS  k D  600  0.85  510 V
Vclamp  BVDSS  k D  Vos  Vin  115 V
source
Take Vos around 15 – 20 V
RCD clamp
design entry

Inclusion of a Safety Margin
 The voltage on the drain swings up to Vclamp
BVDSS = 600 V Vout  nominal

I out  max
Safety margin
Vin  max
Vos
Vclamp
Vr
100 V /
Vin
div Test at start-up
and in short-circuit
VDS(t)
 Capture this waveform in worst-case conditions

The Clamp Circuit Overshoots
 The clamp diode forward transit time delays the clamping action
Vos = 14 V
VDS(t)
 This spike can be lethal to the power MOSFET

Do not Reflect too Much Voltage
 The reflected voltage affects the power dissipation in the clamp
1 kc Vclamp
PVclamp ,avg  Fsw Lleak I peak 2 kc 
2  kc  1 Vr
60
50
40
Pclamp  W  30
20
10
0
1 1.5 2 2.5 3
kc
 If Vclamp is too close to Vr, dissipation occurs  kc = 1.3 to 2

Compute the Transformer Turns Ratio
 The turns ratio affects the reflected voltage…
V out Vf  kc Vout  V f 

Vclamp  kc N
N Vclamp
 But also the Peak Inverse Voltage of the secondary diode
PIV  Vin N  Vout

ringing
Choose a 100%
derating factor
Vf PIV
If PIV  100 V Vd  t 
Then BV  200 V
 Always check the margins are not violated in any operating modes

Select the Clamp Passive Elements
 The clamp resistor depends on the maximum peak current

2Vclamp Vclamp 
Vout  V f  
 N  Vclamp Cclp Rclp
Rclp  Cclp 
Fswlleak I peak 2 Rclp Fsw V
D
Vsense ,max Vin ,max

I peak ,max   t prop
Rsense Lp
Worst-case value
 Watch for the peak current overshoot in fault!

Clamp Current is Smaller
 Lump capacitance charge at turn off depletes the leakage energy
I = 234 mA 1.13² = 1.28

(0.234/1.84)*100 = 13% Power is reduced by 28%

The Leakage Inductor Rings
 This ringing can be of high frequency and is radiated-EMI rich
Cclp .
Rclp .
Rdamp
D
VDS(t)
 It can also forward-bias the MOSFET body diode

 Damp it!

Fighting Parasitic Ringing – part I
 The installed resistor reduces the ringing on the drain
V
With Rdamp
Similar
overshoot
Without Rdamp
a VDS(t) b VDS(t)
0lleak
Q 1 Zlleak @ f 0  Rdamp
Rdamp

Fighting Parasitic Ringing – part II
 If the series resistor is not enough, install a damper
. 1. Measure the ringing: f0

Rdamp
.
2. Evaluate leakage impedance at f0
Z lleak  2 lleak f 0
Cdamp
3. Make Rdamp  Z lleak
1
4. Try Cdamp 
2 f 0 R
5. Tweak for power dissipation
Ray Ridley – Snubber design procedure

Effects brought by clamping action
vdrain in volts 520 Vpeak = 510 V VDS(t)
400
1
plot1
280
160 Fleak = 2.08 MHz
40.0
No damper – zoom
3.0325m 3.0335m 3.0345m 3.0355m 3.0365m
time in seconds
490
VDS(t)
vdrain in volts
370
Plot5
250
130 Can forward bias
10.0 a the body diode No damper 2
3.042m 3.046m 3.050m 3.054m 3.058m
time in seconds
490
Vpeak = 452 V VDS(t)
vdrain#a in volts
3
370
Plot4
250
130
10.0 b Rdamp = 290  – Cdamp = 220 pF
3.042m 3.046m 3.050m 3.054m 3.058m
time in seconds
490 Vpeak = 494 V VDS(t)

vdrain#a in volts
370
Plot3
250
130
10.0 c Rdamp = 290  – Cdamp = 50 pF 3
3.042m 3.046m 3.050m 3.054m 3.058m
time in seconds

What Diode to Select for the Clamp?
 A fast diode is a must: MUR160 is good fit
VDS(t)
V = 37 V
No ringing!
Id(t)
Recovery losses
VDS(t)
 Can a simple 1N4007 be used in a RCD clamping network?

 The answer is yes for low power applications (below 20 W)
 The long recovery time naturally damps the leakage inductor

Be Sure the Clamp Level does not Runaway
 Watch-out for clamp voltage variations, at start-up or in short-circuit
 The main problem comes from the propagation delay!
140
120
100
Vclamp (V) )
80
60
40
0 1 2 3
Ipeak (A)

Check the Clamp Voltage Variations
No design margin!
600
vdrain in volts
400 10
Drain
plot1
200
0
-200 VDS(t) voltage

150u 450u 750u 1.05m 1.35m
time in seconds
300
vclamp in volts
200
Clamp
Plot2
12
100
0
-100
Vclamp(t) voltage
150u 450u 750u 1.05m 1.35m
time in seconds
overshoot
1.30 Max Vsense
vsense in volts
900m
Vsense(t) Sense
Plot3
500m
100m
-300m
15 voltage
150u 450u 750u 1.05m 1.35m
time in seconds
14.0
16
Output
vout in volts
10.0
Plot4
6.00
2.00 Vout(t) voltage

-2.00 Worst case
150u 450u 750u 1.05m 1.35m
time in seconds

A Zener or TVS to Hard Clamp the Voltage
 TVS do not suffer from voltage runaways in fault conditions
Vbulk Vout
TVS
Id(t)
Dclp t  200 ns
VDS(t)
1 Vz
PTVS  Fswlleak I peak 2
2
Vz 
Vout  V f 
N
 The TVS improves the efficiency in standby but degrades EMI
 It costs around 5 cents…

Course Agenda


What Control Scheme?
 Two control scheme coexist, current-mode and voltage-mode
Voltage-mode?
Operating
waveforms
are identical
Current-mode?
Voltage-mode?
Ac -transfer
functions
differ
Current-mode?

Voltage-Mode Control
 Voltage mode uses a ramp to generate the duty-ratio
 The error voltage directly adjusts the duty-ratio
Vout
Vbulk .
.
vdd S
Q
Q
Verr  t 
FB
D t 
R
Vsaw  t 
Verr -
+ D t 
Rsense
+
-
Vmax

Voltage-Mode Control
PROs
 Does not need the inductor current information

 Can go to very small duty-ratio
 CCM operation without sub-harmonic instabilities
 No need for slope compensation, current limit unaffected
CONs
 No inherent input line feedforward (weak audio susceptibility)

 Cannot use small bulk capacitor, bad ripple rejection
 2nd-order system in CCM: mode transition can be a problem
 Limited integrated circuit offer

Peak-Current-Mode Control
 Current mode uses the inductor current information as a ramp
 The error voltage adjusts the inductor peak current
 The duty-ratio is indirectly controlled
Vout
Vbulk .
.
D t 
S
Q
Q
vdd
I L t 
R Verr  t 
FB +
Verr I L t 
Rsense
Vmax

Peak-Current-Mode Control
PROs
 Inherent pulse-by-pulse current limitation

 Natural input line rejection
 Mode transition DCM to CCM is easy
 Converter remains a 1st-order system at low frequency
 Widest offer on the market: a really popular technique!
CONs
 Leading Edge Blanking limits the minimum duty-ratio

 Requires slope compensation against sub-harmonic oscillations
 Additionnal ramp affects the available maximum peak current
 Current sense can sometimes be a problem (floating sense)

A Dirty Inductor Current Signal
 The inductor current is sensed with a resistor, a transformer…
 This information is affected by parasitics: false tripping possible!
700m
Can potentially
false trip the
500m
controller
300m
100m
-100m
Vsense  t 
3.122m 3.126m 3.131m 3.135m 3.139m

The LEB Cleanses the Signal
 A circuit blinds the controller at turn-on for a small time (250 ns)
 It conveys the signal afterwards: Leading Edge Blanking
Vbulk
PWM .
reset .
2
DRV
Vsense  t 
S2 CS
Clean
Rsense edges
S1 2
DRV
t LEB

It Limits the Minimum Duty-Ratio
 During the LEB duration, the controller is completely blind!
 In output winding short-circuits, failures are likely to occur
4
+ 80% 0.8 R sense
2.6
1.2
VCS  t 
t LEB
V sense  t 
13.0 V DRV  t 
9.00
t LEB  t del
5.00
1.00
-3.00
591u 594u 597u 600u 603u

If the Primary Inductor is too Low…
 In short-circuit situations, you reflect the diode forward drop
Vf
Vbulk I Lp  t 
Vf .
Almost
1 N
N . no decrease
Soff
V S on
S on  in
Lp
Vf
Rsense S off 
NL p t
ton ,min
Tsw
 If you hit the minimum on-time, you cannot limit the current!

The Primary Current Runs out of Control
 The current current climbs cycle by cycle until smoke appears!
9.00
Maximum theoretical
peak value, 5 A 7
7.00
iprim in amperes
The current climbs-up

Plot1
5.00
to 9 A!!
3.00
Demagnetization Chris Basso

1.00
ok too weak ILp(t) first design…
Minimum ton
1.60
Vsense(t)
1.20
1V
vsense in volts
Plot2
800m
400m
0 8
35.0u 70.0u 105u 140u 175u

time in seconds

Sub-Harmonic Oscillations
 Ac analysis shows a first-order system at fc << Fsw/2
 No LC peaking anymore as in CCM voltage mode
 But a subharmonic peaking at Fsw/2 now appears
25.0
15.0
H s
5.00
-5.00
-15.0
180
90.0
-90.0
-180 H  s  Flyback power

stage in CCM
1 10 100 1k 10k 100k

Instability Depends on Duty-Ratio
 The condition for instability is: CCM operation + duty-ratio > 50%
IL
I peak  a  S1t
IL(0) Ipeak  IL(Tsw) Verr
Ri b  I peak  S 2 t
S1 S2 Solving
a t
b IL(Tsw) I peak  a I peak  b

IL(0) S1 S2
IL(0) I L (0) I L (Tsw )
 IL(Tsw) 
t S1 S2
S2 d
t 
S1 d '
dTsw d’Tsw
Tsw n
 d 
I L ( nTsw )  I L (0)   
 d '

Instability Depends on Duty-Ratio
 With a duty-ratio below 50%, perturbation naturally dies out …
IL
clock
Ipeak
IL(0)
Duty-ratio < 50%
IL(0)
t
Asymptotically stable Perturbation has gone…
n
 d 
IL I L (nTsw )  I L (0)   
clock
 d '
Ipeak
Duty clamp
IL(0)
IL(0)
Duty-ratio > 50%
t
Asymptotically unstable

The Cure is in the Ramp
 Injecting a ramp on the feedback signal, damping is obtained
IL  Sa 
n
 1 S  n
Verr I L ( nTsw )  I L (0)   2
  I L (0)  a 
b c  d '  Sa 
Ri  d S 2 
Sa
S1 Must stay
S2 IL(Tsw) below 1
IL(0)
IL(0) Sa
1
t IL(Tsw)
Up to S2
d = 100% 1
S
0 a
t S2
dTsw d’Tsw
Tsw
S a  50% S 2

A Model to Simulate a Flyback Converter
 A SPICE model can predict subharmonic instabilities
774mV
3 2
PWM switch CM
vc
a
duty-cycle
DC 5 X2x
441mV XFMR D1A
RATIO = -N mbr20200ctp vout
100V -79.0V 19.7V 19.0V
vout
6 1
p
Vin
c
100
AC = 0 R10
0V
4 14.4m
X9
19.0V Rload
PWMCM Lp 8 4
L = Lp {Lp} B1 C5
Fs = Fsw
Voltage 6600u
Ri = Ri
Se = Se V(err)/3 > 1 ?
1 : V(err)/3
parameters R1
X3
66k
AMPSIMP
Vout=19 2.32V
LoL 2.50V 10
err
Soff=(Vout/(N*Lp))*Ri 1kH
13 12
2.50V
CoL 2.32V 2.32V
N=250m 1kF
9
Fsw=65k 0V
15
R2
Lp=350u 10k
Ri=250m AC = 1 V2
Vstim 2.5
A=0.5
Se=A*Soff

Simulation Results of the CCM Flyback
 As ramp is injected, the double-pole Q is damped
 Injecting more ramp turns the converter into voltage-mode
24.0
12.0
No ramp
-12.0
H s S a  50% S2
-24.0
180
No ramp
90.0
-90.0
-180 H  s  S a  50% S2
1 10 100 1k 10k 100k

Modern Circuits Include Slope Compensation
 A simple resistor in series with current sense resistor does the job
Vbulk
2.5 V
PWM .
reset .
Rramp
20 kΩ 6 Q2
R18
S2
VFB 4.2 4
R11
0.8 V C9 R25
S1
PWM
300 ns
Q delay Adjust the resistor to set
the ramp to any level
NCP1250

Course Agenda


Modulation Strategies
 The most popular modulation strategy is trailing-edge
vGS(t) feedback
on
Trailing edge
off modulation
Clock
 Leading-edge modulation often appears in post-regulators

vGS(t)
feedback
on
off off
Leading edge
modulation
Clock

Fixed Frequency Operation
 The vast majority of converters use fixed-frequency operation
 Switching losses depend on frequency: high frequency, high losses!
 Capacitive losses are a brake to efficiency improvement
 CCM operation induces high losses on the secondary diode
 Potential shoot-trough hampers synchronous rectification
 The Right Half-Plane Zero severely limits the available bandwidth
Hard blocking
iD  t  Noise and losses! id  t 
vDS  t  iDS  t 

The Right-Half-Plane Zero
 In a CCM flyback, Iout is delivered during the off-time:
id(t) id(t)
IL0 IL1
Vin Vin
Lp Lp
IL(t) Id0 IL(t)

Id1
d̂
t t
D0Tsw D1Tsw
Tsw Tsw
 If D brutally increases, D' reduces and Iout drops! dvL  t 
 What matters is the inductor current slew-rate
dt

Processing the Output Power Demand
 If iL(t) can rapidly change, Iout increases when D goes up
200 µs d = 59%
d(t) vout(t)
d = 58.3%
iL(t)
iout(t)
100u 300u 500u 700u 900u

Failing to Increase the Current in Time
 If iL(t) is limited because of a big Lp, Iout drops when D increases
2
10 µs
d = 59%
d(t) vout(t)
Vout drops!
d = 58.3%
iL(t)
iout(t)
Iout drops!
100u 300u 500u 700u 900u

The RHPZ is a Positive Root
 Small-signal equations can help us to formalize it
The negative sign

indicates a positive root!
 s  s 
1  

1 
vôut  s   
 G0 
z1  z2 
Voltage
dˆ  s 
2
mode  s 
s
1   Rload D '2
Q0  0   z2  2
N DL
 s  s  s 
 1   1  
 1  
 z1   z
Current ˆvout  s 
 G0   2   z3 
mode
vˆc  s  D s
 Voltage mode or current mode, the RHPZ remains the same

Simulating the RHPZ
 To limit the effects of the RHPZ, limit the duty ratio slew-rate
 Choose a crossover frequency equal to 20-30% of RHPZ position
 A simple RHPZ can be easily simulated:
R1
10k
K1
C1
10n
SUM2
4 Vout(s)
Vin(s)
Vin 3 2 1
K2
X1
SUM2
K1 = 1
K2 = 1
E1
10k
R1  s 
Vout ( s )  Vin ( s )  Vin ( s )  Vin ( s ) 1  
1  0 
sC1

A Zero Producing a Phase Lag
 With a RHPZ we have a boost in gain but a lag in phase!
40.0
|Vout(s)|
20.0 +1
0
LHPZ
-20.0
s
-40.0 G (s)  1 
0
180 RHPZ
argVout(s)
90.0
0 s
G (s)  1 
-90.0 -90° 0
-180
1 10 100 1k 10k 100k 1Meg

frequency in hertz

Is There a RHPZ in DCM?
 A RHPZ also exists in DCM boost, buck-boost converters…
id (t)
Ipeak
D3Tsw
t
D1Tsw D2Tsw
Tsw
 When D1 increases, [D1, D2] stays constant but D3 shrinks

 The triangle is simply shifted to the right by d̂1
id (t)
Ipeak
D3Tsw
d̂1
t
D1Tsw D2Tsw
Tsw
 The refueling time of the capacitor is delayed and a drop occurs

 If D increases, the diode current is delayed by d̂1
7.00 340m
i(b2), i(b2)#a in amperes
5.00 300m id(t) d(t) 4

vduty in volts
Plot1
3.00 260m
1.00 220m
-1.00 180m d̂1 3

2
2.02m 2.04m 2.06m 2.09m 2.11m

time in seconds
7.05
1
6.95
vout in volts
Plot3
6.85
6.75
6.65 vout(t)
1.85m 1.99m 2.13m 2.27m 2.41m
time in seconds
7.05
vout(t)
6.95
vout in volts
Plot2
6.85
1
6.75
6.65
2.02m 2.04m 2.06m 2.09m 2.11m

time in seconds

A Large-Signal Model is Available
 Averaged models can predict the DCM RHPZ
L1
75u 10.0V
11
c
15.0V
vout
vôut  s 
 Hd
 
1  s sz1 1  s sz 2 
p
Vout
ˆ
d s  
1  s s p1 1  s s p 2 
10.0V PWM switch VM
R10
3
150m
Vin
10V
R11
1 Rload
a
15.0V 16 150
sz1  s z2 
X3
PWMVM
C5
1m
Cout RESR M 2L
L = 75u
Fs = 100k
2
vout 2M  1 1  11 M 
s p1  s p2  2 Fsw  
M  1 Cout RESR  D 
R1
50k
2.50V
5 Merci
LoL
2V M  1 Vatché!
278mV
1
1kH 278mV
8
H d  out
6 D 2M  1
Verr R3
CoL X2 10k
V2
1kF AMPSIMP
0V 2.5
10
V1x
AC = 1

The Model Predicts it!
 Averaged models can predict the DCM RHPZ
H d  28.75 dB
180 40.0
28.6 dB
f z1  1.06 kHz
90.0 20.0
f z2  141 kHz
fp1 f p1  4.2 Hz
0 0 f p2  47.1 kHz
fz2
-45°
-90.0-20.0
fz1 7
fp2
8
-180 -40.0
1 10 100 10k 100k 1Meg

4.2 Hz 1 kHz 47 kHz 141 kHz

Going to Variable Frequency
 More converters are using variable-frequency operation
 This is known as Quasi-Square Wave Resonant mode: QR
 Valley switching ensures extremely low capacitive losses
 DCM operation saves losses on the secondary diode
 Easier synchronous rectification
 The Right Half-Plane Zero is pushed to high frequencies
Smooth signals
iD  t  Less noise id  t 
vDS  t  Low CV² losses vDS  t 

What is the Principle of Operation?
 The drain-source signal is made of peaks and valleys
 A valley presence means:
 The drain is at a minimum level, capacitors are naturally discharged
 The converter is operating in the discontinuous conduction mode
V
480
360
Vin
240
valley
120 ton toff DT

0 vDS  t 
2.061m 2.064m 2.066m 2.069m 2.071m

A QR Circuit Does not Need a Clock
 The system is a self-oscillating current-mode converter
Vbulk Np:Ns
Vout
Demag Lp
detector +
. .
Cout
- 65 mV
Rload
.
Resr
S
Q
Q
Vdd R
Rpullup -
FB
GFB Rsense
CTR

A Winding is Used to Detect Core Reset
 When the flux returns to zero, the aux. voltage drops
 Discontinuous Mode is always maintained
Vbulk V Core is
.
800
reset vDS  t 
600
delay . . 400
200
I Lp  t  0
delay
V A
d
20 800m
I Lp  t  vaux  t 
10 400m
Vaux  N
dt 0 0
-10 -400m
-20 -800m  0
2.251m 2.255m 2.260m 2.264m 2.269m
set

The Frequency Linearly Changes
 As the peak current and the on-slope vary, Tsw changes
iLp  t 
Son , HL  Vin, HL L p Son , LL  Vin , LL L p
I peak ,max
P1
P2 Soff  Vout  V f  NL p
t
ton , HL ton, LL Tsw, HL Tsw, LL
I peak ,max
Soff  V f NL p
low rms currents in the MOSFET (weak stress)

t
Tsw
 Excellent behavior in short-circuit conditions!

The Excursion Can be Quite Large
 In heavy load low-line conditions, Fsw decreases
 In light-load and high-line operations, Fsw can go very high
80 3.4
70 3.2
Fsw 60
I peak 3
 kHz  50
A 2.8
40 2.6
30 2.4
100 200 300 400 100 200 300 400
Vin  V  Vin  V 
 EMI and switching losses are at stake as Fsw goes up
 Standby power obviously suffers from this condition

In a Bounded System Discrete Jumps
 As the load gets lighter, the frequency goes to the sky
 Modern controllers fold the frequency back with a VCO
 Problem, the only places to re-start are valleys: discrete jumps
Output
current

New Controllers Lock in the Valleys
 To prevent the noise, the NCP1380 locks the valley
 The current is allowed to move within a certain limit
 When it exceeds this limit, the controller selects a new valley
 As the load gets lighter, a VCO takes over and reduce Fsw
110
5 4th 3Fsw
rd versus
2ndPout at VINmin 1st
VCO
mode
4
810
Fsw (Hz)
4
610
4th 3rd 2nd 1st
4
410
VCO Pout decreases
mode Pout increases
4
210
0 20 40 60
Pout
 (W)

NCP1379/1380

Course Agenda


What is The Problem?
 A converter is designed to operate on wide mains – 85 to 265 V rms
 It can deliver a maximum power before protection trips
 The maximum power delivered at high line is larger than that at low line
Increase load
85 V rms to 265 V rms until protection
trip.

What Does the Standard Say?
 There is a test called Limited Power Source, LPS
 The maximum power the converter can deliver must be clamped
 If clamped, the manufacturer can use inferior fire proofing materials
Output Voltage
Output Current Apparent Power
Vout  V
Iout  A S  VA
Vrms Vdc
 20  20 8  5 Vout
20  Vout  30 20  Vout  30 8  100
- 20  Vout  60  150 Vout  100
19-V adapter, Iout,max = 5 A
IEC950 safety standard

Why the Power Runs Away in a Flyback?
Vin ,max
 The inductor current I peak  I peak ,max  t prop
Lp
slope increases at high I peak ,max I peak , HL
line. 0.8 Rsense
Vin High
S
Lp line
 The controller takes I peak , LL
time to react to an I Lp  t  Low PWM is reset
overcurrent situation. line
 The inductor current tdel

keeps growing until the CSout  t  Depends on
MOSFET turns off. drive capability
VGS  t  and MOSFET
 The overshoot is QG
larger at higher slopes
(High Vin)
t prop

The Effect in a DCM Converter
 A flyback converter operated in DCM obeys the formula:
1 I  Lp 
Pout  L p I peak ,max 2 Fsw
2 I peak ,max
Primary Max. peak Switching Converter

inductor current in frequency efficiency
fault t
 As Lp and Fsw are fixed, Ipeak,max changes with line input
Vsense Vin , LL Vsense Vin , HL
I peak ,max, LL   t prop I peak ,max, HL   t prop
Rsense Lp Rsense Lp
Low line High line
I peak Vin, HL  Vin, LL A 13.5% overshoot translates


I peak ,max, HL L pVsense in a 28% power increase
 Vin , LL 1.13
2
 1.28 ( is considered constant over the range)
t prop Rsense

The Power Increases at High Line
 Lp = 250 µH, Vsense = 1 V, tprop = 350 ns, Vin,LL= 120, Vin,HL = 370 V, Rsense =
0.33 Ω, Fsw = 65 kHz
65
60
63 W
Pout  W  55 Pout  17 W
50 46 W
 = 85%  = 89%
45
100 200 300 400
Vin  V 
 In this example, the converter stays DCM on the whole range.

How to Compensate the Runaway?
 How do we compensate this excess of power?
 we reduce the maximum peak current at high line
 this is called Over Power Protection – OPP
I peak I peak
I peak ,max I peak ,max  f Vin  I peak , LL
I peak , HL
Vin Vin
LL HL LL HL
 How to calculate the compensated high-line current?

 Equate low-line power with high-line power and solve for Ipeak
1 2
Pout ,max, HL  L p I peak ,max, HL Fsw HL
2
Solve for Ipeak

Reducing the Peak Current
 The final inductor peak current must equal:
2 Pout ,max, LL
I peak ,max, HL 
L p Fsw HL
 The compensated setpoint must subtract the prop. delay
Vsense Vin , HL
 I peak ,max, HL  t prop
Rsense Lp
 The amplitude of the sensed voltage must reduce by:
 Vin , HL 
V  Vsense   I peak ,max, HL  t prop  Rsense
 Lp 
 

For What Final Result?
 Thanks to the OPP, the power stays under control
70
63 W
60
Pout  W 
50
46 W
42 W 46 W Pout  4 W
40
100 200 300 400
Vin  V 

The CCM Case is a Different Picture
 In DCM, the valley current is zero, the stored energy is:
1 2
E  L p I peak ,max
2
 The peak current runaway, alone, affects the transmitted power
 In CCM, the valley current changes the formula:

1
E  L p  I peak ,max 2  I valley 2 
2
I L  p
I peak ,max
I valley
t

The Converter Changes its Operating Mode
 In fault mode, the converter operates in deep CCM at low line
 As the input voltage increases, the valley current decreases
I Lp  t 
I p ,max, LL Maximum current in fault
V out  Vf 
NLp
ELL Vin ,min
Lp
I p , valley , LL
Low line
ton , LL
t
I p ,max, HL Maximum current in fault
V
out  Vf 
Vin ,max NLp
EHL
Lp
I p , valley , HL High line

t
EHL  ELL 0 ton , HL

Computing the Transmitted Power in CCM
 First, we write the ton and toff equations in CCM
I Lp  t 
I peak
Vout  Vf 
NL p
Vin ,min
Lp
I valley
t
ton toff
Tsw
I peak  I valley
V
 in ton I valley  I peak 
V
out  Vf t Tsw  ton  toff
off
Lp NL p
(1) (2) (3)

Solving for the Valley Current
 By combining the 3 equations, we have:
L p  I peak  I valley  L p  I peak  I valley 
ton  toff  Tsw  ton  Tsw 
Vin Vin
 Replace toff in (2):
I valley  I peak 
V f  Vout  I valley Lp  I peak L p  TswVin 
L p NVin
 Solve for Ivalley: LL or HL
TswVin V f  Vout  I L  I peak  I valley TswVin V f  Vout 

I valley  I peak  I L 
L p V f  Vout  NVin  L p V f  Vout  NVin 
Vsense Vin
I peak ,max   t prop
Max fault Rsense L p
current

Identifying the Operating Mode
 Having the ripple on hand, we can confirm the mode:
I N I L
ton  L L p toff  Lp
Vin V
out Vf  I Lp  t 
I peak
ton  toff  Tsw CCM
I valley  0 I valley
ton t
I peak
ton  toff  Tsw
BCM
I valley  0
ton t
I peak
ton  toff  Tsw DCM DT
DT  Tsw  toff  ton
t
ton

Evaluating the Power in CCM
 Lp = 600 µH, Vsense = 1 V, tprop = 350 ns, Vin,LL= 120, Vin,HL = 370 V, Rsense = 0.33 Ω, Fsw = 65 kHz
1
Pmax, LL  L p  I peak ,max, LL 2  I valley , LL 2  Fsw LL  76 W
2
1
Pmax, HL  Lp  I peak ,max, HL 2  I valley , HL 2  Fsw HL  104 W
2
110
100
Pout  W  90 Pout  24 W
80
70
100 200 300 400
Vin  V 

Reducing the Peak Current at High Line
 If we lower the peak at high line, the ripple remains the same
I Lp  t 
I L I LCMP
I peak
I peak CMP
I valley
I valleyCMP
t
ton toff
Tsw
 We can re-write the flyback power formula to include the ripple

1
Pmax, HL  2

 L p I peak ,max, HL   I peak ,max, HL  I L , HL  Fsw HL
2
2
0 in DCM

We Want to Limit the High-Line Power
 We can force the high-line power to match that of low line
1
 2

Pmax, LL  L p I peak ,max, HL   I peak ,max, HL  I L , HL  Fsw HL
2
2
 From there, we can extract the compensated peak current value

Fsw L p HL I L , HL 2  2 Pmax, LL
I peak ,max, HL 
2 Fsw Lp HL I L , HL
 As this is the new setpoint, prop. delay contribution must be removed
 Vin , HL 
V  Vsense   I peak ,max, HL  t prop  Rsense
 Lp 
 
 After compensation, the peak current setpoint at high line becomes
Vsense  V Vin , HL
I peak ,max, HL   t prop
Rsense Lp

What is the Final Result?
 The high line power now respects the LPS limit
110
100 104 W
90
Pout  W 
80 75 W
76 W
Pout  6 W
70
70 W
60
100 200 300 400
Vin  V 

What Practical Solutions?
 There are several possibilities to reduce the peak current
1. Offset the current sense signal in the CS pin:
I  Lp 
I L , LL I L , HL
I peak ,max • easy to do
• affects the no-load
stand-by power
High line
• affects light-load
t efficiency
2. Reduce the peak limit as Vin increases
I  Lp  • implemented at IC level
I L , LL
I peak ,max, LL I L , HL
I peak ,max, HL • does not affect the no-
load stand-by power
• does not affect light-
High line load efficiency
t

Build an Offset on the CS Pin
 This offset must be proportional to the input voltage
Vbulk Vbulk
. Vcc
ROPP1 .
.
rotated . .
DRV Q1
DRV Q1
ROPP 2
ROPP1
CS
CS
R1 R1
C1 Rsense Rsense
C1
 Both options degrade light-load operation because of the offset

OPP Implementation in the NCP1250
 The NCP1250 implement a non-dissipative OPP circuitry
800 mV
off
600 mV PWM
on
reset
off
0 0 300-ns
blank
-200 mV
on
OPP CS
ROPPU
1 + 4
Aux. ROPPL 0.8 V

. 0.8 V
 The auxiliary swings to –Vin and reduces the setpoint  OPP

Checking the Results
 Let us check on a real 19-V adapter built with the NCP1250
Lp = 600 µH, Vsense = 1 V, tprop = 350 ns, Vin,LL= 120, Vin,HL = 370 V
Rsense = 0.33 Ω, Fsw = 65 kHz, Vclamp = 90 V, ll = 2.2 µH, N = 0.25
 Without any OPP compensation, we have:

I out ,max, LL  4.1A I out ,max, HL  5.7 A
 Once OPP has been implemented:

Pout , LL  72 W so I out , LL  3.8 A Pout , HL  78 W so I out , HL  4.1A

Course Agenda


Small-Signal Analysis
 Loop instability is a common issue in production
 Due to time pressure, designers often use trial and error
 no indication on design margins
 offenders are ignored, robustness is at stake
T s
G(s)
? T  s 
H(s) 10 100 1k 10k 100k
 Understand and counteract their variations when building G(s)

There are Two Options
 Analytical analysis of the power stage:
 best to see where the offenders are hidden (ESR, opto pole etc.)
 equations are complex but litterature abounds
 transfer function are for DCM or CCM
 difficult to predict transient response
 SPICE models:
 easy-to-implement averaged models
 can work in ac or transient mode
 easily transition between CCM and DCM
 do not explictly disclose the position of poles and zeros
A measurement on the bench is

mandatory, whatever you choose!

Analytical Analysis
 You must first characterize the "plant" transfer function
 what are your power stage ac characteristics?
Plant Vin  s  GVin  s 

+ I out  s  Z out  s 
+  d(s) -
Vref  G(s) vc(s)
H(s) + Vout  s 

Compensator
Vout  s  Vout  s 
H s  H s 
vc  s  d s
Current-mode control Voltage-mode control

How do we Stabilize a Converter?
 We need a high gain at dc for a low static error
 We want a sufficiently high crossover frequency for response speed
 Shape the compensator G(s) to build phase and gain margins!
T s
fc = 6.5 kHz
0° - 0 dB
T  s 
-88° GM = 67 dB
m = 92°
-180°
T  s   67 dB
10 100 1k 10k 100k 1Meg

How much phase margin to chose?
 a Q factor of 0.5 (critical response) implies a m of 76°
 a 45° m corresponds to a Q of 1.2: oscillatory response!
10
Q < 0.5 over damping
1.80 Q=5
Q = 0.5 critical damping
Q=1 Q > 0.5 under damping 7.5 Q
1.40
Q = 0.707
Asymptotically stable
1.00 5 m
600m
Q = 0.5 Fast response 2.5 76°
and no overshoot!
200m Q = 0.5
Q = 0.1 0
5.00u 15.0u 25.0u 35.0u 45.0u 0 25 50 75 100
 phase margin depends on the needed response: fast, no overshoot…

 good practice is to shoot for 60° and make sure m always > 45°

What Compensator Types do we Need?
 There are basically 3 compensator types:
 type 1, 1 pole at the origin, no phase boost
 type 2, 1 pole at the origin, 1 zero, 1 pole. Phase boost up to 90°
 type 3, 1 pole at the origin, 1 zero pair, 1 pole pair. Boost up to 180°
G s G s G s
boost
boost
270
G  s   270 270
G  s  G  s 
1 2 5 10 20 50 100 200 500 1k 10 100 1k 10k 100k 10 100 1k 10k 100k
Type 1 Type 2 Type 3

Fixed-Frequency Current-Mode
 First, check the operating mode, CCM or DCM?
2
 
Rload  Vin 
L p ,crit    Lp > Lp,crit ? Yes, CCM else DCM
2 Fsw N 2  V  Vout 
in
 N 
Vout
 Assume CCM, compute the duty-ratio: D 
Vout  NVin
Vout 2 Lp N 2
 Compute M and  L : M L 
NVin Rload Tsw
 Evaluate the dc gain and poles/zeros positions:
Rload 1
G0 
RsenseGFB N 1  D 2
 2M  1
 L

 Compute the poles/zeros positions: 3
2
1  D  1 D
1
f z2 
1  D  Rload L
f z1  f p1 
2 RESR Cout 2 DL p N 2 2 Rload Cout
 Check the quality coefficient at Fsw/2

Vin 1
Sn  Rsense Se   M c  1 S n Qp 
Lp   M c 1  D   0.5 
1 = no compensation
 Apply to formula to plot the ac response:
 s  s 
 1   1  
  1 Se 
H  s   G0  z1   z2 
Mc  1 n 
Tsw
 s  s s2 Sn
 1   1  2
3rd order  Q n
  p1  n p

 Extract the magnitude and the argument definitions
 2 2 
  f   f  
 1   1    
f
 z1  f
 z2  1
Hf  20 log10 G0 
 2 2 2 
  f    f 2   f  
1  
  f p  1   
  f n    f n Q p
 
  1    
 
 
 f   f   f   f 1 
arg H  f   tan 1    tan 1    tan 1    tan 1  
 fz   fz   fp  f nQp  
2
 1  2  1  f
 1    
  fn  
RHPZ
 Plot them with Mathcad® for instance.

 Extract the information at the selected crossover frequency
20
°
H s
10 100
Sub-harmonic
oscillations
dB
0 0
Damp poles
with Se
 10
H  s   100
 20
10 100 103 104 105 Hz
H  3kHz   16.3dB arg H  3 kHz   23

 The compensation strategy is the following:
 compensate the gain loss at fc so that: G  3 kHz   16.3dB
 evaluate the boost in phase at fc to get phase 70° margin:
Boost  PM  argH  f c   90  3.15

Boost = 0 select type 1 – origin pole
Boost < 90° select type 2 – origin pole, 1 pole, 1 zero
 k-factor can be used to place the pole and the zero
 boost  poles and zeros are coincident
k  tan   45   1
 2 
f c 3k
f pk 1  kf c  1 3k  3 kHz f zk 1    3 kHz
k 1
 Plot the compensator transfer function
80  180
G s
60  200
40
dB  220
°
20
 240
0
G  s   260
 20
10 100 10 3 10 4 10 5 Hz
 2 
  f  
 1   
  f zk 1  
  f   f   180
G f   20 log10 G boost   tan 1    tan 1  
  f 
2    f zk   f   
 f    1  pk 1 
1 
 f pk 0  f p  
  k1  

 Plot the loop gain transfer function and check the margins
100 0
T s
 100
50
fc = 3 kHz
dB °
 200
0
T  s   300
m  70
 360
 50
Hz
10 100 10 3 10 4 10 5
 Sweep ESR, Cout, Rload and verify the results

 In case the converter transitions to DCM, update the equation!
20
H s  
10
s s 
50 1   1
  z 
  z1  2 
0 H  s   G0
0  s  s 
1   1
  p 
 10
  p1  2 
 20  50
H  s 
 30
10 100 103 104 105
 Yes, analytical analysis is long and tedious.

 But, it teaches where the threats are and how to deal with!

Variable-Frequency Current-Mode
 Observing the waveforms helps us to derive an average model
Ia t  Ic t 
I peak I peak
I peak
Ic t  Tsw

2
dTsw Tsw
 It gives birth to a large-signal model
2 Ri Pout Vout  NVin 
Ia Ic Vc 
a c VinVout
d1.Ic Vc/(2*Ri) Vc Lp  1 N 
Tsw    
Ri  Vin Vout 
Sense 2P R
resistor d1  out i
p VcVin

 Linearization is needed to get a small-signal model
 Implement this small-signal model in a flyback configuration
v(c,p).kcp
a
ic.kic
X5
XFMR
RATIO = N
p
Vout
v(a,c).kac
Vin
Resr
ic
vc.kc
Rload
c
Cout
Lp
http://cbasso.pagesperso-orange.fr/Spice.htm

 Derive the transfer function and isolate poles and zeros
 s  s  1 2M  1
1  1  f p1 
   2 Rload Cout M 1
vôut  s  s s Rload Div
 G0  z1   z2 
G0  1
vˆc  s   s   2Vout  f z1 
1   2 NRi   1 2 RESR Cout
1st order  s p1 
NV
 in 
Rload 1
 Then plot the function f z2 
2 N 2 Lp M 1  M 
0
15
H  s   20
 40
dB 10
°
 60
5 Tailor G(s) to get

 80
H s the desired fc
0  100
3 4 5
1 10 100 10 10 10 Hz

Use a SPICE Model to Stabilize the Converter
PWM switch CM
vc
a
duty-cycle
DC 16
parameters 116mV
X2x
XFMR D1A
mbr20200ctp L1 R1
RATIO = -250m vint vout
Vout=19 340V 2.2u 20m 19.0V
vout
2 18 4 19.0V 20
p
Vin -78.4V 19.6V 19.0V
c
Ibridge=250u 340
Rlower=2.5/Ibridge AC = 0 0V R10 R15
Rupper=(Vout-2.5)/Ibridge 13 15m 85m
X9
19.0V 19.0V Rload
PWMCM Lp
(V(err)-1.2)/3 > 1 ? 1 27 20
Lp=600u L = Lp {Lp} 470mV
C5 C1
Fs = Fs 1 : (V(err)-1.2)/3
Fs=70k 6
2m 220u
Ri = Rsense B1
Rsense=0.5 Se = Se Voltage
Se=0
fc=1k Vdd
pm=60 5
5.00V
Gfc=-21 9 vint vout
pfc=-88
G=10^(-Gfc/20) Rled
{RLED}
boost=pm-(pfc)-90
pi=3.14159 R2
47k 2.50V
18.8V Cannot be
K=tan((boost/2+45)*pi/180)
Fzero=fc/k Verr
Rupper2
{Rupper}
beaten for
X3
Fpole=k*fc
2.61V
OP384X1 R3
47k 2.39V
LoL
1kH 2.39V X7
Optocoupler
simplicity
Rpulldown=4.7k 19 8 5
RLED=CTR*Rpulldown/G
Czero=1/(2*pi*Fzero*Rupper)
err UC384X
gnd
2V5
Cpole = 1/(6.28*pole*pullup)
CTR = CTR and speed!
Cpole=1/(2*pi*Fpole*Rpulldown)
17.6V
2.39V
CTR=0.9 15 Czero1
Cpole2
Pole=15k CoL
{Cpole}
10
{Czero}
1kF 2.49V
0V
11
14
X10
Vstim Rlower2
TL431_G
{Rlower}
Automate the AC = 1
R4
compensation! {Rpulldown}

Unveil the Transfer Function in a Second
dB °
40.0 180
H  s 
20.0 90.0
0 0
H s
-20.0 -90.0
-40.0 -180 Power stage gain
dB °
60.0 180 T s
30.0 90.0
m
0 0
T  s 
-30.0 -90.0 fc
-60.0 -180 Loop gain
10 100 1k 10k 100k

Course Agenda


How is regulation performed?
 Text books only describe op amps in compensators…
Vout
Verr
 The market reality is different: the TL431 rules!

Vout
I’m the
law!
Verr
TL431 optocoupler

The TL431 Programmable Zener
 The TL431 is the most popular choice in nowadays designs
 It associates an open-collector op amp and a reference voltage
 The internal circuitry is self-supplied from the cathode current
 When the R node exceeds 2.5 V, it sinks current from its cathode
K
R
K
TL431A R
A
2.5V
R
A
K
A
 The TL431 is a shunt regulator

A Rabbit and a (French) Snail…
 The TL431 lends itself very well to optocoupler control
Vdd Fast lane Slow lane
Vout
Vout
R pullup RLED R1 RLED
I1
VFB 1V
I LED I bias 
Rbias
Rbias Rbias
V f  1V
C2 C1 I1
TL431 Rlower
Vmin  2.5 V
dc representation
 RLED must leave enough headroom over the TL431: upper limit!

Understanding the Fast Lane Drawback
 This LED resistor is a design limiting factor in low output voltages:
Vout  V f  VTL 431,min

RLED ,max  R pullup CTR min
Vdd  VCE , sat  I bias CTR min R pullup
 When the capacitor C1 is a short-circuit, RLED fixes the fast lane gain
Vout  s 
RLED R1
Vdd VFB ( s )  CTR  R pullup  I1
I1
R pullup Vout ( s )
I1 
0V RLED
Ic in ac
VFB  s 
VFB ( s ) R pullup
Rlower  CTR
Vout ( s ) RLED
This resistor plays a role in dc too!

The Static Gain Limit
 Let us assume the following design:
5  1  2.5
Vout  5 V RLED ,max   20k  0.3
4.8  0.3  1m  0.3  20k
Vf  1V
VTL 431,min  2.5 V
Vdd  4.8 V
VCE , sat  300 mV RLED ,max  857 
I bias  1 mA
CTR min  0.3
R pullup  20 k 
R pullup 20
G0  CTR  0.3  7 or  17 dB
RLED 0.857
 In designs where RLED fixes the gain, G0 cannot be below 17 dB

You cannot “amplify” by less than 17 dB

Forbidden Compensation Areas
 You must identify the areas where compensation is possible
dB °
40.0 180
Not ok
Requires
less
f c  500 Hz
20.0 90.0 H s than 17 dB
of gain
0 0
-17 dB
-20.0 -90.0
arg H  s 
Requires
-40.0 -180
ok 17 dB
or more
10 100 500 1k 10k 100k

Injecting Bias Current
 Make sure enough current always biases the TL431
 If not, its open-loop suffers – a 10-dB difference can be observed!
> 10-dB difference
Ibias
Easy
Ibias = 1.3 mA solution
Rbias
Ibias = 300 µA
1
Rbias   1 k
1m

Small-Signal Analysis
 The TL431 is an open-collector op amp with a reference voltage
 Neglecting the LED dynamic resistance, we have:
Vout  s  Vout  s   Vop  s 

I1  s  
RLED
1
RLED R1 sC1 1
Vop  s   Vout  s   Vout  s 
Rupper sRupper C1
C1
I1
1  1 
I1  s   Vout  s  1  
0 RLED  sRupper C1 
We know that: VFB ( s )  CTR  R pullup  I1

Rlower
Vop  s  VFB  s  R pullup CTR 1  sRupper C1 
  
Vout  s  RLED  sR C
upper 1  

Creating a High-Frequency Pole
 In the previous equation we have:
R pullup
 a static gain G0 = CTR
RLED
1
 a 0-dB origin pole frequency  po 
C1 Rupper
1
 a zero z  1
Rupper C1
 We are missing a pole for the type 2!
Vdd
Type 2 transfer function
R pullup
Add a cap. from
VFB  s  collector to ground
VFB  s  R pullup CTR  1  sRupper C1 
  
C2 Vout  s  RLED  sRupper C1 1  sR pullup C2  

Understanding the Optocoupler Pole
 The optocoupler also features a parasitic capacitor
 it comes in parallel with C2 and must be accounted for
Vout(s)
Vdd
Rpullup
VFB(s) FB
c
C
Copto
C2  C || Copto e optocoupler

Extracting the Pole
 The optocoupler must be characterized to know where its pole is
Cdc Rled
Ic 10uF 20k
2 5
Rpullup O  s 
20k
Rbias
VFB 1 3
Vdd
5
X1 4 6
SFH615A-4 O s
Vbias Vac
IF
-3 dB
4k
 Adjust Vbias to have VFB at 2-3 V to be in linear region, then ac sweep

 The pole in this example is found at 4 kHz
1 1 Another design
Copto    2 nF constraint!
2 R pullup f pole 6.28  20k  4k

The TL431 in a Type 1 Compensator
 To make a type 1 (origin pole only) neutralize the zero and the pole
VFB  s  R pullup CTR  1  sRupper C1 

  
Vout  s  RLED  sRupper C1 1  sR pullup C2  
R pullup substitute 1
sRupper C1  sR pullup C2 C1  C2  po 
Rupper Rupper RLED
C1
CTR CTR R pullup CTR
 po  C2 
C2 RLED 2 f po RLED
 Once neutralized, you are left with an integrator
1 f po CTR
G s  | G  f c  | f po  G fc f c C2 
s fc 2 G fc f c RLED
 po

A Type 1 Design Example
 We want a 5-dB gain at 5 kHz to stabilize the 5-V converter
Vout  5 V
Vf  1 V
VTL 431,min  2.5 V Apply 15%
margin
Vdd  4.8 V
RLED ,max  857  RLED  728 
VCE , sat  300 mV
I bias  1 mA
CTR min  0.3
R pullup  20 kΩ
5
G fc  10 20
 1.77 CTR 0.3
C2    7.4 nF
f c  5 kHz 2 G fc f c RLED 6.28  1.77  5k  728
Copto = 2 nF
R pullup
C  7.4n  2n  5.4 nF C1  C2  14.7 nF
Rupper

Simulation of the Type 1
 SPICE can simulate the design – automate elements calculations…
parameters
Vout=5
Vf=1
Vref=2.5
VCEsat=300m
Vdd=4.8 E1
Ibias=1m Vdd -1k
{Vdd} L1
A=Vout-Vf-Vref 4.99V 1k 4.99V
4.80V 4.99V
B=Vdd-VCEsat+Ibias*CTR*Rpullup err
Rmax=(A/B)*Rpullup*CTR 6 5 7
Rpullup RLED R2 R5 2.50V

Rupper=(Vout-2.5)/250u
fc=5k {Rpullup} {RLED} {Rupper} 100m 9
Gfc=-5 2.50V 4.99V
2.50V
3.97V 2 10
G=10^(-Gfc/20) VFB 4 3 B1
pi=3.14159 C3
1k Voltage V2
R6 0V V(err)<0 ?
Fpo=G*fc 1k 2.5
0 : V(err)
C1
Rpullup=20k {C1} V3
Cpole 2.96V AC = 1
RLED=Rmax*0.85 {Cpole} 1
C1=Cpole1*Rpullup/Rupper
X2
Cpole1=CTR/(2*pi*Fpo*RLED)
Optocoupler
Cpole=Cpole1-Copto Cpole = Copto X1
R3
10k
Automatic bias
CTR = CTR TL431_G
Fopto=4k
Copto=1/(2*pi*Fopto*Rpullup)
point selection
CTR = 0.3

Type 1 Simulation Results
 The pullup resistor is 1 k and the target now reaches 5 dB
dB
20.0
G s
10.0
5 dB
0
-10.0
-20.0
°
270
arg G  s 
180
90.0
-90.0
100 200 500 1k 2k 5k 10k 20k 50k 100k

The TL431 in a Type 2 Compensator
 Our first equation was already a type 2 definition, we are all set!
Vdd
Vout R pullup
R pullup RLED G0 = CTR
R1 RLED
VFB 1
z1 
Rbias R1C1
C2 C1 1
p 
1
R pullup C2
TL431 Rlower
 Just make sure the optocoupler contribution is involved…

Deriving Component Values for the Type 2
 You need to provide a 15-dB gain at 5 kHz with a 50° boost
f p   tan  boost   tan 2  boost   1  f c  2.74  5k  13.7 kHz

 
R pullup
f z  fc 2
f p  25k 13.7k  1.8 kHz G0 = CTR  1015 20  5.62
RLED
 With a 250-µA bridge current, the divider resistor is made of:
Rlower  2.5 250u  10 kΩ R1  12  2.5  250u  38 kΩ
 The pole and zero respectively depend on Rpullup and R1:

C2  1 2 f p R pullup  581 pF C1  1 2 f z R1  2.3 nF
 The LED resistor depends on the needed mid-band gain:
R pullup CTR ok
RLED   1.06 kΩ RLED ,max  4.85 kΩ
G0

Checking the Optocoupler Contribution
 The optocoupler is still at a 4-kHz frequency:
C pole  2 nF Already above!
 Type 2 pole capacitor calculation requires a 581-pF cap.!
The bandwidth cannot be reached, reduce fc!

 For noise purposes, we want a minimum of 100 pF for C
 With a total capacitance of 2.1 nF, the highest pole can be:
1 1
f pole    3.8 kHz
2 R pullup C 6.28  20k  2.1n
 For a 50° phase boost and a 3.8-kHz pole, the crossover must be:
fp
fc   1.4 kHz
2
tan  boost   tan  boost   1

Placing the Zero in the Transfer Function
 The zero is then simply obtained:
fc 2
fz   516 Hz
fp
 We can re-derive the component values and check they are ok
C2  1 2 f p R pullup  2.1 nF C1  1 2 f z R1  8.1 nF
 Given the 2-nF optocoupler capacitor, we just add 100 pF
 In this example, RLED,max is 4.85 k

R pullup 20
G0  CTR  0.3  1.2 or  1.8 dB
RLED 4.85
 You cannot use this type 2 if an attenuation is required at fc!

TL431 type 2 Design Example
 The 1-dB gain difference is linked to Rd and the bias current
dB
30.0
G s
20.0
10.0
0
14 dB @ 1.4 kHz
-10.0
°
140 arg G  s 
130
120
50°
110
100
10 100 1k 10k 100k

Design Example 1 – a Single-Stage PFC
 The single-stage PFC is often used in LED applications
 It combines isolation, current-regulation and power factor correction
 Here, a constant on-time BCM controler, the NCP1608, is used
141V
1 19 1 V = 1 µs
PWM switch BCM

duty-cycle
598mV
vc
a
Dc 2
68.4V X2 Vout
Fsw (kHz)
XFMR
Fsw 5
3.09V -210V
RATIO = -250m
52.5V
Iout = 2.4 A
8.74V
7 8
Ip
V1
p
Ip
6
c
{Vrms*1.414} 154mV
3
R2 R7
X1
GAIN
R1 X5 50m 65k
PWMBCMVM 100m K = Gpwm D4
L=L 52.5V 26.9V
50 V
GAIN 1N965
0V
9 11 2 A string
4
1.57V
22 C5
B1 C1
L1 2.2mF 0.1uF
Voltage Rsense
{L}
V(errac)-0.6 0.5 1.24V
23
Vsense
parameters Vdd
15.1V
{Vdd} 1.25 V ILED
1.24V
Vrms=100
5.00V
14
R5
10
R4
Ac out
L=400u {RLED}
18 {Rupper}
VFB R6
Ct=1.5n
LoL {Rpullup}
Icharge=270u errac
1k 2.17V 2.17V 12.2V
Gpwm=(Ct/Icharge)*1Meg 2.17V 29 17 16
X4
Optocoupler
On-time CoL
1k C2 11.1V
Cpole = Copto
CTR = CTR
C4
{C1}
R9
{R2}
0V
selection 20
AC = 1
{C2} 13
1.24V
28
ac in V3
15
X3
TLV431
1.24V
Average simulation

 Once the converter elements are known, ac-sweep the circuit
 Select a crossover low enough to reject the ripple, e.g. 20 Hz
dB 0
8.00
H s -2.5 dB
4.00
20 Hz
0
-4.00
-8.00
°
80.0
40.0
arg H  s  -11°
0
-40.0
-80.0
1 2 5 10 20 50 100 200 500 1k

 Given the low phase lag, a type 1 can be chosen
 Use the type 2 with fast lane removal where fp and fz are coincident
dB
2
20.0
1
10.0
13
fc = 19 Hz
0
15 V 0.5  -10.0
3
-20.0
T s
5V 10
°
11
6.1 kΩ 10 kΩ 180
ton
generation 20 kΩ 90.0
7 6 m = 90°
0
586 nF 13.6 kΩ
395 nF 4 12 -90.0
argT  s 
5
-180
G s 1 2 5 10 20 50 100 200 500 1k

 A transient simulation helps to test the system stability
6.00
4.00
2.00
2.2 A
0
-2.00
I LED  t 
5.00
4.60
VFB  t 
4.20
3.80
3.40
4.00
2.00
-2.00
-4.00
I in  t 
20.0m 60.0m 100m 140m 180m Vin = 100 V rms

Design Example 2: a DCM Flyback Converter
 We want to stabilize a 20-W DCM adapter
 Vin = 85 to 265 V rms, Vout = 12 V/1.7 A
 Fsw = 65 kHz, Rpullup = 20 kΩ
 Optocoupler is SFH-615A, pole is at 6 kHz
 Cross over target is 1 kHz
 Selected controller: NCP1216
1. Obtain a power stage open-loop Bode plot, H(s)

2. Look for gain and phase values at cross over
3. Compensate gain and build phase at cross over, G(s)
4. Run a loop gain analysis to check for margins, T(s)
5. Test transient responses in various conditions

 Capture a SPICE schematic with an averaged model
839mV
vc
a
PWM switch CM
389mV
duty-cycle
DC 6
X2x
XFMR D1A
RATIO = -166m mbr20200ctp vout
90.0V 12.0V
vout
2 3 4
Vin p -76.1V 12.6V
c
90
AC = 0 R10
0V
13 20m
X9
Rload
PWMCM L1 12.0V
V(errP)/3 > 1 ? 1 7.2
L = Lp {Lp}
Fs = 65k 1 : V(errP)/3 C5
8
Ri = 0.7 3mF
Se = Se B1
Voltage
Coming from FB
 Look for the bias points values: Vout = 12 V, ok

 Observe the open-loop Bode plot and select fc: 1 kHz
dB °
H s
40.0 180
20.0 90.0
Phase at 1 kHz
-70 °
0 0
-20.0 -90.0
arg H  s 
-40.0 -180
Magnitude at 1 kHz
-23 dB
10 100 1k 10k 100k

Design example 2: a DCM flyback converter
 Apply k factor or other method, get fz and fp
 fz = 3.5 kHz fp = 4.5 kHz
Vout(s)
Vdd 2 kΩ 38 kΩ
20 kΩ
VFB(s) 10 nF
k factor FB
gave
2.5 nF
C  3.8 nF 10 kΩ
install Copto  1.3nF
C2  3.8n  1.3n  2.5 nF

Design example 2: a DCM Flyback Converter
 Check loop gain and watch phase margin at fc
4
° dB
180 80.0 T s
90.0 40.0 arg T  s 
m = 60°
0 0
-90.0 -40.0
Crossover
1 kHz
-180 -80.0
10 100 1k 10k 100k

 Sweep ESR values and check margins again
12.04 Vout(t)
High
12.00
line
11.96
11.92 100 Low

mV
line
11.88
200 mA to 2 A in 1 A/µs
3.00m 9.00m 15.0m 21.0m 27.0m

Conclusion
 The flyback converter hides several parasitic elements

 Understanding where they hide and how they move is key!
 Despite CM overwhelming presence, QR designs grow
 CM is a 3rd-order system whereas QR is 1st order
 TL431 lends itself well for compensation, watch the optocoupler!
 SPICE eases and speed-up the design
 Always check theoretical assumptions with bench measurement
Merci !
Thank you!
Xiè-xie!

Flyback Chris Basso APEC Seminar 2011

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Flyback Chris Basso APEC Seminar 2011

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The Dark Side of Flyback

1 • Chris Basso – APEC 2011

 The Flyback Converter

2 • Chris Basso – APEC 2011

 Seminars are usually highly theoretical – link to the market?

 Industrial requirements usually not covered: standby, over power…

 This 3-hour seminar will shed lights on less covered topics:

 Why the converter delivers more power than expected? Solutions?

 Books talk about compensation with op amps, I have a TL431!

 Quasi-resonant converters presence increases, how do they work?

 In a 3-hour course, we are just scratching the surface…!

3 • Chris Basso – APEC 2011

4 • Chris Basso – APEC 2011

buck-boost buck-boost flyback

 The addition of a transformer brings:

5 • Chris Basso – APEC 2011

 The current increases in the inductor in relationship to Vin and Lp

6 • Chris Basso – APEC 2011

IC Apply volt-second balance

ton = DTsw toff = (1-D)Tsw

Vout Nton NDTsw ND

VDS ,off  Vin

8 • Chris Basso – APEC 2011

V2 4 0 PULSE 0 5 0 10n 10n 3u 10u

 It will run open loop for simplicity, Vout  8 V

9 • Chris Basso – APEC 2011

250 Diode blocks

12.0 Ipeak / N Id(t)

CCM flyback – no parasitics

10 • Chris Basso – APEC 2011

DCM (core reset) Epeak

12.640 Output voltage

2.00 Ipeak / N Id(t)

DCM flyback – no parasitics

11 • Chris Basso – APEC 2011

 Power (W) is energy (J) averaged over time (s):

12 • Chris Basso – APEC 2011

 The Flyback Converter

13 • Chris Basso – APEC 2011

14 • Chris Basso – APEC 2011

12.0 Id(t) Diode current

CCM mode – with parasitics

15 • Chris Basso – APEC 2011

200m Ipeak Iin(t) Input current

300m DCM (core reset)

DCM mode – with parasitics

16 • Chris Basso – APEC 2011

17 • Chris Basso – APEC 2011

CD0 is the cap. for VDS = V0

18 • Chris Basso – APEC 2011

 The energy lost is smaller with the non-linear variation!

19 • Chris Basso – APEC 2011

20 • Chris Basso – APEC 2011

 Some induction lines couple in the air: leakage flux

21 • Chris Basso – APEC 2011

 This is commonly known as the "PI" model

22 • Chris Basso – APEC 2011

 The turns ratio is usually normalized to the primary

23 • Chris Basso – APEC 2011

 During the on-time, both Lp and lleak store energy

24 • Chris Basso – APEC 2011

 The leakage inductor current fills up the drain lump capacitor

25 • Chris Basso – APEC 2011