Session 2 – Topologies and Control

Hybrid Switched Capacitor Converters:

Topologies, Trends, and Comparison
Jason T. Stauth
Associate Professor of Engineering
Thayer School of Engineering at Dartmouth
Co-Director of NSF I/UCRC:
Power Management Integration Center PMIC

1
High-Density Power Management
Applications that demand: high density + efficiency

Application Trends

Mobile Devices & Pressure on battery life,

Communication size, cost, # converters

Performance # cores, density,

Electronics/Comp. integration, parasitics

Renewable Energy, Extreme cost pressure,

Automotive reliability
2
 Passive Component Density Considerations
*Murata class II ceramic
Cap. Energy Ind. Energy (w/ factor in derating)

0603
Capacitors

0402
%
% 𝐵&'$
∝ 𝜀 # 𝐸!"#$ # 𝑉𝑜𝑙 ∝ # 𝑉𝑜𝑙

0201
𝜇
Relatively higher Relatively lower

Inductors
General tradeoffs: winding and core *coilcraft/murata SMD
loss, thermal and saturation limits… (w/ factor in Isat/Imax)

• Inductors have both lower efficiency

and lower power density at small size!
• Always better with ‘physically larger’
magnetic components
[Sullivan et al., On size and magnetics: Why small
efficient power inductors are rare, 3D-PEIM, 2016]
[Kyaw et al., Fundamental Examination of Multiple
Potential Passive Component Technologies.., TPEL3 ’18]
 High Density Power Conversion
S1 LX VOUT àReduce passive component volume
VIN i
S2 COUT IOUT
n Strategy 1: Increase frequency
+ Good: Smaller inductor, capacitor
DV 𝑉#𝑠 – Bad: Increase in frequency dependent
Di pp µ losses (winding, core, gate drive etc.)
f sw L 𝐻

Di pp 𝐴#𝑠 n Strategy 2: Change Architecture

Dvout , pp µ
𝐹 n Reduce inductor ΔV
f swCout
n Reduce output cap ΔI
e.g. Interleaving
n Multiply ‘effective’ frequency
 Hybrid/Resonant SC Converters [Ye, Sanders, and
Pilawa, COMPEL ’19]

Switched Capacitor Stage + Inductor(s)

IL
• High energy density SC network à reduce inductor ∆𝑽
à much smaller inductor and/or energy storage requirements
L
C • Inductor à eliminate ‘charge sharing’ in SC stage
SC Stage VOUT
à Higher efficiency (lower cond. loss and lower sw. frequency)
à Higher power density (smaller passive component volume,
better utilization of semiconductor devices)
Buck Converter ReSC ReSC
95% efficiency (partially integrated) (fully integrated)
85% efficiency

Volume
97% efficiency Buck
[Renz & Wicht

>250 mm2 ISSCC ‘19] + 3-level

[Mclaughlin &
Stauth ISSCC ‘20]
+ + 4-level
~80 mm2 <10 mm2 Loss
[Din & Stauth TPEL ‘17] [Schaef & Stauth ISSCC ‘17]
[Stupar et al., Prodic and Taylor TPEL ‘19]
 Switched Capacitor ‘Base’ Classes
Ladder Dickson
Series Parallel Dickson/Ladder
VIN
VIN VOUT
VOUT
𝝋𝟐
VIN

𝝋𝟏 1 VOUT VOUT
VOUT
Perspective: Perspective:
• Min cap (dielectric) volume to block VIN-VOUT • Min switch rating (area etc.) to block VIN-VOUT
• ..But requires switches to absorb high • ..But requires capacitors to absorb high
voltage stress voltage stress

• Best capacitor (passive) utilization • Worst capacitor (passive) utilization

• Worst switch utilization • Best switch (active) utilization
[Seeman & Sanders, TPEL ’08] 6
 Other Common Examples
Cascaded (doubler) Multiphase operation @multiphase operation:
VIN • Intermediate utilization
VOUT VIN • Highest VCR per cap
4 2 1 VOUT
of ‘any’ SC topology

[Ye et al., “The Cascaded Resonant Converter…” TPEL ’20]

[Xia et al., “A Two-Stage Cascaded Hybrid Switched-Capacitor…” ISSCC ’21]

Flying Capacitor Multilevel FCML Multiphase operation

VOUT • Dickson-like charge
VIN 1 2 1 multiplier
VOUT
VOUT • Intermediate utilization
• Multilevel = diff’t VCRs
VIN 3 3 2
VOUT VOUT • Effective fsw multiple.
[Meynard PESC ’92, many other more recent]
7
 Hybrid/Resonant Operation
Resonant Switched Capacitor (ReSC): PWM Regulated (Hybrid)
VIN
VIN
PWM
SC Stage SC Stage
IL IL IL
VX VOUT VX VOUT
LX LX VX
CEFF IOUT CEFF IOUT VOUT

(shown for series-parallel)

φ0 φ0
IL

t
[Pasternak et al., “Modeling and Performance Limits of [Lei et al., “A General Method for Analyzing Resonant and
Switched-Capacitor DC–DC Converters Capable of Soft-Charging Operation of Switched-Capacitor
Resonant Operation with a Single Inductor,” JESTPE ’17] Converters,” TPEL ’15] 8
 Other Considerations: Hybrid/Resonant πIDC/2 iLx indirect

t
Direct vs indirect conversion [Schaef TPEL ’18; Kesarwani TPEL’15]
VDD VDD

πIDC/2
iLx direct • Power loss in inductor
t
(depends on current PSD)
vs • Voltage stress limits
πIDC/2 iCbp
iLx indirect
-IDC/2
t (difft. for direct vs indirect)
t • Multimode Operation
[Kesarwani APEC ’15] (CCM à DCM, Resonant vs PWM)
πIDC/2
iLx direct
Bypass (decoupling) capacitance Flying Capacitor Voltage Balance
Vin Iin,dc t
VOUT ¼ VIN
iCbp
iin,ReSC t Vx
-IDC/2 C +
io -
iio Iout
+ iout,ReSC iL
Cig iig ReSC Vout
-
Converter • Inductor ‘decouples’ flying capacitor voltages
Cog
+
iog Iout,dc
• High-order system dynamics, voltage drift
-
• Imbalance à higher voltage stress & ripple
[Rentmeister COMPEL ’17] [Meynard, Prodic, Corradini, Ruderman, Reusch, etc. ]
 Topology Comparison
Many possible hybrid-SC topologies, Which is best?
Vin Vin Vin

SN 1x 1x SN* Φ1
Φ2 (N-1)x
Φ1 Φ2
CN-1
1x 1x Φ1
CN-1
• Active device utilization?
CN-1
CN-1

(N-1)x 1x (N-1)x
(N-1)x
Φ1 1x 1x
(N-1)x
Φ2 • Passive component utilization?
• Other considerations?
(N-1)x Φ2

S3 1x 1x S3* 1x
Φ1 Φ1
Φ2 1x 1x Φ1
C2
2x
C2
1x
2x
C2
2x
Φ1
2x
C2
Exercise: Pasternak, Kiani, McLaughlin
1x 1x Φ2
2x Φ2 [Compel ’17,’18; TPEL ‘21]
S2 1x 1x S2 *
Φ1 1x Φ1
C1
Φ2 1x 1x Φ1
C1
• Minimum power loss FOM
C1 C1

1x
1x
1x
1x
1x
Φ1 1x Vout 1x
1x
Φ2 (active devices and inductor)
Φ2
S1 1x
Vx
1x S1*
1x Vx
IL
Φ2 1x 1x Φ1
IL
• Size constraints on passive
IL IL Φ1 1x 1x Φ2
components
Vout Vout
[McLaughlin et al., “Analysis and Comparison of Hybrid-
FCML Series Parallel Dickson Resonant Switched-Capacitor DC–DC Converters With
(Direct) (Direct) (Indirect) Passive Component Size Constraints,” TPEL ’21]
 Comparison Development: minimum
power loss in arbitrary dc-dc converter
Φ2
Vin

(N-1)x
*V
PSW = in
å
iÎswitches
Psw* ,i V= 2 Rsp 0 Esp 0 ´ V f sw
SN
in in

ΦiÎ
å
switches
I rms ,i × vra,i/2
Φ2 1x 1x 1
Φ1 Φ1 SN 1x 1x SN* 1x SN* CN-1 CN-1
CN-1 CN-1 1x CN-1 Charge multiplier Switch voltage rating
Convex optimization, Φ1 1x Φ2
1x
(DC current)
Vx
(N-1)x
Φ2
(N-1)x
optimal switch sizing
1x RMS/DC ratio
S3
Modified Sum(AV)

å
1x S3 1x 1x S3* 2x S3*

b r ,i ar ,i vra,i/2
Φ1 Φ1
P *
= 2 I out Rsp 0 Esp 0 ´ f sw
Φ2 1x 1x Φ1
C2 C2 1x C2 C2 C2
2x 2x SW
Φ
Φ2
Vx
1x iÎswitches
1 1x 1x Φ2

S2 1x 1x S2* S2 2x S2* Φ2 1x
Φ1 1x Φ1 1x Φ1
C1 C 1x C1
C1 α =C Voltage scaling parameter
1

1x 1x DC load current
1
Φ1 1x Vout 1x Φ2
Φ2
Baseline Specific
1x IL α ≈ 3I L
CMOS (constant field)
S1 1x 1x * 1x *
S1 Relative/normalized Φ2 1x 1x Φ1
Vx Vx Parameters
S1 Vx S1
1x
switching frequencyΦ1
α≈2 CMOS (cascode)
IL IL IL 1x 1x Φ2
(depends on L & C) 0<α<2 GaN, SiC, discrete Si
Vout Vout Vout
(a) Series Parallel [Kiani, Compel
(b) FCML ’18] (c) Dickson (d) Stacked-Ladder (Dickson)
@ 𝛼 = 0 →All devices same rating
11
 Comparison Development: minimum
power loss in arbitrary dc-dc converter
Active device @Same VCR, Iload, fsw: Topology with
lowest ∑𝛽𝑎𝑣 achieves lower loss; better
utilization:
use of available semiconductor Rsp*Esp

Same total energy, area,

volume, voltage/current
*
PSW µ f sw å
iÎswitches
b r ,i ar ,i vra,i/2
Rsp Esp µ vra
ripple limit, etc
α = Voltage scaling parameter
Passive Component Utilization
α≈3 CMOS (constant field)
@Same total passive component size: Deliver
more energy/cycle or same same Iload at lower fsw α≈2 CMOS (cascode)

à better use of available passive energy 0<α<2 GaN, SiC, discrete Si

@ 𝛼 = 0 →All devices same rating

12
Active and Passive Component Utilization
~similar to MSSL and MFSL metrics in [Seeman TPEL ’08]

Passive Component Utilization:

𝒇∗𝒔𝒘 @ fixed total cap volume, same L Device Utilization: ∑ 𝛽𝑎𝑣
el
arall
ri es-P
* * * Se
son * ML
Dick FC
Lower Lower
is is
better
FCML better

Series-Parallel Dickson

*Dickson Topologies: 1. Split Phase Dickson: [Lei & Pilawa, TPEL ’16]
à Competing ‘dual’ advantages: 2. Stacked Ladder: [Li & Sanders, ECCE ’16]

à Dickson has better use of switches Combine for Full Comparison

à SP has better use of Capacitors 13
 Combined Performance Limits
@ Same total inductance (fixed L), not including losses in inductor
Same Total Capacitor Volume (or Energy) Same Total Capacitor Area

rallel
-Pa ML
ML ri es
FC
F C Se
el
Lower
s-P arall Lower
is Serie is
better better

Dickson Dickson

à Competing ‘dual’ advantages: Dual Advantages offset

à Dickson has better use of switches Compress performance differences
à SP has better use of Capacitors …But this doesn’t consider inductor loss
14
 Combining Inductor Losses, Consider Inductor Sizing
Note: switches everywhere ∗ 1
optimized (min loss @ each fsw) 𝑃$-$'. ∝ ∗ 1/3
+ 𝛽",# 𝑎",# 𝑣",#
𝐶/00 𝐿
∗
𝐶!"" = 𝑓𝑖𝑥𝑒𝑑 𝐿 = scaling for
SC Follows:
(same SC stage) resonance @ 𝑓$%
[H.-P. Le, JSSC ’11]
Pur
eS
Power Loss (normalized)

Boundary
FSL/SSL
~Q

Ideal inductor model

-1
PMIN µ f SW µ L 4
ReSC
fsw/fFSL 15
 Combining Inductor Losses, Consider Inductor Sizing
Note: switches everywhere ∗ 1 [Scaling Laws: Perreault et
optimized (min loss @ each fsw) 𝑃$-$'. ∝ ∗ 1/3
+ 𝛽",# 𝑎",# 𝑣",# al and Sullivan, APEC ‘09]
𝐶/00 𝐿
∗ @ fixed volume, scale #
𝐶!"" = 𝑓𝑖𝑥𝑒𝑑 𝐿 = scaling for turns, fixed L/R ratio
SC Follows:
(same SC stage) resonance @ 𝑓$%
[H.-P. Le, JSSC ’11]
Pur
eS
Power Loss (normalized)

ß
Hi
C Realistic inductor
gh
er (fixed size, fixed L/R)
@

Boundary
FSL/SSL
L
fix Optimum L
ed Lo (or # turns)
s w
ize er L @fixed volume
à
~Q

Ideal inductor model

-1
PMIN µ f SW µ L 4
ReSC
fsw/fFSL 16
 Combining Inductor Losses, Consider Inductor Sizing
Note: switches everywhere ∗ 1 [Scaling Laws: Perreault et
optimized (min loss @ each fsw) 𝑃$-$'. ∝ ∗ 1/3
+ 𝛽",# 𝑎",# 𝑣",# al and Sullivan, APEC ‘09]
𝐶/00 𝐿
∗ @ fixed volume, scale #
𝐶!"" = 𝑓𝑖𝑥𝑒𝑑 𝐿 = scaling for turns, fixed L/R ratio
SC Follows:
(same SC stage) resonance @ 𝑓$%
[H.-P. Le, JSSC ’11]
Pur Optimum design lives
eS
Power Loss (normalized)

ß C just above ideal curve

Hi Smaller = Lower L/R
gh
@ er

Boundary
FSL/SSL
L
fix
ed Lo
s we
ize rL
à
Larger Smaller
Increasing
inductor volume
Ideal inductor model
-1
PMIN µ f SW µ L 4
ReSC Larger = Higher L/R

fsw/fFSL 17
 @ Fixed Total Passive Component Size
@Large C, Small L: @Large L, Small C: Optimal Sizing
[Kiani COMPEL ’18]
[McLaughlin TPEL ’21]

• More loss in L • Lower loss in L

• Higher fsw • Higher fsw • Minimum total loss
• Higher Loss • Higher Loss • Generally minimizes fsw
[McLaughlin et al., “Analysis and Comparison of Hybrid-Resonant Switched-Capacitor
DC–DC Converters With Passive Component Size Constraints,” TPEL ’21] 18
 Assume Fixed Total Passive Component Size
Optimal Inductor Volume / Total Volume Optimal Sizing
Winding DC-resistance dominant [Kiani COMPEL ’18]
40% [McLaughlin TPEL ’21]
𝑉𝑜𝑙, 𝑇𝑜𝑡𝑎𝑙

35%
𝑉𝑜𝑙, 𝐿

ore Loss)
on C
30% r (D epends
o
red-Induct
Co
25% Winding AC-resistance dominant

2 2.2 2.4 2.6 2.8 3.0 • Minimum total loss

Steinmetz Parameter, β • Generally minimizes fsw
Takeaway: Inductor
𝑃&'() is
= 𝑘~25% , , to
, 𝑓*+ 𝐵𝜷~40% of total Volume
Depends on ‘how losses scale:’ DC & AC resistance, core loss etc. 19
Topology Comparison (Fixed Passive Volume)
Inductor DC resistance loss model

on
Dicks
arallel
Series-P Dickson

𝛼" = 1 𝛼" = 2 𝛼" = 3

(GaN/SiC etc.) (Cascode scaling) (Constant field scaling)

Series Parallel Better Dickson-Based Better

 Topology Comparison (Fixed Passive Volume)
Versus 𝜶𝒓 @ N = 4:1 Step Down VCR

3 N = 4:1

FOM,DC (Normalized)
2.5 FCML

Dickson
2
-P arallel
s
Serie
1.5
0 1 2 3
∝𝒓 (switch scaling parameter)

@𝛼( = 0, All same switches @𝛼( = 2, Cascode scaling: @Long-channel (constant field):
• Series Parallel = Best: • Dickson ~ Better: use of • FCML starts to win (all same
no penalty for HV switches switches more effective *low* voltage switches)
21
 Caveats to Analysis/Conclusions Rentmeister:
ReSC w/ ZVS APEC ‘19
• Assumes Passive Size is dominant!
(if ‘switch sizes’ are dominant à Dickson-based!)

• Bottom plate (CV2, Coss) losses à important factor!

• ZVS in hybrid topologies:
[Blackwell et al., COMPEL ’18]
[Rentmeister et al., APEC ’19]
RESR F(Frequency, VDC)
• Resistive losses in capacitors à non-negligible!
[Coday et al., COMPEL ’18; APEC ’20] CX F(VDC)

• Variety of other challenges limit implementation(s) Balancing & Startup = Critical

• Gate driving complexity [Wicht, Pilawa, Stauth, others] VOUT ¼ VIN
• Flying capacitor voltage balance [Meynard, Prodic, Corradini, Vx
Ruderman, Reusch, Stillwell, Pilawa, others]
Iout
• Startup/precharge [Prodic, Stauth, Schaef, Pilawa]
iL
• Assembly: complexity and interconnect losses
22
 Example Topologies, Integrated
Automotive-Grade 48V Dickson
[Asherloo et al., & Trescases ISS/JSSC ’21]
• 48V:~3.3V step down
@ 91.4% efficiency
• Startup pre-charge, fault det.
• Valley current balancing
• Masterless multiphase
HV Self-Timed Resonant DC-DC
[Rindfleisch &
Wicht ISSCC ’20]
• High Voltage! 325V:~3.3V step down
@ 50-60% efficiency!
• On-chip HV resonant capacitor
• Self-timed ZVS/ZCS!

Cascaded Step Down Converter Quasi-resonant Series Parallel

[Xia et al., ISSCC ’21] [Schaef & Stauth JESTPE ’17]
• High VCR à 5V:0.4-1V • Early demonstration of startup pre-
@ 96.9% efficiency charge circuit, ZVS method
• Startup in <10μs • 33nH inductor
• Nonlinear control: Fast load • 330nF flying cap
transient & flying capacitor • 12V:3.7V, 4.6W at 87% efficiency
balancing 23
 Example Topologies, Discrete
48V:2V FCML w/
Current-Limit Control
[Rentmeister & Stauth APEC ’17]
• Early example/analysis of valley-
current control/ cap balancing
[First creditàReusch ECCE ’09]
• Multimode operation
• Moderate efficiency & density
FCML Inverter (LittleBox)
‘indirect’ resonant
‘Switched Tank’ Dickson topology [Lei et al. & Pilawa, TPEL ’17]
[Jiang et al., TPEL ’19]
• 2kW Multilevel inverter
• 48:12V step down
• Over 98% peak eff. • 97.6% eff @ >200W/in3
• Over 500W/in2 • Active energy buffer

Cascaded Resonant Converter Lego-PoL: high VCR Dual-Inductor Hybrid DSD/Series Cap Buck
[Ye & Pilawa, TPEL ’20] [Baek & Chen ’19-’21] [Seo/Das & HP. Le ’19-’21] [Nishijima ’05; Shenoy ‘15]
CF La

VIN VOUT

Lb

i.e. ‘sigma’ converter? 24

 Extended DSD Topology ßDickson-based with modifications

Multi Phase DSD Buck [Das et al., “Dual Inductor

TI: [Nishijima et al., Intelec ‘05] Hybrid..” JESTPE ’21] [Yang et al., ISSCC ‘21]

Ca La

Cb Lb

Cc Lc

Ln

• Dickson based but ~swap a switch for an inductor àbetter sum(VA)

• Interleaving quite attractive for high current PoL!
• Limited conversion ratio range & some restrictions on phase interleaving 25
 Challenges and Future Exploration
• Complicated circuits and switching networks
• Better gate-drive, level shift, timing and control
• Considerations of parasitics, layout, passive
component integration (flying and bypass caps)
• Flying capacitor voltage balance
• Huge challenges in normal operation
• Worst in transient conditions: line, load
• How to startup without overstressing
switches/passives
Example: [Xia et al., ISSCC ’21]
• Fast line/load transient response
• 5V:<1V cascaded hybrid
• Nonlinear control • Startup in <10μs
• Voltage balance feedback • Fast load transient & cap
• Real-time balancing balancing
 Thanks!
Students who contributed to this work:
Prescott McLaughlin (current), Ziyu Xia (current), Jan Rentmeister (Google),
Hassan Kiani (Apple), Sarah Pasternak (ADI), Kapil Kesarwani (Eta Wireless),
Chris Schaef (Intel),

27
 Some References
J. T. Stauth, “Pathways to mm-scale DC-DC converters: Trends, opportunities, and limitations,” in 2018 IEEE Custom Integrated Circuits
Conference (CICC), 2018, pp. 1–8.
S. R. Pasternak, M. H. Kiani, J. S. Rentmeister, and J. T. Stauth, “Modeling and Performance Limits of Switched-Capacitor DC–DC Converters
Capable of Resonant Operation With a Single Inductor,” IEEE J. Emerg. Sel. Top. Power Electron., vol. 5, no. 4, pp. 1746–1760, Dec. 2017.
P. H. McLaughlin, J. S. Rentmeister, M. H. Kiani, and J. T. Stauth, “Analysis and Comparison of Hybrid-Resonant Switched-Capacitor DC–
DC Converters With Passive Component Size Constraints,” IEEE Trans. Power Electron., vol. 36, no. 3, pp. 3111–3125, Mar. 2021.
Z. Xia and J. Stauth, “17.1 A Two-Stage Cascaded Hybrid Switched-Capacitor DC-DC Converter with 96.9% Peak Efficiency Tolerating
0.6V/μs Input Slew Rate During Startup,” in 2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, pp. 256–258.
C. Schaef, J. Rentmeister, and J. T. Stauth, “Multimode Operation of Resonant and Hybrid Switched-Capacitor Topologies,” IEEE Trans.
Power Electron., vol. 33, no. 12, pp. 10512–10523, Dec. 2018.
M. H. Kiani and J. T. Stauth, “Passive Component Modeling and Optimal Size Allocation for Hybrid-Resonant Switched Capacitor DC-DC
Converters,” in 2018 IEEE 19th Workshop on Control and Modeling for Power Electronics (COMPEL), 2018, pp. 1–8.
M. H. Kiani and J. T. Stauth, “Optimization and comparison of hybrid-resonant switched capacitor DC-DC converter topologies,” in 2017 IEEE
18th Workshop on Control and Modeling for Power Electronics (COMPEL), 2017, pp. 1–8.
J. S. Rentmeister and J. T. Stauth, “Bypass capacitance and voltage ripple considerations for resonant switched capacitor converters,” in 2017
IEEE 18th Workshop on Control and Modeling for Power Electronics (COMPEL), 2017, pp. 1–8.
K. Kesarwani, R. Sangwan, and J. T. Stauth, “Resonant-Switched Capacitor Converters for Chip-Scale Power Delivery: Design and
Implementation,” IEEE Trans. Power Electron., vol. 30, no. 12, pp. 6966–6977, Dec. 2015.

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