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Analog to Digital Converters
Microcontroller Applications
Analog to Digital
Converters
Analog to Digital Converters
 We have two methods in which can be used
for A/D Conversion.
1. Using an external A/D Converter. Interface the
input signal into this device. Connect the
converter binary output to the input of a
microcontroller.
2. Use the on board A/D Converter. (The
ATMega2560 already consists of a A/D
Converter).
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 An Analog to Digital Converter simply
converts an analog signal into digital format.
Essentially, converting a waveform into a
series of binary numbers.
 Microcontrollers handle data in Binary
format, hence we need to convert analog
signals.
A/D Converter Generic Concept
 An A/D Converter converts a voltage linearly
between VREFLO and a VREFHI voltage in 2n
steps.
 For example, a 3 bit converter will convert a
voltage between VREFLO = 0V and VREFHI =
1V.
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Counter Based ADC

 Counter Based A/D Converter

M = 3 (Resolution in Bits
N = 8 (Number of voltage intervals)
EFSR = VREFHI – VREFLO = 0 – 1 = 1V (Full scale voltage range)
Q=EFSR / N = 1/8 = 0.125V
Therefore, each bit is a resolution of 0.125V
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Counter Based ADC Integrating Converter

 This type uses a D/A converter as part of its feedback loop. It’s  Integrating A/D Converter
design is simple and is easily constructed.
 The start command causes the counter to be reset, which in
turn causes the D/A output to fall to zero. The clock is gated
into the counter which counts up towards full scale. The D/A -
output rises with each clock pulse until it is equal to or greater +
than the analog input. It is then that the comparator output
switches and stops the counter. The digital number in the
counter is the digital value of the input voltage.
 This type of system is inherently slow in operation, as it must
increment the D/A output from zero up to the unknown level.

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Integrating Converter Integrating Converter: Example

 The Control Logic counts a predefined period of clock pulses:  Vref = 1V

Eg 10000 pulses.  R = 220k
 During this period, the input signal ‘-Vin’ is sampled through an  C = 0.1uF
integrator circuit. Fclk = 100kHz

 The integrator will charge until the Control Logic reaches 10000  Tclk = 10us
pulses. The Control then switches from ‘Vin’ to ‘Vref’.
 T = 1000 x Tclk = 100ms
 The integrator will now discharge at a constant rate, until it
reaches 0V.
At 0V, the Comparator will switch the Control Logic off.  Find

– Slope of the First Stage Integration
 The remaining count at the Counter Digital Output is your digital – Vout of First Stage
conversion. – Slope of the Second Stage Integration
– t1
9 10 – The Digital Value (Number of Pulses)

Successive Approximation Successive Approximation

This is the typed used on the ATMega32.

 Successive Approximation A/D Converter 
 ADC works by using a digital to analog converter (DAC) and a
comparator to perform a binary search to find the input voltage.
 A sample and hold circuit is used to sample the analog input voltages
and hold the sampled value whilst the binary search is performed.
 The sample and hold circuit samples the analog input on a rising edge
of the signal. The comparator output is a logic 1 if the sampled analog
voltage is greater than the output of the DAC (VDAout), otherwise it is
0.
 If the comparator output is a logic 0 (i.e. the analog input is lower than
the output of the D-A converter) the bit is cleared and the next bit set.
This process continues until each bit has been checked. The state of
the bits at the end on the sequence is directly related to the input
signal voltage.
11 12  It is the one of the fastest converters available.

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Successive Approx: Example Parallel ADC

 Show the internal workings of the Successive Approximation  Parallel A/D Converter
Register by going through each step from 128 up and indicating
the value of the comparator and digital output.
 Vin = 2.8V
 A/D = 8 Bit Converter
 Span = 10V

Consider That:
If Vin > VDAoutput then Comp Out = 1
If Vin < VDAoutput then Comp Out = 0

If Comp Out = 1 then Bit = 1

If Comp Out = 0 then Bit = 0
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Parallel ADC ATMega2560 A/D Converter

Sometimes called a flash converter.  10-bit Resolution (2^10 = 1024)


 This converter compares all analog code levels to the input. It is
the fastest of all of the A/D Types. It’s speed is limited only by
the propagation delay in the comparator and the decoding logic.
 The resistive divider chain biases as the input of each of the
comparators to different code level appropriate to the resolution
in use.
 The circuit requires at least 2^n comparators for an ‘n’ bit
comparison.
 It becomes very complex in terms of hardware for resolutions
beyond 5 to 6 bits.
 The output of the comparators is not in binary form and so
15 further decoding is required. 16
 1 LSB Integral Non-linearity
 +-2 LSB Absolute Accuracy
 13-260us Conversion Time
 Up to 15kSPS at Maximum Resolution
 16 Multiplexed Single Ended Input Channels
 14 Differential Input Channels
 4 Differential Input Channels with Optional Gain of 10x and 200x
 Optional Left Adjustment for ADC Result Readout
 0-Vcc ADC Input Voltage Range
 Selectable 2.56V or 1.1V ADC Reference Voltage
 Free Running of Single Conversion Mode
 Interrupt on ADC Conversion Complete
 Sleep Mode Noise Canceler

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ATMega2560 A/D Converter Design Considerations

 The ATmega2560 features a 10-bit  Resolution

Successive Approximation ADC.
 The ADC is connected to an 16-Channel
Analog Multiplexer which allows 8 single-
ended voltage inputs constructed from the
pins of PORTF and PORTK.
 The single-ended voltage input refer to 0V
(GND).
– Resolution is the number of binary bits outputted
by the converter.
– An ADC with a 10bit output can represent up to
1024 (2^10) unique conditions of signal
measurement.
– Over the range of measurement from 0% to
100%, there will be exactly 1024 unique binary
numbers outputted by the converter.

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Design Considerations Design Considerations

 Conversion Rate  Conversion Rate

– Sample frequency. This is the speed at which the – Using the same sampling frequency, here is the
converter reads the inputted analog signal. affect on a slow-changing signal.

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Design Considerations Design Considerations

 Conversion Rate  Conversion Rate

– It’s important that an ADC’s sample time is fast enough to – If an ADC is subjected to an analog input signal
capture essential changes in the analog waveform.
whose frequency exceeds the Nyquist Frequency,
– The highest frequency waveform that an ADC can capture
is called the Nyquist Frequency. the converter will output a false digitised signal.
– Nyquist Frequency is equal to one half of the ADC’s sample – This phenomenon is know as Aliasing.
frequency.
– If an ADC circuit has a sample frequency of 5000Hz, the
highest-frequency waveform it can successfully resolve will
be the Nyquist Frequency of 2500Hz.

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Design Considerations Using the ATMega2560 ADC

 Conversion Rate  10 bit ADC, successive approximation

 Range between GND and VREF (can be the voltage
on the AREF or AVCC pin, or internal 2.56V / 1.1V).
 16 lines which can be used as single ended voltage
inputs or as an 16-channel multiplexer
 16/32 differential voltage input combinations, 4 of
them are also equipped with a programmable gain
stage (amplification steps of 0 dB (1x), 20 dB (10x),
or 46 dB (200x) on the differential input voltage
before the A/D conversion).

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Steps in Using the Converter Steps in Using the Converter

 Consider conversion rate.

 ATMega2560 ADC consists of it’s own
internal clock frequency which can range
between 50 to 200kHz. This value can be
changed by adjusting a Pre-Scaler value.
(Like a Timer).
 Select the channel (see MUX5:0 in ADMUX
and ADCSRB) – see complete table in
datasheet.
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Steps in Using the Converter Steps in Using the Converter

 Select your channel

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Steps in Using the Converter Steps in Using the Converter

 When the conversion is complete (ADIF in ADCSRA

is high), the conversion result is placed in the
registers ADCL and ADCH. Note: read ADCL first
and then ADCH.
 The result is returned as a 10 bit result in ADCL and
ADCH – it can be right-justified if ADLAR = 0 or left-
justified if ADLAR = 1
 Note: as the binary value of the converted analog
voltage is a 10-bit value, it will need to be stored into
an unsigned int type variable. The two values stored
in ADCL and ADCH will need to be combined.

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C code example for for a right-justified result (ADLAR = 0)

…
unsigned int digitalVoltage = 0;
unsigned char lowADC = 0, highADC = 0;
Implementation Notes
ADMUX = 0b01000000; //AVCC, ADLAR=0, channel 0
ADCSRA = 0b11000111; //enable, start conv, prescaler 128
for(i=0;i<2;i++) // do the ADC conversion at least twice  Configure Port pin as input. The pull up resistors are not to be
{ activated.
ADCSRA = ADCSRA | 0x40; //start conversion  Use the AVCC reference.
while(ADCSRA & 0x10 == 0); //wait for conversion to be done  For better accuracy, you may want to average the values
lowADC = ADCL; read.
highADC = ADCH;  The (unsigned int) cast is needed to ensure proper type
digitalVoltage = ((unsigned int) highADC) << 8 ; upgrade from unsigned char to unsigned int.
digitalVoltage = digitalVoltage | (unsigned int) lowADC;  If you haven’t used this before, note the ability of writing data
ADCSRA = ADCSRA | 0x10; //re-arm the flag in binary in your code, by using 0b followed by the binary
} value
 while(ADCSRA & 0x10 == 0);
This is polling the ADIF (AD Interrupt Flag), as when this
becomes 1, the conversion is done.

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