COMP2304 Computer Architecture and Organization

Addressing Modes and Instruction Format of the INTEL Core I7-4790K

Processor and the AMD Vishera FX-9590 Processor

By:

Dwi Putri Wahyuningsih

2019390004

Submission Date: April 8, 2020

Faculty of Engineering & Technology

Sampoerna University
 I. Intel Core I7 4790K
1. Addressing Modes

Supported modes include direct, direct, register, indirect register, indexed, and special
modes for handling array elements. The problem is that not all modes apply to all instructions and
not all registers can be used in all modes. This makes the work of compiler writers much more
difficult and leads to worse code.

MODE bytes control the addressing mode. One of the operands is determined by a
combination of the MOD and R / M fields. The other always register and is given by the REG field
value. If both fields are zero, for example, the operands are read from the memory address
contained in the EAX register.

Columns 01 and 10 involve a mode in which registers are added to the 8- or 32-bit offsets
that follow the instructions. If an 8-bit offset is selected, it's first-sign extended to 32 bits before
being added. For example, the ADD instruction with R / M = 011, MOD = 01, and offset 6 counts
the amount of EBX and 6 and reads the memory word at that address for one of the operands. EBX
is not modified.

MOD = 11 column gives the choice of two registers. For word instructions, the first choice
is used; for byte instructions, the second choice. Note that tables are not fully organized. For
example, there is no way to indirectly go through EBP and there is no way to offset from ESP.
 In some modes, additional bytes, called SIB (Scale, Index, Base), follow the MODE bytes.
SIB bytes determine the scale factor as well as two registers. When a SIB byte is present, the
operand address is calculated by multiplying the index register by 1, 2, 4, or 8 (depending on
SCALE), adding it to the base register, and finally maybe adding 8- or 32-bit displacement,
depending on the MOD. Almost all registers can be used as indexes or bases.

SIB mode is useful for accessing array elements. For example, consider the Java statement

for (i = 0; i <n; i ++) a [i] = 0;

where a is an array of 4-byte integers local to the current procedure. Typically, EBP is used to
point to the base of the stack frame that contains local variables and arrays. The compiler might
save me on EAX. To access [i], it will use SIB mode whose operand address is the number 4 ×
EAX, EBP, and 8. These instructions can be stored in [i] in one instruction.

2. Instruction Format

The Core i7 4790k instruction format is very complex and irregular, having up to six
variable length fields, of which five are optional. This situation occurs because architecture
evolved over several generations and included several bad choices early on. On behalf of backward
compatibility, this initial decision cannot be canceled later. In general, for two-operand
instructions, if one operand is in memory, the other may not be in memory. So, there are
instructions for adding two registers, adding registers to memory, and adding memory to registers,
but not adding memory words to other memory words.

In previous Intel architectures, all opcodes were 1 byte, although the prefix byte concept
was widely used to modify some instructions. The prefix bytes are additional opcodes attached to
the front of the instructions to change the action. WIDE instructions in IJVM are examples of
prefix bytes. Unfortunately, at some point during evolution, Intel ran out of opcodes, so one
opcode, 0xFF, was specified as an escape code to allow the second instruction byte.
 The individual bits in the Core i7 4790k opcode do not provide much information about
the instructions. The only structure in the opcode field is the use of low-order bits in some
instructions to indicate bytes/words, and the use of contiguous bits to indicate whether a memory
address (if any) is the source or destination. So, in general, opcodes must be fully translated to
determine what class of operation to perform - and thus how long the instruction will take. This
makes high-performance implementation difficult because extensive decoding is needed before it
can even be determined where further instructions begin.

Following the opcode byte in most of the instructions that reference the operand in memory
is the second byte that tells everything about the operand. These 8 bits are divided into 2-bit MOD
fields and two 3-bit register fields, REG and R / M. Sometimes the first 3 bits of this byte are used
as extensions for opcodes, giving a total of 11 bits for opcodes. However, the 2-bit mode field
means that there are only four ways to handle operands and one operand must always be a register.
Logically, every EAX, EBX, ECX, EDX, ESI, EDI, EBP, ESP must be specified as registers, but
encoding rules forbid certain combinations and use them for special cases. Some modes require
additional bytes, called SIB (Scale, Index, Base), giving further specifications. This scheme is not
ideal, but a compromise gave the competing demands of backward compatibility and the desire to
add new features that were not initially imagined.

Besides all this, some instructions have 1, 2, or 4 more bytes that specify the memory
address (displacement) and maybe 1, 2, or 4 other bytes contain constants (direct operand).
II. AMD VISHERA FX-9590
1. Addressing Modes
AMD Vishera FX 9590 architecture doubles the number of GPRs and increases its
width to 64-bits. It also doubles the number of YMM/XMM registers. To support the
specification of register operands contained in the eight additional GPRs or
YMM/XMM registers and to make the additional GPRs available to hold addresses to
be used in the addressing modes, the REX prefix provides the R, X, and B bit fields to
extend the reg, r/m, index, and base fields of the ModRM and SIB bytes in the various
operand addressing modes to four bits. A fourth REX bit field (W) allows instruction
encodings to specify a 64-bit operand size.

REX.W: Operand Width (Bit 3). Setting the REX.W bit to 1 determines the 64-bit
operand size. Like the prefix override of the existing 66j operand size, overriding the
64-bit REX operand size does not affect the byte operation. For non-byte operations,
overriding the REX operand size takes precedence over the 66j prefix. If the 66-hour
prefix is used in conjunction with the REX prefix that has the W bit set to 1, the 66-
hour prefix is ignored. However, if the 66-hour prefix is used together with the REX
prefix that has the W bit removed to 0, the 66-hour prefix is not ignored, and the size
of the operand becomes 16 bits.
REX.R: Register field extension (Bit 2). The REX.R bit adds a 1-bit extension (in
the position of the most significant bits) to the ModRM.reg field when it encodes GPR,
YMM / XMM, control, or debug registers. REX.R does not change ModRM.reg when
 the field specifies another register or is used to extend the opcode. REX.R is ignored in
such cases.
REX.X: Index field extension (Bit 1). The REX.X bit adds a 1-bit (msb) extension
to the SIB.index field.
REX.B: Base field extension (Bit 0). The REX.B bit adds a 1-bit (msb) extension
to the ModRM.r / m field to specify the GPR or XMM register, or to the SIB.base field
to determine the GPR

2. Instruction Format