Professional Documents
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University of Waterloo
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
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ENTITY entity_name IS
GENERIC(
generic_1_name : generic_1_type;
generic_2_name : generic_2_type;
generic_n_name : generic_n_type
);
PORT(
port_1_name : port_1_dir port_1_type;
port_2_name : port_2_dir port_2_type;
port_n_name : port_n_dir port_n_type
);
END entity_name;
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ENTITY andgate IS
PORT ( a : IN std_logic;
b : IN std_logic;
c : OUT std_logic );
END andgate;
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std_ulogic
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std_logic_vector( <max> DOWNTO <min> )
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY simple_buffer IS
PORT ( din : IN std_logic;
dout : OUT std_logic );
END simple_buffer;
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PROCESS (a, b, d)
-- a, b, and d are in the sensitivity list to indicate that
-- the outputs of the process are sensitive to changes in them
BEGIN
-- CASE keyword is only valid in a process
CASE d IS
WHEN ‘0’ =>
c <= a AND b;
WHEN OTHERS =>
c <= ‘1’;
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END CASE;
END PROCESS;
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY dffe IS
PORT( rst, clk, ena, d : IN std_logic;
q : OUT std_logic );
END dffe;
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY vending IS
PORT(
reset : IN std_logic;
clock : IN std_logic;
buttons : IN std_logic_vector(1 DOWNTO 0);
lights : OUT std_logic_vector(1 DOWNTO 0)
);
END vending;
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ENTITY andnand IS
PORT ( a : IN std_logic;
b : IN std_logic;
q : OUT std_logic;
qbar : OUT std_logic );
END andnand;
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std_logic_vector C <
std_logic_vector C <
std_logic 3 <
std_logic_vector C
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ENTITY quadmux IS
PORT ( a : IN std_logic_vector(3 DOWNTO 0);
b : IN std_logic_vector(3 DOWNTO 0);
sel : IN std_logic;
c : OUT std_logic_vector(3 DOWNTO 0) );
END quadmux;
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sel c[3..0]
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ENTITY seven_seg IS
PORT( dataIn : IN std_logic_vector(3 DOWNTO 0);
segments : OUT std_logic_vector(7 DOWNTO 0) );
END seven_seg;
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ENTITY dregister IS
PORT( rst, clk, ena : IN std_logic;
d : IN std_logic_vector(7 DOWNTO 0);
q : OUT std_logic_vector(7 DOWNTO 0) );
END dregister;
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clock
enable
reset value[31..0]
ENTITY counter IS
PORT(
reset : IN std_logic;
clock : IN std_logic;
enable : IN std_logic;
value : OUT std_logic_vector(31 DOWNTO 0)
);
END counter;
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BEGIN
PROCESS (reset, clock)
BEGIN
IF (reset = ‘1’) THEN
count <= X”00000000”;
ELSIF (clock’EVENT) AND (clock = ‘1’) THEN
IF (enable = ‘1’) THEN
count <= count + 1;
END IF;
END IF;
END PROCESS;
-- Here, the count value is
value <= std_logic_vector(count); -- converted to std_logic_vector
-- using a conversion function
END synthesis1;
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