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MITSUBISHI
SEMICONDUCTOR
SEMICONDUCTOR
<Intelligent
<Intelligent
Power
Power
Module>
Module>
PS21353-N
PS21353-N
TRANSFER-MOLD
TRANSFER-MOLD
TYPE
TYPE
INSULATED
INSULATED
TYPE
TYPE
PS21353-N
INTEGRATED POWER FUNCTIONS
600V/10A low-loss 4th generation (planar) IGBT inverter
bridge for 3 phase DC-to-AC power conversion.
APPLICATION
AC100V~200V inverter drive for motor control.
(1.5)
(10.5)
5 (COM)
PCB 6 UP
(1) PATTERN 7 VVFS
(1) (0.5) (1.9) SLIT 8 (VPG)
(1.8MIN) 9 VVFB
(PCB LAYOUT) 10 VP1
DUMMY PIN Detail A 11 (COM)
(1.778 × 26) *Note2 12 VP
(1.778) 13 VWFS
(5) 14 (WPG)
(6.25) (6.25) (6.25) (8) (8) A 15 VWFB
16 VP1
2)
(0.5)
TH 17 (COM)
28 27 26 25 24 23 22 21 20 19 18 16
17
15 13
14
12 10
11
987 654 321
D EP 18 WP
(17.4)
(φ2 19 (UNG)
29
Type name , Lot No. .3) 20 VNO(NC)
(φ3
(0.75)
30
21 UN
22 VN
(30.5)
26 CIN
27 VNC
(1.2)
28 VN1
35 34 33 32 31
29 (WNG)
30 (VNG)
31 P
(7.62) (4MIN)
(0.5)
32 U
(7.62 × 4) (1.25) 33 V
(2.5) 34 W
(41)
35 N
(42)
(49) *Note1:(***) = Dummy Pin.
*Note 2: In order to increase the surface distance between terminals, cut a slit, etc. on the PCB surface
when mounting a module.
Sep. 2001
MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>
PS21353-N
TRANSFER-MOLD TYPE
INSULATED TYPE
CBW+
CBW–
CBV+
CBU–
CBV–
CBU+
High-side input (PWM)
C3 : Tight tolerance, temp-compensated electrolytic type (5V line) (Note 1,2)
(Note : The capacitance value depends on the PWM control C4
scheme used in the applied system). C3
Input signal Input signal Input signal
C4 : 0.22~2µF R-category ceramic capacitor for noise filtering. coditioning coditioning coditioning
DIP-IPM
Drive circuit Drive circuit Drive circuit
Inrush current
limiter circuit
P
H-side IGBTS
AC input
U
V
(Note 4)
W
M
C Fig. 3 AC line output
Z
N1 N
VNC
CIN L-side IGBTS
DIP-IPM
Short Circuit Protective Function (SC) :
SC protection is achieved by sensing the L-side DC-Bus current (through the external
Drive circuit
P shunt resistor) after allowing a suitable filtering time (defined by the RC circuit).
When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned
OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is
recommended to stop the system when the Fo signal is received and check the fault.
IC (A)
SC Protection
H-side IGBTS Trip Level
U
V
W
L-side IGBTS
External protection circuit
N1 Shunt Resistor A N
(Note 1)
VNC
C R Drive circuit
CIN
B Collector current
Protection circuit waveform
C
(Note 2) 0
Note1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0µs. 2 tw (µs)
2: To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible.
Sep. 2001
MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>
PS21353-N
TRANSFER-MOLD TYPE
INSULATED TYPE
TOTAL SYSTEM
Symbol Parameter Condition Ratings Unit
VCC(PROT) Self protection supply voltage limit VD = VDB = 13.5~16.5V, Inverter part
Tj = 125°C, non-repetitive, less than 2 µs 400 V
(short-circuit protection capability)
Tf Heat-fin operation temperature (Note 2) –20~+100 °C
Tstg Storage temperature –40~+125 °C
60Hz, Sinusoidal, 1 minute, connection
Viso Isolation voltage 1500 Vrms
pins to heat-sink plate
Al Board Specifications:
Dimensions 100 × 100 × 10mm, finishing: 12s, warp: –50~100µm
Control Terminals
Groove
IGBT Chip
Temp. measurement point
Temp. measurement (inside the Al board)
N W V U P
point
(inside the Al board)
Power Terminals
Sep. 2001
MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>
PS21353-N
TRANSFER-MOLD TYPE
INSULATED TYPE
THERMAL RESISTANCE
Limits
Symbol Parameter Condition Unit
Min. Typ. Max.
Rth(j-f)Q Junction-to-heat sink thermal Inverter IGBT part (per 1/6 module) (Note 3) — — 5.0 °C/W
Rth(j-f)F resistance Inverter FWD part (per 1/6 module) (Note 3) — — 6.5 °C/W
Note 3 : Grease with good thermal conductivity should be applied evenly about +100µm~+200µm on the contact surface of a DIP-IPM and a
heat sink.
Sep. 2001
MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>
PS21353-N
TRANSFER-MOLD TYPE
INSULATED TYPE
DIP-IPM
+–
Measurement Range 3mm
Heat-sink
–
+
Heat-sink
Sep. 2001
MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>
PS21353-N
TRANSFER-MOLD TYPE
INSULATED TYPE
VUFB DIP-IPM
VUFS P
HVIC 1
VP1 VCC VB IGBT1 Di1
UP IN HO
COM VS U
VVFB
VVFS
HVIC 2
VP1 VCC VB IGBT2 Di2
VP IN HO
COM VS V
VWFB
VWFS
HVIC 3
VP1 VCC VB IGBT3 Di3
VP IN HO
COM VS W
LVIC IGBT4
Di4
UOUT
VN1 VCC
IGBT5
Di5
VOUT
UN UN IGBT6
Di6
VN VN WOUT
WN WN
VNO
Fo Fo
CIN
VNO(NC)
VNC GND N
CFO
CFO CIN
Note: The IGBTs gates and the HVICs COM terminals are connected to the dummy pins.
Sep. 2001
MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>
PS21353-N
TRANSFER-MOLD TYPE
INSULATED TYPE
SC a4
a1
Output current Ic a8
SC reference voltage
Sense voltage of the
shunt resistor
Fault output Fo a5
Control input
UVDr
Control supply voltage VD b5
UVDt
b2
b1 b3 b6
Output current Ic
Fault output Fo b4
Sep. 2001
MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>
PS21353-N
TRANSFER-MOLD TYPE
INSULATED TYPE
Control input
UVDBr
Control supply voltage VDB c1 c5
UVDBt
c3
c2 c4 c6
Output current Ic
5V line
DIP-IPM
5.1kΩ 4.7kΩ
UP,VP,WP,UN,VN,WN
Fo
CPU
1nF 1nF
VNC(GND)
Note : RC coupling at each input (parts shown dotted) may change depending on the
PWM control scheme used in the application and on the wiring impedance of
the application’s printed circuit board.
Sep. 2001
MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>
PS21353-N
TRANSFER-MOLD TYPE
INSULATED TYPE
C1: Tight tolerance temp - compensated electrolytic type; C2,C3: 0.22~2 µ F R-category ceramic capacitor for noise filtering
5V line C2 VUFB
DIP-IPM
C1 VUFS P
HVIC1
VP1
VCC VB
C3
UP
IN HO
COM VS U
C2 VVFB
C1 VVFS
HVIC2
VP1
VCC VB
C3
VP
IN HO
V
C2
COM VS M
VWFB
C1 VWFS
C HVIC3
P VP1
VCC VB
U C3
WP
IN HO
U COM VS W
N
I LVIC
T UOUT
C3 VN1
VCC
5V line
VOUT
UN
UN
VN VN WOUT
WN If this wiring is too long,
WN short circuit might
Fo VNO be caused.
Fo
CIN
VNC N
GND CFO
C
CFO CIN
Note 1 : To prevent the input signals oscillation, an RC coupling at each input is recommended, and the wiring of each input should be as short
as possible (less than 2cm).
2 : By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler
or transformer isolation is possible.
3 : FO output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply with approximately
5.1kΩ resistance.
4 : FO output pulse width should be decided by connecting an external capacitor between CFO and VNC terminals (CFO). (Example : CFO
= 22 nF → tFO = 1.8 ms (typ.))
5 : Each input signal line should be pulled up to the positive side of the 5V power supply with approximately 4.7kΩ resistance (other RC
coupling circuits at each input may be needed depending on the PWM control scheme used and on the wiring impedances of the
system’s printed circuit board). Approximately a 0.22~2µF by-pass capacitor should be used across each power supply connection
terminals.
6 : To prevent errors of the protection function, the wiring of A, B, C should be as short as possible.
7 : In the recommended protection circuit, please select the R1C5 time constant in the range of 1.5~2µs.
8 : Each capacitor should be put as nearby the terminals of the DIP-IPM as possible.
9 : To prevent surge destruction, the wiring between the smoothing capacitor and the P&N1 terminals should be as short as possible. Ap-
proximately a 0.1~0.22µF snubber capacitor between the P&N1 terminals is recommended.
Sep. 2001
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