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Optoelectronic System

and Control Lab., ECE,


NCTU

Design of Analog CMOS


Integrated Circuits

Class 9 – Operation Amplifier

Paul C.–P. Chao


Dept. of Elec. and Contrl. Eng.
National Chiao Tung University

05/19/2019

2007/11/20
2019/05/19 PaulPaul
C.-P.C.-P.
Chao,Chao
P1
Optoelectronic System
and Control Lab., ECE,
NCTU

Scope
 An operation amplifier (op amp) means “high-gain
differential amplifier,” with Av from 10 to 105.
 Ops are an integral part of many analog and mixed-
signal systems
 For dc bias generation, waveform generation, high-speed
amplification or filtering
 Performance parameters.
 Simple op amps such as telescopic and folded cascode
topologies
 Two-stage and gain-boosting configurations - the
problem of common-mode feedback
 Slew rate, power supply rejection and noise.

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Optoelectronic System
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NCTU

Performance Indices

 Gain
 Bandwidth
 Slew Rate
 Output Swing
 Linearity
 Noise and Offset
 Power Supply Rejection Rate

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Optoelectronic System
and Control Lab., ECE,
NCTU
Gain
 Example: the circuit is designed for a nominal of 10, i.e.,
 1 + R1/R2 =10
V A1 R  R2 A1
 The close-loop gain: out   1 
Vin 1  R2 R2 R1  R2
A1  A1
R1  R2 R2
R1  R2 V  R  R  R2 1 
If A1  , then out  1  1 1  1 
R2 Vin  R2  R2 A1 
 The term (R1 + R2)/(R2 A1) = (1 + R1/R2)/ A1 represents the relative erro
 To achieve a gain error less than 1%, we must have A1 > 1000.

 Simple CS stage – an open-loop implementation:


Vout
 g m RD  10
Vin

 It is difficult to guarantee an error less than 1%


 The variations in the mobility and gate oxide thickness of the
transistor and the value of the resistor typically yield an error
greater than 20%.

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P4
Optoelectronic System
and Control Lab., ECE,
NCTU BW and SR

 Bandwidth
 Defined at 3db drop.
 Ought to be increased for
faster response – a higher
slew rate. Bandwidth

 Slew Rate

Slew rate
Feedback
to
increase
SR

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P5
Optoelectronic System
and Control Lab., ECE,
NCTU

Others

 Output swing – A wide range of signal amplitudes


 Linearity – Minimizing nonlinearity
 For a cascode OP, the input pair M1 – M2 exhibits a
nonilinear relationship between its differential drain
current and input voltage
 Noise and offset – The input noise and offset of op
amps determine the minimum signal level that can be
processed with reasonable quality
 Supply rejection – In mixed-signal systems it is
connected to noise digital supply lines
 The performance of op amps in the presence of supply
A cascode OP noise, especially as the considered frequency increasing
(close to digital sampling frequency), is quite important.
For this reason, fully differential topologies are preferred

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P6
Optoelectronic System
and Control Lab., ECE,
NCTU
Single-Stage OP
 Single-ended output  Differential output
– Current mirror - Differential Amp

 Low frequency gain = gmN (roN || roP)


 The small-signal gain hardly exceeds 20 in submicron devices with typical
current levels
 The bandwidth is usually determined by the load capacitance, CL
 Noises are contributed from M1-M4

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Chao,Chao
P7
Optoelectronic System
and Control Lab., ECE,
NCTU Unit-Gain Buffer
 Input common-mode voltage range
Vin,min  VCS ,OD  VGS1  VCS ,OD  VOD1  VTH 1
Vin,max  VDD  ( VGS 3  VTH 3 )
VOD3  VDS 3
fdbk
 Suppose Vth= 0.7V and VOD = 0.3V, then Vin,min
Implemented
= 1.3V, and Vin,max = 2.7V. Thus, the input CM
by an ACM range equals 1.4V with a 3V supply.

 Output impedance

Rout ,open roP || roN 1


Rout   
1   Rout ,open 1  g mN (roP || roN ) g mN

 The closed-loop output impedance is relatively


fdbk
independent of the open-loop output impedance.
 Allowing us to design high-gain op amps by
increasing the open-loop output impedance (for
high gain) while still achieving a relatively low
closed-loop output impedance.
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P8
Optoelectronic System
and Control Lab., ECE,
NCTU
Telescope Cascode OP (TCO)
 Single-ended output  Differential output
– Current mirror - Differential Amp

 For a high gain, the differential cascode topologies with large Zout can be used.
 Low-frequency gain Av = gmN [(gmN roN2) || (gmP roP2)]
 Drawbacks: Two degenerated CS
Based on class 3, pg 38
 Smaller output swing.
 A mirror poles at X, decreasing stability (introducing a zero).
 Hard to implement a unit buffer.
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Chao,Chao
P9
Optoelectronic System
and Control Lab., ECE,
NCTU Output Swing
 Fully differential topology, the output swing is given by * Unit buffered TCO
 2[VDD − (VOD1 + VOD3 + VCSS + |VOD5| + |VOD7|)]
where VODj denotes the overdrive voltage of Mj
- The above output swing is relatively small.

 Another drawback is the difficulty in shortening their


inputs and outputs, e.g., to implement a unity-gain buffer.

 For a unit-bufferred TCO


 M2 and M4 in saturation: VX

M 2 : Vout  VX  VTH 2
  Vb  VTH 4  Vout  Vb  (VGS 4  VTH 2 )
 M4 : Vout  Vb  VTH 4

• The output swing Vout,max − Vout,min = VTH4 − (VGS4 − VTH2) =


VTH2 − (VGS4 − VTH4), which can be maximized by minimizing
VOD,M4, but always less than VTH2.
• The output swing is less than VTH, thus, a cascode op amp is not Allowable
suitable for implementing a unit-gain buffer, due to small Range
output swing.

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Chao,Chao
P10
Optoelectronic System
and Control Lab., ECE,
NCTU Design Example
For TCO

 Specifications:
 VDD=3V, differential output swing=3V
 Power dissipation=10mW, voltage gain=2000
 Assume μnCOX=60μA/V2, μpCOX=30μA/V2,
λn=0.1V-1, λp=0.2V-1 (for an effective channel
length of 0.5μm)
 Power budget:
 IM9=3mA, IMb1,IMb2=330μA
 Output swing:
 Node X(Y) swing=1.5V, M3-M6 in saturation
 Design for ODs:
 |VOD7|+|VOD5|+VOD3+VOD1+VOD9=1.5V
 VOD9~0.5V (M9 carrying largest current)
 |VOD5|=|VOD7|~0.3V (suffer from low mobility)
 VOD1=VOD3~0.2V
 W/L: (fixing L=0.5μm)
 By ID=(1/2)μCOX(W/L)(VGS-VTH)2
(W/L)1-4=1250, (W/L)5-8=1111, (W/L)9=400

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Chao,Chao
P11
Optoelectronic System
and Control Lab., ECE,
NCTU Design Example
For TCO (cont’d)
 Gain: Av  gm1 ( gm3ro3ro1 ) //( gm5 ro5ro7 )  1416
 In order to increase the gain,

2Cox (W / L) I D  1
g m ro   WL / I D    
ID  L
 Speed or noise requirements may dictate the bias
current – ID is not a good choice used to be tuned to
increase gain.
 The width of each transistor, W, must be at least
scaled with its length so as to maintain a constant
W/L, then overdrive voltages.
 Choose (W/L)5-8=1111μm/1μm, with WL to be increased
for a better design.
 Doubling W5-8, Av=4000
VTH+VOD1
VTH+VOD3
 CM level& bias:
 Min. allowable input CM level =VGS1+VOD9=1.4V
 Vb1,min=VGS3+VOD1+VOD9=1.6V
 Vb2,max=VDD-(|VGS5|+|VOD7|)=1.7V
VTH+VOD3

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P12
Optoelectronic System
and Control Lab., ECE,
NCTU Folded Cascode OPs

gm1Vin

 In order to alleviate the drawbacks


of TCO, the folded cascode is
gm1Vin
employed.

 The primary advantage of the


folded structure lies in the choice of
the voltage levels because it does
gm1Vin not stack the ODs by cascode
transistors on the top of the input
device.
gm1Vin

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Chao,Chao
P13
Optoelectronic System
and Control Lab., ECE,
NCTU
Differential Folded Cascode OPs

ISS/2
ID3 ID4

ISS/2

 Two important differences between the two circuits:


 Power consumption:
 In Fig.(a), one bias current, ISS, provides the drain current of both the input transistors
and the cascode devices
 In Fig.(b), the input pair requires an additional bias current, ISS1 = ISS/2 + ID3 (more
power consumption) V < V +V
in S3 TH1
 Input Common Mode Rejection: =Vb1 − VGS3 +VTH1
 In Fig.(a), the input CM level cannot exceed Vb1 − VGS3 +VTH1 (upper bound)
 In Fig.(b), it cannot be less than Vb1 − VGS3 + |VTHP| (lower bound)
 In Fig.(b), it is possible to tie the n-well of M1 and M2 to their common source point
Vin > VS3 +VTHP
=Vb1 − VGS3 +VTHP

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Chao,Chao
P14
Optoelectronic System
and Control Lab., ECE,
NCTU
Differential Folded TCOs

 Folded cascode op amp with cascode PMOS


loads
 Max. output voltage swing: with proper
choice of Vb1 and Vb2,
 Peak-peak swing = [VDD − (|VOD7| +
|VOD9|)] − (VOD3 + VOD5 ) for one side

 The swing is lesser by the overdrives of


the tail current source, M5 and M6, in
the telescopic cascode.

 Carrying large currents, M5 and M6 may


require a high overdrive voltage if their
capacitance contributions to nodes X
and Y are to be minimized 1 W
I D  nCox ( )(VGS  VTH )2
2 L
larger

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Chao,Chao
P15
Optoelectronic System
and Control Lab., ECE,
NCTU
Small-signal Gain for DFTCO

ID1 Iout

Equivalent circuit with


output shorted to ground Equivalent circuit with output open
Half circuit Since ( g m3  g mb 3 ) 1 || ro 3  ro1 || ro 5 ROP  ( g m 7  g mb 7 ) ro 7 ro9
| Av | Gm Rout I out  I D1  Gm  g m1 Rout  ROP || [( g m3  g mb3 )ro3 (ro1 || ro5 )]

 Thus, |Av| ≈ gm1{[(gm3+gmb3)ro3(ro1||ro5)] || [(gm7+ gmb7) ro7 ro9]}


 The gain is usually two or three times lower than that of a unfolded telescopic
cascode.

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C.-P. C.-P.
Chao,Chao
P16
Optoelectronic System
and Control Lab., ECE,
NCTU
Device Capacitances

 Effect of device capacitance on the dominant pole in telescopic and


folded cascode op amps

Ctot = CGS3 + CSB3 + CDB1 + CGD1 Ctot = CGS3 + CSB3 + CDB1 + CGD1 + CGD5 + CDB5

 The pole at the “folding point,” i.e., the sources of M3 and M4, is quite closer to the
origin than that associated with the source of cascode devices in a telescopic
topology, since the total capacitance becomes much larger.

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Chao,Chao
P17
Optoelectronic System
and Control Lab., ECE,
NCTU
A High-Gain DFTCO

 The circuit provides a higher gain because of the greater mobility of


NMOS devices (than PMOS)
 But at the cost of lowering the pole at the folding point
 ωp,X ≈ (gm3 + gmb3) / Ctot,X {=(RC)-1}
Low by PMOS

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Chao,Chao
P18
Optoelectronic System
and Control Lab., ECE,
NCTU
Comparison between TCO and FCO

 The voltage swing of a folded-cascode op amp (FCO) is only slightly higher than that of a
telescopic configuration (TCO)
 But with cost of higher power dissipation, lower voltage gain, lower pole frequencies, and
higher noise (two more current s ourses)
 FCOs are still used quite widely, even more than telescopic topologies,
 This is because the choice of the input common-mode level is easier (due to a larger swing)
 In a TCO, three voltages must be defined carefully:
 The input CM level and the gate bias voltages of the PMOS and NMOS cascode transistors in
CSes.
 In FCO, only the latter two are critical. The capability of handling input CM levels are close
to one of the supply rails

TCO FCO
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Chao,Chao
P19
Optoelectronic System
and Control Lab., ECE,
NCTU Design Example of a DFCO

 Specifications:
 VDD = 3V, differential output swing=3V, power dissipation=10mW, voltage
gain=2000
 Assume µ nCox=60 µA/V2, µ pCox=30 µA/V2, λn=0.1V−1, λp=0.2V−1 (for an effective
channel length of 0.5 µm), γ=0, VTHN = |VTHP| = 0.7V

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P20
Optoelectronic System
and Control Lab., ECE,
NCTU Design Example of a DFCO
Determining peripheral components

 Power budgeting:
 IM11 = 1.5mA, IM9 + IM10 = 1.5mA, IMb1 + IMb2 + IMb3 = 330µA
 Output swing:
 One side swing=1.5V, M3-M10 in saturation
 Choose |VOD5,6| ≈ 0.5V, |VOD3,4| ≈ 0.4V, VOD7,8 = VOD9,10 ≈ 0.3V
 W/L:
 Since ID = (1/2) µCox(W/L)(VGS − VTH )2,
we have (W/L)5,6 = 400, (W/L)3,4 = 313, (W/L)7−10 = 555
 Output CM level:
 CMmin = 0.6V, CMmax = 2.1V, thus CMavg, opt = 1.35V

VDD-VOD5

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Chao,Chao
P21
Optoelectronic System
and Control Lab., ECE,
NCTU Design Example of a DFCO
Determining M1,2

 Determine (W/L)1,2:
 min. input CM level = VGS1 + VOD11 (VOD11=0.4V <- Ball-Park Design)
 If input and output are shorted for unit buffer, then VGS1 + VOD11 is designed to be
CMavg, opt =1.35V. Thus VGS1=0.95V, VOD1,2 = 0.25V, (W/L)1,2=400
 The maximum dimensions of M1,2 are determined by the tolerable input
capacitance at nodes X and Y
 Gain: gm=2ID/(VGS − VTH), we have
 gm1,2 = 0.006 A/V, gm3,4 = 0.0038 A/V, gm7,8 = 0.05 A/V
 For L = 0.5µm, ro1,2=ro7-10=13.3kΩ, ro3,4=2ro5,6=6.67kΩ
 Note |Av| ≈ gm1{[(gm3 + gmb3)ro3(ro1 || ro5)] || [(gm7 + gmb7) ro7ro9]}=400

VGS2 + VOD11=1.35V

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Chao,Chao
P22
Optoelectronic System
and Control Lab., ECE,
NCTU
Single-Ended TCO
(with current mirrors)
Fig(a):
 Fig(a): VX = VDD − |VGS5| − |VGS7|, limiting the
maximum value of Vout to VDD − |VGS5| − |VGS7| +
|VTH6| and wasting one PMOS threshold voltage
in the swing
 Fig(b): To solve above issue, M7 and M8 are
biased at the edge of the triode region.

 Disadvantages of SETCO over differential TCO:


 It provides only half the output voltage swing Fig(b):
 It contains a mirror pole at node X, thus
limiting the speed of feedback systems
employing such an amplifier

 It is preferable to use the differential topology,


although it requires a feedback loop to define the
output CM level, as demonstrated in the previous
example.

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Chao,Chao
P23
Optoelectronic System
and Control Lab., ECE,
NCTU

Triple TCO

 The “triple cascode” topology


provides a gain on the order of
(gmro)3/2 but further limits the output
swings

 With six overdrive voltages


subtracted from VDD in this circuit, it
is difficult to operate the amplifier
from a supply voltage of 3V or lower
while obtaining reasonable output
swings

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Chao,Chao
P24
Optoelectronic System
and Control Lab., ECE,
NCTU

Two-Stage OPs
 The gain of one-stage topologies is limited to the input pair gm and Rout.
 Two-stage op amps consist of first stage providing a high gain and the
second providing large swing.
 The first stage incorporates various amplifier topologies
 But the second stage is typically configured as a simple common-source stage to
allow maximum output swings
 Can we cascade more than two stages to achieve a higher gain?
 Each gain stage introduces at least one pole in the open-loop transfer function,
making it difficult to guarantee stability in a feedback system using such an op
Amp
 For this reason, op amps having more than two stages are rarely used.

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Chao,Chao
P25
Optoelectronic System
and Control Lab., ECE,
NCTU Two-Stage OPs

 Simple two-stage op:


 Gain:
 Av,1st stage = gm1,2(ro1,2 || ro3,4)
 Av,2nd stage = gm5,6(ro5,6 || ro7,8)
 Overall gain Av = Av,1st stage × Av,2nd stage
 Output swing = VDD − |VOD5,6| − VOD7,8

 Two-stage op for a higher gain, with


a cascoded first-stage DP.
 The overall voltage gain is then
Av

 
 g m1,2  g m3,4  g mb3,4  ro3,4 ro1,2   g m5,6  g mb5,6  ro5,6 ro 7,8 

  g m9,10  ro 9,10 || ro11,12  

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P26
Optoelectronic System
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NCTU

Single-ended Two-Stage OP

Shorted for unit buffer

Single-ended

 If the gate of M2 is shorted to Vout to form a unity-gain buffer, then the


minimum allowable output level is equal to VGS2 + VISS, severely limiting
the output swing.

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Chao,Chao
P27
Optoelectronic System
and Control Lab., ECE,
NCTU Gain-Boosting
by Feedback

 Rout = gm2ro2ro1
 M1 operates as a degeneration resistor

Add a
 The voltage variations at the drain of M2 affect VX Fb-op
(drain of input device)to a lesser extent because
A1 regulates this voltage (VX= Vb at steady state)
 With smaller variations on VX and the current
through ro1 and hence the output current remains
more constant, yielding a higher output
impedance
 Rout ≈ A1gm2ro2ro1, Rout is boosted substantially
without stacking more cascode devices on top of *Current-Voltage Feedback
M2 – An alternative to cascoding and two-stage op. (Sensing drain of input
device – stabilize ΔI by input
signal)

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Chao,Chao
P28
Optoelectronic System
and Control Lab., ECE,
NCTU
Cascode Stage with Gain-boosting
(Regulated Cascode)

Implemented

 For small-signal operation, Vb is


assumed zero (grounded) for
analysis “Regulated Cascode”
-- regulating Vx
 Gain:
 |Av| ≈ gm1 (gm2 ro2 ro1) (gm3 ro3)

Rout1 A1
 Min. output swing:
 Since VX = VGS3, the min.value of Vout is VOD2 + VGS3
 The auxiliary amplifier limits the output swing Smaller

 Note: Min. output swing is VOD2+VOD1 in a simple cascode

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C.-P. C.-P.
Chao,Chao
P29
Optoelectronic System
and Control Lab., ECE,
NCTU Boosting a Differential TCO

VOD3 + VGS5 + VISS2


 The minimum level at the drain of M3
(output node) is equal to VOD3 + VX =
VOD3 +VGS5 + VISS2
 The voltage swing limitation results in
the fact that the gain-boosting amplifier
incorporates an NMOS differential pair –
Smaller ODs.

 Implemented by ->
OR

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Chao,Chao
P30
Optoelectronic System
and Control Lab., ECE,
NCTU Boosting by a Folded Cascodes
 (a) : The voltages at X and Y are instead sensed by a PMOS pair
 The minimum value of VX is not dictated by the gain-boosting amplifier, since the min.
CM level of a folded cascode using a PMOS can be small.
 The minimum allowable level of VX and VY is given by VOD1,2 + VISS1 .
 (b): Output impedance
 Since VP
 g m5 Rout1  A1
VX A1
 where Rout1 ≈ [gm7ro7(ro9||ro5)] || (gm11ro11ro13) -> Rout ≈ gm3ro3ro1gm5Rout1

Rout1

VP
Half circuit & CS
implementation
VX
(a) Aux. Amp. By
Folded Cascode

(b) Aux. Amp. By


TCO
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P31
Optoelectronic System
and Control Lab., ECE,
NCTU

Boosting at Loadings and Signals


to increase Gain by enlarging Rout

Regulating drain
of current
sources
-- Boosting Rout

Increase output
swing -> Folded

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Chao,Chao
P32
Optoelectronic System
and Control Lab., ECE,
NCTU

Concluding Gain-Boosting

 A good method of increasing without adding a


two-stage or more cascode devices.
 Still introducing poles by regulating cascodes.
 Only an small portion of signal flows
through the gain-boosting op, which
experiencing the “slowed down.”

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Chao,Chao
P33
Optoelectronic System
and Control Lab., ECE,
NCTU

Performance Comparison
between OPs

Related to Related to
bandwidth, current
poles sources

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Chao,Chao
P34
Optoelectronic System
and Control Lab., ECE,
NCTU Common Mode Feedback (CMFB)
 The advantages of full differential circuits over
single-ended counterparts such as
 Greater output swings
 Avoiding mirror poles
- then a higher closed-loop speed

 However, high-gain differential circuits require


common mode feedback.
 To understand this, consider circuit at right:
Implemented by
 Mismatches in the PMOS and NMOS current
mirrors defining ISS and ID3,4 create a finite error
between ID3,4 and ISS /2
 If ID3,4 > ISS /2, then both M3 and M4 must
enter the triode region so that their drain
currents fall to ISS /2
 If ID3,4 < ISS /2, then both VX and VY must
drop so that M5 enters the triode region,
thereby producing only 2ID3,4

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P35
Optoelectronic System
and Control Lab., ECE,
NCTU Common Mode Feedback (CMFB)

 The circuit at right mimics the previous current


mismatch.
 Since RP||RN is quite high, the voltage error may be large,
thus driving the p-type or n-type current source into
triode region.
 Thus, in high-gain amplifiers, the output CM level is quite
sensitive to device properties and mismatches and it
cannot be stabilized by means of differential feedback. V  ( I P  I N )( RP || RN )
 Thus a CMFB network must be added to sense the CM
level of the two outputs and accordingly adjust one of the
bias currents in the amplifier.
 A basic topology of CMFB at right

 Sense the output CM level

 Compare with a reference

 Return the error to the amplifier’s bias network

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P36
Optoelectronic System
and Control Lab., ECE,
NCTU

CMFB by Resistive Sensing

 Output CM level: Vout,CM = (Vout1 + Vout2)/2


 Resistive divider level:

Vout ,CM  ( RV
1 out 2  R2Vout1 ) /( R1  R2 )

 (Vout1  Vout 2 ) / 2, if R1 = R2
 R1 and R2 implemented by CMOS process
 Must be much larger than the output impedance
of the op amp so as to avoid lowering the open-
loop gain.
 Occupy a very large area.
 Suffer from substantial parasitic capacitance to the
substrate.

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P37
Optoelectronic System
and Control Lab., ECE,
NCTU CMFB by Source Followers
 Outputs are sensed by source followers to avoid previous drawbacks of resistance sensing.
 The CM level by this is lower than the real output CM level by VGS7,8
 R1 and R2 or I1 and I2 must be large enough (-> IX small enough) to ensure that M7 or M8 is not
starved when a large differential swing appears at the output; that is,
 If Vout2 is quite higher than Vout1, then I1 must sink both IX ≈ (Vout2 − Vout1)/(R1 + R2) and ID7

 Consequently, if (R1 + R2) or I1 is not sufficiently large (ΔI1 is too large compared to ID7 ), ID7
drops to zero and Vout,CM no longer represents the true output CM level
 This sensing method limits the differential output swings
 The sensed swing at each output is reduced by approximately VTH, a significant value in
low-voltage design

Part of

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P38
Optoelectronic System
and Control Lab., ECE,
NCTU
CMFB by MOS in Triodes

 Identical transistors M7 and M8 operate in


deep triode region [VDS<<2(VGS-VTH)]
 RP is a function of Vout1 + Vout2 but independent
of Vout2 − Vout1
 If the outputs rises together, then RP drops

 If they change differentially, one increases and


another decreases.
 Drawbacks: not stable feedback.

RP  Ron 7 // Ron8

1 1

W W
nCox(Vout1  VTH ) nCox (Vout 2  VTH )
L L
1
=
W
nCox (Vout1  Vout 2  2VTH )
L

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P39
Optoelectronic System
and Control Lab., ECE,
NCTU Feedbacks for CMFB via OP

 An amplifier detects the difference between Vout,CM and a reference voltage, VREF,
 Applying the result to the NMOS current sources with negative feedback
 With loop gain large, the feedback network forces the CM level of Vout1 and Vout2 to
approach VREF
 The feedback may also control only a fraction of the current to allow optimization of the
settling behavior.
 For example, each of M3 and M4 can be decomposed into two parallel devices, one biased
at a constant current and the other driven by the error amplifier

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P40
Optoelectronic System
and Control Lab., ECE,
NCTU Alternative for CMFB via OP

 In a folded-cascode op amp, the CM feedback


may control the tail current of the input
differential pair
 This method increases the tail current if Vout1
and Vout2 rise,
 Lowering the drain currents of M5−M6 and V  ( I P  I N )( RP || RN )
restoring (decreasing) the output CM level.

smaller smaller
larger larger
larger larger

larger
larger

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P41
Optoelectronic System
and Control Lab., ECE,
NCTU
CMFB by Triode MOS

 This CMFB tunes Ron7 || Ron8 in a feedback fashion such that


ID5 and ID6 exactly balance ID9 and ID10, respectively.
 With this balance, CM level can be calculated: Vout1,2
 Assuming ID9 = ID10 = ID,
 It must hold: (2ID )(Ron7|| Ron8)= (Vb − VGS5), i. e.,
Ron7 || Ron8
ID ID Vb  VGS 5 1
 RP 
2I D W
nCox ( )7,8 (Vout 2  Vout1  2VTH ) Vout1,2
L
2I D 1
 Vout 2  Vout1   2VTH
W V 
nCox ( )7,8 b GS 5V
L
2I D
where VGS 5   VTH 5
W
nCox ( )5
Triode MOSes L
 Drawbacks:
With (Ron7 || Ron8)
 The voltage drop across Ron7||Ron8 limits the output voltage
swing (Next slide alleviates this effect)
 To minimize this drop, M7 and M8 are usually quite wide
devices, introducing substantial capacitance at the output

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P42
Optoelectronic System
and Control Lab., ECE,
NCTU Alternative of CMFB by Triode MOS*
 CM is sensitive to Vb. If Vb is higher than expected,
the tail current of M1 and M2 increases and the output
CM level falls
 The feedback through M7 and M8 attempts to correct
this error, the overall change in Vout,CM depends on the
loop gain in the CMFB network
 Determine the sensitivity dVout,CM/dVb:
 M7,8 in deep triode region:
 gm7,8=µ nCox(W/L)7,8VDS7,8
 Feedback factor:
V2 VDS 7,8
  ( gm7  gm8 )( Ron 7 // Ron8 )  
V1 I 20
VGS 7,8  VTH 7,8
dVout ,CM 1 VGS 7,8  VTH 7,8
Thus,  
dVb closed
 VDS 7,8
when loop gain large

 Since VGS7,8 (i.e., the output CM level) is typically in


the vicinity of VDD/2, the above equation suggests
that VDS7,8 must be maximized to
 increase feedback factor
 decrease sensitivity
2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P43
Optoelectronic System
and Control Lab., ECE,
NCTU Defining Vb for Better Accuracy

 The idea is to define Vb by a current


mirror arrangement such that ID9 tracks
I1
 Suppose (W/L)15 = (W/L)9 and (W/L)16 =
(W/L)7 + (W/L)8
 Thus, ID9 = I1 only if Vout,CM = VREF
In practice  The circuit produces an output CM level
equal to a reference but it requires no
resistors in sensing Vout,CM

 In practice, since VDS15 ≠ VDS9, CLM


results in a finite error. ( The headrooms of
M15 and M9 are different)

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P44
Optoelectronic System
and Control Lab., ECE,
NCTU
For VDS15 = VDS9

 Transistors M17 and M18 reproduce at the drain of M15 a voltage equal to
the source voltages of M1 and M2, ensuring that VDS15 = VDS9

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P45
Optoelectronic System
and Control Lab., ECE,
NCTU
Two More CMFBs*
 Differential pair using diode-connected loads
 The output CM level, VDD − VGS3,4, is relatively well-defined (- no mismatch with ISS), but
the voltage gain is quite low, Av = gm1,2(ro1,2||ro3,4||1/gm3,4) ~ gm1,2/gm3,4
 Resistive CMFB
 To increase the differential gain, the PMOS device must operate as current sources for
differential signals
 For differential change at Vout1 and Vout2, node P is a virtual ground and the gain can be
expressed as Av = gm1,2(ro1,2||ro3,4||RF) -> much higher gain
 For perfect CM levels, M3 and M4 operate as diode connected devices (since no current
through RF)

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P46
Optoelectronic System
and Control Lab., ECE,
NCTU
Input CM Range of an OP

 Limitation: While the differential input swings are usually much smaller, the input
common-mode level may need to vary over a wide range in some applications
 Unity-gain buffer:
 The voltage swings are limited by the input differential pair rather than the output cascode
branch.
 Vin,min ≈ Vout,min = VGS1,2 + VISS, approximately one threshold voltage higher than the allowable
minimum provided by M5-M8
 If Vin < Vin,min: The MOS transistor operating as ISS enters the triode region, decreasing the
bias current of the differential pair and hence lowering the transconductance (then OP
gain).

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P47
Optoelectronic System
and Control Lab., ECE,
NCTU
Extending Input CM Range

 Incorporate both NMOS and PMOS differential


pairs such that when one is “dead”, the other is
“alive”
 Two folded-cascode op amps with NMOS and
PMOS input differential pairs
 As the input CM level approaches the ground
potential, the NMOS pair’s transconductance
drops, eventually falling to zero
 Nonetheless, the PMOS pair remains active,
allowing normal operation
 Conversely, if the input CM level approaches
VDD, M1P and M2P begin to turn off but M1 and
M2 function properly

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P48
Optoelectronic System
and Control Lab., ECE,
NCTU Slew Rate
 An Op used on feedback circuits exhibits a large-signal behavior
called “slewing,” the linearity of which vanishes during slewing.
 For a linear system (no feedback and op)

 Response of a linear circuit to input step

Since Vout  Vo [1  exp(t /  )], where   RC


dVout Vo t
Thus, Slew Rate =  exp  Vo
dt  
 A larger input step Vo  output rises more rapidly

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P49
Optoelectronic System
and Control Lab., ECE,
NCTU Rise Rate of an OP *

 Response of a linear op amp to step response


 Assume the op amp is linear, the current balance
X
at X
 R2   1 V
 Vin  Vout  A  Vout   out  Vout CL s
 R1  R2   Rout R1  R2

 Assuming R1+R2>>Rout, we have

Vout A
(s) 
Vin  R2   Rout CL 
1  A  1  s
 R1  R2   1  AR2 /( R1  R2 ) 

 The step response is given by

A   t  
Vout  Vo 1  exp    u (t )..............(*)
1 A
R2    
R1  R2

 The slope is always proportional to input Vo, before steady state.


 This type of response is called “linear settling.”

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P50
Optoelectronic System
and Control Lab., ECE,
NCTU Vout Rise based on Small-signals of an
Unit-Buffered ACM

 If Vin experiences a change of ΔV


 ID1 increases by (gmΔV/2), ID2 decreases by (gmΔV/2)
 The total small-signal current provided by the op amp equals (gmΔV)
 This current begins to charge CL
 Vout and VX rise.
 Feedback -> Reduce the difference between VG1 and VG2 and hence the
output current of the op amp
 Vout varies according to (*) in a linear way.

Assumed R1+R2>>Rout

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P51
Optoelectronic System
and Control Lab., ECE, Slewing Scenario based on Large-Signal of an
NCTU
Unit-Buffered ACM
low-to-high
slewing high-to-low

slewing

 Slewing during low-to-high transition -> nonlinear slewing


 M1 absorbs all of ISS
 M2 turns off
Initial Slope=ISS/CL
 As M2 remains off
 The feedback is broken
 The current charging CL is constant and independent of the input level
 As Vout rises, VX approaches Vin
 M2 turns on
 The circuit returns to linear operation
 Slewing during high-to-low transition
2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P52
Optoelectronic System
and Control Lab., ECE,
NCTU

About Slew Rate

 The large-signal speed may be limited by the slew rate


 simply because the current available (fixed finite ISS -> fixed finite
initial slope ) to charge and discharge the dominant capacitor in
the circuit is small.

 Since the input/output relationship during slewing is


nonlinear, the output of a slewing amplifier exhibits
substantial distortion.
 For example, if a circuit is to amplify a sinusoid Vosinω0t (in steady
state), then its slew rate must exceed Voω0 (Why?)

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P53
Optoelectronic System
and Control Lab., ECE,
NCTU Slew Rates of TCO at Two
Different Stages

 When a large differential input


applied (M1 or M2 off), Vout1 and  (Vout1- Vout2) exhibits a slew rate
Vout2 , individually, appears as equal to ISS/CL.
ramps with slopes equal to
±ISS/(2CL)

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P54
Optoelectronic System
and Control Lab., ECE,
NCTU

Slew Rate of Unit-Buffered FDTCO

Current Current
Mirror Mirror

 If IP≧ISS,
 The slew rate is equal to ISS/CL, independent of IP.

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P55
Optoelectronic System
and Control Lab., ECE,
NCTU Initial Output Drop when ISS>>IP

 If ISS>IP, during slewing


 M3 turns off
 VX falls to a low level such that M1 and the tail current source enters the
triode region
 ISS becomes small such that ISS<IP , then VX rises and VG2 rise to turn on M2.
 Thus, for the circuit to return to equilibrium after M1 turns on
 VX must experience a large swing
 Slow down the settling
 It is not recommended.

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P56
Optoelectronic System
and Control Lab., ECE,
NCTU Clamped Circuits in FDTCO*
To fix initial output drop

 Add clamp transistors M11 and M12.


IP  Part of (ISS –IP) flows through M11 or M12,
requiring only enough drop in VX or VY
ISS
to turn on one of these transistors (like
M3).
ID12  The current through the clamped circuit
(larger) provides portion of current to
ID3
differential pairs.

 M11 and M12 clamp the two nodes


relatively to VDD (a more aggressive
approach) by VTHN during slewing.
 Since the equilibrium values of VX and VY
are usually higher than VDD-VTHN (achievable
smaller headroom by M9 and M10), M11 and M12
are off during small-signal operation.

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P57
Optoelectronic System
and Control Lab., ECE,
NCTU

Prices of Increasing Slew Rate

 For a given load capacitance, to increase the slew rate


 ISS must be increased.
 All of the transistors must be made proportionally
wider - generate large currents.
 The power dissipation and the input capacitance
are increased
 Note that if the device current and width scaled together,
gmro of each transistor and the open-loop gain of the op
amp remain constant.

W 1 WL W
g m ro  2 I  
L I I I

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P58
Optoelectronic System
and Control Lab., ECE,
NCTU

Power Supply Rejection Ratio


 Since the diode-connected M3 “clamps” node X to VDD * Saturated M3,4:
 VX experiences approximately the same supply change as 1 W 
I D3   pCOX   VDD  VG  VTH 
2

from VDD 2  L 3,4


Fixed Clamped
 Vout experiences the same supply change.
 In other words, the gain from VDD to Vout is (if the circuit
is perfectly symmetric, Vx=Vout)

Vout
1
VDD

 Power Supply Rejection Ratio (PSRR) is defined by

the gain from the input to the output


PSRR 
the gain from the supply to the output

 At low frequencies:
Vout Vout
PSRR   g mN (roP // roN ) /1  g mN (roP // roN )
Vin VDD
* PSSR increases with voltage gain of an OP.

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P59
Optoelectronic System
and Control Lab., ECE,
NCTU
Noise in TCO
 To identify the dominant sources of noise - to change the gate voltage of each transistor
by a small amount and predict the effect at the output.

* At relatively low frequency, the  The input-referred noise voltage per unit bandwidth is
cascode devices contribute given by
 2 2 g m7,8  KN KP g m2 7,8
negligible noise, leaving M1-M2 Vn  4kT  2
2
2 2 2 2
 3g 3 g  (WL ) C f (WL)7,8 Cox f g m2 1,2
and M7-M8 as the primary noise  m1,2 m1,2  1,2 ox

sources See pg33 in Class 7 where KN and KP denote the 1/f noise coefficients of NMOS
and PMOS devices, respectively

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P60
Optoelectronic System
and Control Lab., ECE,
NCTU Noise in Folded TCO
(Thermal Noise)

 Low noises for the cascode devices is negligible at low


frequencies
 M1-M2, M7-M8, and M9-M10 as potentially significant
sources
 Thermal noise:
 2 
Vn2,out |M 7 ,8  2  4kT g m2 7,8 Rout
2

 3 g
 m 7,8 
M7, M8 are uncorrelated

 2 
Vn2,out |M 9,10  2  4kT g m2 9,10 Rout
2

 3g m9,10 
 2 
Vn2,out |M1,2  2  4kT g m2 1,2 Rout
2

 3 g m1,2 

 With Av=gm1,2Rout, the total input-referred


thermal noise is
 2 2g 2g 
Vn2,in  8kT   m2 7,8  m29,10 
 3g m1,2 3g m1,2 3g m1,2 
Larger noise than the telescopic counterpart
2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P61
Optoelectronic System
and Control Lab., ECE,
NCTU Noise in Folded TCO
(Flicker Noise)

 Flicker noise (1/f noise)


 KN 1 2 
V 2
|  2
n ,out M 9,10 g m 9,10 Rout 
2

 OX
C (WL ) 9,10 f 
 KP 1 2 
Vn2,out |M 7 ,8  2  2
g m 7,8 Rout 
 COX (WL)7,8 f 
 KN 1 2 
Vn2,out |M1,2  2  g m1,2 Rout 
2

 OX
C (WL )1,2 f 

 With Av=gm1,2Rout, the otal input-referred


thermal noise is

Vn2,out ,tot
V 2
n ,in 
Av2
2K N  1 1 g m2 9,10  2 K P 1 g m2 7,8
   2  2
COX f  (WL )1, 2 (WL ) 9,10 g m1,2   COX f (WL)7,8 g m1,2

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P62
Optoelectronic System
and Control Lab., ECE,
NCTU
Noise in Folded TCO
(Conclusive Remarks)

 The overall noise:


 2 2g 2g  2K N  1 1 g m2 9,10  2 K P 1 g m2 7,8
V 2
n ,in  8kT   m2 7,8  m29,10     2  2
 3g m1,2 3g m1,2 3g m1,2  Cox f  (WL )1,2 (WL ) 9,10 g m1,2   Cox f (WL)7,8 g m1,2

 The noise contribution of the PMOS and NMOS current sources


increases in proportion to their transconductances (gm)
 Trade-off between output swings and the input-referred noise:

2I D
gm 
(VGS  VTH )
noise overdrive voltage output voltage swing

Trade-off

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P63
Optoelectronic System
and Control Lab., ECE,
NCTU
Noise in Two-Stage OP

 Total voltage gain: Av  gm1 (ro1 // ro3 ) * gm5 (ro5 // ro 7 )


 In the 2nd stage (Two CS stages) :
 The noise current of M5 and M7 flows through ro 5 // ro 7

2 1 16kT g m5  g m7
Vn2 |M 58  2*4kT ( g m5  g m7 )(ro5 // ro 7 ) 2 * 2 
3 Av 3 g m2 1 g m2 5 (ro1 // ro3 )2
 In the 1st stage:
2 g m1  g m3
Vn2 |M14  2*4kT
3 g m2 1
 Total input-referred thermal noise:

16kT 1  g m5  g m 7 
Vn2,tot   m1
g  g m3  
3 g m2 1  g m2 5 (ro1 // ro3 )2 

smaller than
-> can be neglected

2007/11/20
2019/05/19 Paul Paul
C.-P. C.-P.
Chao,Chao
P64

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