Professional Documents
Culture Documents
Brian Fortman
DesignDRIVE marketing manager
C2000™ MCU
Texas Instruments
Introduction
At the heart of the matter of improving servo drive performance is the system’s current-
loop performance or torque response. The current loop is the linchpin upon which
the performance of the rest of the system depends. Even though several alternative
architectures can provide a pathway to a greater current-loop bandwidth, some are
more effective and cost-efficient than others. Only one solution in particular can
optimize or eliminate the design trade-offs involving long, drawn-out and complex
development programs, expensive bill of materials (BOM) costs, excessive power
consumption, cumbersome thermal-management strategies and others. This
solution, which is based on TI’s commercial-off-the-shelf (COTS) C2000™ real-time
microcontrollers (MCUs) and the enhanced DesignDRIVE development platform,
increases the bandwidth of a servo motor drive’s current control loop.
A faster current loop pays off in servo motor control 2 July 2017
loops by nearly 10 times or even higher. As a processing capabilities to accommodate shorter
result, a faster current loop is essential to higher feedback cycles and retain a lower carrier frequency
system performance. to avoid the undesirable power and thermal
trade-offs. To augment the system’s processing
Current loop close-up resources, some designs have employed current-
The current loop controls the torque in a servo loop processing data paths in a field programmable
motor by manipulating the pulse-width modulator gate array (FPGA) in addition to the MCU, but this
(PWM) outputs that drive an inverter. The motor only addresses the processing half of the equation
currents are monitored and fed back to the current- and comes with its own set of strings.
loop controller and the controller updates the PWM
outputs if necessary. The current-loop feedback FPGA architectures
path quantifies the analog output of the motor Adding an FPGA does not eliminate the need for
current sensor with a high-precision analog-to- an MCU in a servo motor drive design because the
digital converter (ADC), and then feeds the result MCU controls the speed and position feedback
to the current-loop controller. Several different loops, and in some cases the system’s user
modules of field-oriented control (FOC) algorithms interface and connectivity. Inserting an FPGA
process this sample before the controller makes any into the current control loop has a ripple effect
adjustments to the PWM’s outputs. throughout the rest of the design. See Figure 1
Many conventional proportional integral (PI) current- on the following page. To accommodate the entire
loop controllers limit the current-loop bandwidth current control loop, the FPGA will require custom
to approximately 10 percent of the PWM carrier design work to incorporate PWM generation,
frequency, which is typically in the 10-kHz range. inverter protection circuitry and logic to control the
This would yield a current-loop bandwidth of 1 kHz. analog sampling. This design work will complicate
To increase the bandwidth, some drive systems system development, drive up the gate count
increase the carrier frequency to 30 kHz or higher, and cost of the FPGA, and increase design and
will also increase the inverter switching losses and In addition, most FPGAs do not have embedded
demand higher processing performance from the ADCs capable of sufficient performance and
digital control system. A higher switching frequency resolution for servo motor-control applications,
requires increased gate-drive power, which then thus necessitating the design of discrete ADCs and
increases the size and complexity of the system’s analog comparator circuitry into the system. Also,
power supply. Plus, the higher switching losses will the FPGA will likely require parallel input/output
mean additional heat dissipation, necessitating more (I/O) interfaces to minimize data-transfer latencies
extensive thermal-management strategies such as from the ADC and enable fast communications with
larger, heavier and more expensive heat sinks, fans the MCU. Again, the FPGA’s pin count will go up,
or coolants. along with cost and board-space requirements.
Clearly, the historical solutions for increasing And lastly, an FPGA design will typically demand a
current-loop bandwidth come with strings attached. more complex power subsystem, possibly requiring
The cleanest, most effective architecture would additional power rails and higher currents than the
simultaneously address the need for improved MCU and other components would typically need.
A faster current loop pays off in servo motor control 3 July 2017
Issue:
- Requires additional and
more complex power
MCU FPGA supply
power supply Multi-rail power supply
Issue:
- Requires customers own
Control FPGA PWM and Protection design
subsystem - Higher frequency, thus Isolated
PWM dissipates additional power gate drive Three-
phase
MCU inverter
Position
Protection
control
control
Speed
Isolated
Current
control
shunt current
buffer
Fast,
Program
code
Parallel port precise
Fluxgate
ADC sensors
FPGA
code
MCU core
EMIF
Issue: PM
Parallel motor
port
- Requires costly external
ADC and comparators
Issue:
-Requires
Requireshigher
higherpin
pincount
countdevices
FPGAs
to to support
support communications to
low-latency
ADC and
communications to MCU
ADC and MCU
Of course, once an FPGA is present in a design, (FCL) software. The DesignDRIVE development
it invariably becomes the home for functionality platform with FCL software vastly simplifies the
that may have been previously implemented in design process while overcoming the less desirable
discrete devices or not included in the system at trade-offs.
all. In a servo motor-control application, this could FCL software, quite simply, breaks many of the
mean integrating delta-sigma ADC filters, encoder long-held assumptions in current-loop design.
interfaces, pulse-train output generation and other For instance, designers of servo motor control
capabilities. Once this trend begins, the logical end applications have for years placed limitations on the
is a very large, high-pin-count, expensive FPGA. current-loop bandwidth because they assumed that
the controller could update the PWM only once per
Fast Current Loop software
cycle of the control loop. Now, with an integrated
An effective alternative that avoids many of the high-performance successive approximation register
challenges that arise with the addition of an (SAR) ADC, ADC post-processing hardware,
expensive FPGA to a servo-control application trigonometric math accelerator and other cycle-
would be to implement these functions in the MCU. scavenging resources, C2000 MCUs can sample
Outside of TI’s C2000 family of real-time MCUs, the motor currents, convert them to digital data,
few if any such capable MCUs exist. TI harnessed process the data and update the PWM generator
two decades of real-time industrial control system in less than 1 µs. The field-oriented control (FOC)
design experience when applying C2000 MCUs processing and PWM update takes less than
to the development of the new Fast Current Loop 500 ns. Because of FCL software and C2000 MCU
A faster current loop pays off in servo motor control 4 July 2017
ePWM immediate mode capabilities, subcycle PWM as Sigma-Delta filters, analog comparators and
updates occur as soon as possible, instead of PWM protection circuits save the system-level
waiting for an entire control loop cycle to transpire. costs when compared to adding these external
Designers also assumed that achieving a higher components. The Position Manager solutions for
current-loop bandwidth would require higher absolute encoder interfaces as well as Pulse Train
carrier frequencies. So, for example, increasing the Output generation reduce the need to add these
bandwidth by a factor of 3 from 1 kHz to 3 kHz logic gates as well. With the release of the Fast
would require increasing the carrier frequency from Current Loop software, the system-level functions
that FCL can increase the current-loop bandwidth loop design has been the stability of the current-
by a factor of 3 from 1 kHz to approximately loop controller at high speeds. Digital or transport
3.3 kHz while maintaining a carrier frequency of delays progressively reduce the phase margin of
10 kHz. Therefore, using FCL software avoids the the current control loop at higher speeds, eventually
trade-offs of increased power consumption, greater leading to a loss of control. Traditional controllers
heat dissipation, and more complex and expensive in the current loop do not model these digital
thermal-management strategies. delays well.
The TMS320F28379 MCUs are highly integrated However, FCL software includes an efficient
for industrial drive systems. On-chip features such algorithm that assumes a more appropriate system
MCU
Power supply
HRPWM Isolated
“Custom” PWM Three-
Type4 gate drive
F
phase
MCU P
C
o C
S o T C “Custom”
PWM trip & inverter
Comparator
s o
subsystem
Isolated
i n
p
e
n
t
o o Protection
XBAR shunt current
C28x C
t t
i r
e r r n Fast,
4×
buffer
Program d o
Code
o o
l q t Precise
12-bit
DSP w/
n l Fluxgate
3.5
ADCMSPS
L
u r sensors
e o
TMU
MCU Core
l
Sinc
SD Filters
filters
DS isolated
ADCs
Position PM
motor
Sensor
TMS320F28379D/S
Position
Management
2000 MCU™ manager
Pulse Train Line Position
drive control Output (PTO) interface sensor
system-on-chip
to PLC
Figure 2. C2000 system integration for industrial drives.
A faster current loop pays off in servo motor control 5 July 2017
model, compensating for the inherent transport makes a C2000 MCU in a servo-drive application
delay of the system. This is embodied in the a cycle scavenger, saving processor cycles
DesignDRIVE complex controller (CC) and results in over the entire loop and transforming what may
perfect pole-zero cancellation at all times, ensuring have been longer sequential steps into shorter
stability at higher speeds. simultaneous processes.
The hardware and technology breakthroughs that For example, 200-MHz C28x processing cores are,
contribute to FCL software have emerged from of course, critical for breaking apart the workload
more than 20 years of experience in embedded to optimize parallel processing, but so is the real-
processing and motor-control systems by the time deterministic architecture that surrounds
C2000 MCU DesignDRIVE engineers. Certainly, them. Because the architecture keeps the system’s
the MCUs themselves have been endowed with processing as jitter-free as possible, cycles are not
powerful, high-performance processing units, wasted recovering from timing issues or running
coprocessors and specialized processing units, but error-correction routines. There are no data-transfer
the C2000 MCU’s architecture is just as essential latencies between the ADC and the C28x cores,
because it enables a high degree of real-time or between the cores and the PWM. Transferring a
parallel processing through very low latencies sample from the ADC to the C28x cores or updating
and high processing determinism. Ultimately, this the PWM takes only a single cycle. See Figure 3.
A faster current loop pays off in servo motor control 6 July 2017
Several C2000 MCUs, such as the Delfino™ factors in direct opposition with one another. Simple
TMS320F28379D processor, include a powerful yet effective solutions may be hard to come by,
ADC post-processing block capable of performing but fortunately, TI’s experience and expertise in
certain sample-preparation routines in dedicated real-time industrial drive control systems has led to
hardware that the C28x cores would normally have many enhancements to the C2000 family of real-
executed, saving cycles on the main processors time MCUs.
and freeing them to perform other tasks in parallel. The DesignDRIVE developers kit features the latest
The cores themselves have been equipped with enhancement, FCL software. Taking advantage of
coprocessors and specialized processing units a real-time cycle-scavenging architecture, high-
that prove useful in servo-control applications. For performance processing resources and the fast
instance, the main processing cores can offload data throughput of C2000 MCUs to significantly
encoder-feedback processing to the control law increase the current control-loop bandwidth, FCL
accelerator (CLA) coprocessor, which excels at software achieves subcycle updates of the PWM
high-level mathematical processing. Moreover, both in less than 1 µs and without the assistance of
the FOC processing and the CC use a specialized external processing elements like an FPGA or ADC.
processing unit, the trigonometric math unit (TMU). Compared to FPGA-based systems, a C2000 drive
With the aid of the TMU, you can improve Park control system-on-chip with FCL software delivers
transform cycle performance by a factor of 8 over similar performance, while simplifying servo drive
comparable MCUs in the industry. In addition, development and reducing system costs, power
the C28x core’s 32-bit floating-point processing complexities and board space. Compared to
accelerates the execution of several different types traditional MCU-based systems, FCL software can
of mathematically intense calculations used by potentially triple a drive system’s torque response
the FCL algorithms, such as minimum/maximum, and double its maximum speed without increasing
compare and square root. the carrier frequency.
Conclusion
During the development of a servo motor-drive
For more information
application, designers face a diverse set of subtle For additional information about Fast Current
trade-offs, many times placing high performance, Loop software, visit our website.
cost effectiveness, power efficiency and other
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