Complex Circuit Layouts

C (A+B) + AB

Single diffusion runs Multiple Diffusion runs

4-Input NAND Gate “Sticks”

Layout

Step 1: order
gate wires
on poly

OUT

I1

I2

I3
Step 2:
I4
interconnect

2
 Euler Paths

–
–

–
–
–

–
–

Finding Gate Ordering: Euler Paths

3
 A More Complex Example

A (B+C) + DE

D E
YP –
B

XP A –
C –
OUT –
–
A D

XN YN

B C E

A More Complex Example

A (B+C) + DE

D E

YP
B

XP
A
C –
OUT –
–
A D

XN YN
B C E

4
 Sticks Layout
A (B+C) + DE

D E
YP

XP A
C

OUT

A D

XN YN

B C E

Wiring Tracks and Spacing

and
Area Estimation

5
 Review: Wiring Tracks
wiring track
– pitch

Review: Well spacing

–
–

6
First Cut Area Estimation

–
–

Example: NAND3

7
 Example: O3AI

–
Y ( A B C)D

Example: O3AI

–
Y ( A B C)D

8
 Example: O3AI

–
Y ( A B C)D

Another Example Question 1.17

–
–
–

9
Typical Layout Densities (Table 1.10)

Random Logic 1000-1500/transistor

Datapath 250-750/transistor

SRAM 1000/bit

DRAM 100/bit

ROM 100/bit

10