electronics

Article
Cell Voltage Equalizer Using a Selective Voltage
Multiplier with a Reduced Selection Switch Count for
Series-Connected Energy Storage Cells
Masatoshi Uno * , Teruhisa Ueno and Koji Yoshino
College of Engineering, Ibaraki University, Hitachi 316-8511, Japan; 19nm609g@vc.ibaraki.ac.jp (T.U.);
18nm658l@vc.ibaraki.ac.jp (K.Y.)
* Correspondence: masatoshi.uno.ee@vc.ibaraki.ac.jp; Tel.: +81-294-38-5098




Received: 26 September 2019; Accepted: 2 November 2019; Published: 7 November 2019


Abstract: Cell voltage equalization is mandatory to eliminate voltage imbalance of series-connected

energy storage cells, such as lithium-ion batteries (LIBs) and electric double-layer capacitors (EDLCs),
to ensure years of safe operations. Although a variety of cell equalizers using selection switches have
been proposed, conventional techniques require numerous switches in proportion to the cell count
and are prone to complexity. This paper proposes a novel cell voltage equalizer using a selective
voltage multiplier. By embedding selection switches into the voltage multiplier-based cell voltage
equalizer, the number of selection switches can be reduced in comparison with that in conventional
topologies, realizing the simplified circuit. A prototype for twelve cells was built, and an equalization
test using LIBs was performed. The voltage imbalance decreased down to approximately 20 mV by
the proposed equalizer, and the standard deviation of cell voltages at the end of the equalization test
was as low as 10 mV, demonstrating its equalization performance.

Keywords: electric double-layer capacitor (EDLC); equalization; lithium-ion battery (LIB);

selection switch; voltage imbalance

1. Introduction
In general, voltages of series-connected energy storage cells, such as lithium-ion batteries (LIBs) and
electric double-layer capacitors (EDLCs), gradually become imbalanced due to nonuniform individual
cell characteristics in capacitance, internal impedance, coulombic efficiency, and self-discharge rate.
Temperature mismatch in a battery pack or module also leads to the occurrence of voltage imbalance
because the self-discharge rate is dependent on temperature—the higher the temperature, the faster
the self-discharge will be [1]. Some cells in a voltage-mismatched pack might be overcharged
and -discharged due to voltage imbalance during charging and discharging processes, respectively.
Charging–discharging energy storage cells beyond safety boundaries likely results in premature
degradation and hazardous situations of fire or, in the worst case, an explosion. Thus, cell voltage
equalization is mandatory to eliminate the voltage imbalance to prevent operations beyond safety
boundaries [2].
Various kinds of cell voltage equalizers have been proposed and commercialized.
Adjacent cell-to-cell equalizers based on non-isolated bidirectional converters, such as PWM
converters [3,4] and switched capacitor converters [5–8], are the most straightforward approach
for cell equalization. However, in addition to a large number of converters necessary for adjacent
cell-to-cell equalization architectures, energy transfer is limited only between neighboring cells,
collectively increasing power conversion loss in the course of equalization, especially in large-scale
systems comprising numerous cells connected in series.

Electronics 2019, 8, 1303; doi:10.3390/electronics8111303 www.mdpi.com/journal/electronics

Electronics 2019, 8, 1303 2 of 12
Electronics 2019, 8, x FOR PEER REVIEW 2 of 12

On
On the
the other
other hand,
hand, pack-to-cell
pack-to-cell equalizers,
equalizers, which
which areare based
based onon aa single-input–multi-output
single-input–multi-output
converter,
converter, can achieve reduced numbers of converters and active switches[9–20].
can achieve reduced numbers of converters and active switches [9–20]. AA conventional
conventional
pack-to-cell
pack-to-cell equalizer based on a voltage multiplier is shown in Figure 1 as an example. This topology
equalizer based on a voltage multiplier is shown in Figure 1 as an example. This topology
requires
requires only
only two
two switches,
switches, regardless
regardless ofof cell
cellcount,
count,achieving
achievingaasimplified
simplifiedcircuit.
circuit. This
This equalizer
equalizer
automatically
automaticallysupplies
suppliesanan
equalization current
equalization toward
current the least
toward thecharged cell having
least charged cellthe lowestthe
having voltage in
lowest
the pack,in
voltage realizing
the pack,therealizing
automatic equalization
the automatic even without even
equalization feedback control.
without However,
feedback this automatic
control. However,
equalization cannot be simply applied to LIBs because the relatively large voltage drop
this automatic equalization cannot be simply applied to LIBs because the relatively large voltage across internal
drop
impedances of LIBs hinders and slows down the voltage equalization process.
across internal impedances of LIBs hinders and slows down the voltage equalization process.

Figure 1.
Figure 1. Conventional
Conventional equalizer
equalizer using
using an
an inverter
inverter and
and voltage
voltage multiplier
multiplier[19].
[19].

Meanwhile,cell-to-cell
Meanwhile, cell-to-cellequalizers
equalizersusingusingcellcell selectin
selectin switches
switches have
have been been intensively
intensively developed
developed for
for battery
EV EV battery systems
systems [21–35].
[21–35]. TargetTarget cells having
cells having the lowest
the lowest or highest
or highest voltagesvoltages in the
in the pack are pack are
selected
selected
by the cell byselection
the cell selection
switches so switches so that
that their stored their stored are
energies energies are exchanged
exchanged to equalize to cell
equalize cell
voltages,
voltages, regardless
regardless of voltage
of voltage drops acrossdrops across
internal internal impedance.
impedance. Typical equalization
Typical equalization systems usingsystems using
cell selection
cell selection
switches switches
are listed are listed
in Figure 2. Iningeneral,
Figure selection
2. In general, selection
switches switches are switches
are bidirectional bidirectional switches
consisting of
consisting
two of two metal-oxide-semiconductor
metal-oxide-semiconductor field-effect
field-effect transistors transistorsconnected
(MOSFETs) (MOSFETs) connected in
back-to-back back-to-
order
back
to block in bidirectional
order to block current bidirectional
flow. The directcurrent flow. The
cell-to-cell direct using
equalizer cell-to-cell equalizer isolated
a unidirectional using a
unidirectional
converter (e.g., aisolated converter (e.g.,
flyback converter), a flyback
as shown in Figure converter),
2a, requiresas4nshown
selection in switches,
Figure 2a,and requires
therefore,4n
selection
the systemswitches,
is prone to and therefore,[21,22].
complexity the system
Needless is prone
to say,toa complexity
unidirectional [21,22].
switch Needless to say, a
is also necessary
unidirectional
for the isolatedswitch is alsoWith
converter. necessary for the isolated
the pack-to-cell converter. With
or cell-to-pack the pack-to-cell
equalizers or cell-to-pack
with selection switches
equalizers
(Figure with selection
2b) [23–26], the numbersswitches (Figure switches
of selection 2b) [23–26], can the numbers
be halved (i.e.,of2n),
selection
but thereswitches
is still acan
room be
halved
for (i.e., 2n), but
improvement. Thethere is still aequalizer
pack-to-cell room forwith improvement. The pack-to-cell
polarity switches (Figure 2c)equalizer
can furtherwith polarity
reduce the
switches
switch (Figure
count as low2c) as + 5 [27].reduce
cann further the switch
The direct countequalizer
cell-to-cell as low aswith
n + 5an[27]. The storage
energy direct cell-to-cell
medium
equalizer
(Figure 2d),with
such anasenergy storage
a capacitor, mediumresonant
inductor, (Figure 2d),tank,such
etc.,as
cana capacitor,
reduce theinductor, resonant
switch count as lowtank,
as
n + 1 [28–35], but selection switches in many existing direct cell-to-cell equalizer must operate at a
etc., can reduce the switch count as low as n + 1 [28–35], but selection switches in many existing direct
cell-to-cell
high switchingequalizer must operate
frequency, for which at anumerous
high switching frequency, for
high-frequency gatewhich
drivers numerous
are alsohigh-frequency
indispensable.
gate drivers are
Furthermore, four also indispensable.
unidirectional Furthermore,
switches are also four unidirectional
necessary in the caseswitches are also in
of the topology necessary
Figure 2d. in
the case of the topology in Figure 2d. Since each bidirectional selection
Since each bidirectional selection switch and unidirectional switch requires a gate driver as well as switch and unidirectional
switch
its requires
auxiliary a gate
power driverthe
supply, as well
switch as count
its auxiliary
can bepower supply,
an index the switchthe
to represents count can complexity.
circuit be an index
to represents
The number ofthe circuit complexity.
selection switches should The number
desirably ofbeselection
reduced switches
as muchshould desirably
as possible be reduced
to simplify the
as much
circuit and astopossible
reduce to thesimplify
cost. the circuit and to reduce the cost.
This paper proposes a novel pack-to-cell equalizer using a selective voltage multiplier.
By embedding cell selection switches into a voltage multiplier-based cell voltage equalizer, the numbers
of selection switches can be reduced to n, achieving the simplified circuit. Section 2 describes
the proposed equalizer and its major features, followed by the operation analysis in Section 3.
The experimental results of an equalization test for twelve LIB cells connected in series are shown in
Section 4.
Electronics 2019,
Electronics 8, 8,
2019, 1303
x FOR PEER REVIEW 3 3ofof
1212

(a) (b)

(c) (d)

Figure 2. Conventional cell equalizers with selection switches: (a) direct cell-to-cell equalizer based
Figure 2. Conventional cell equalizers with selection switches: (a) direct cell-to-cell equalizer based
on an isolated converter; (b) pack-to-cell equalizer; (c) pack-to-cell equalizer with polarity switches;
on an isolated converter; (b) pack-to-cell equalizer; (c) pack-to-cell equalizer with polarity switches;
and (d) direct cell-to-cell equalizer with energy storage medium.
and (d) direct cell-to-cell equalizer with energy storage medium.
2. Proposed Cell Voltage Equalizer Using Selective Voltage Multiplier
This paper proposes a novel pack-to-cell equalizer using a selective voltage multiplier. By
2.1. Topology cell selection switches into a voltage multiplier-based cell voltage equalizer, the numbers
embedding
of selection switches
The proposed can equalizer
voltage be reduced to n,
using theachieving
selective the simplified
voltage circuit.
multiplier Section
for four cells2connected
describes in
the
proposed equalizer and its major features, followed by the operation analysis in Section
series is shown in Figure 3 as an example. This equalizer consists of the resonant inverter and voltage3. The
experimental
equalizer results of
with selection an equalization
switches embedded.test for twelve with
In comparison LIB cells connected in
the conventional series areequalizer
pack-to-cell shown in
Section 4.
using the voltage multiplier (see Figure 1), coupling capacitors C –C are replaced with selection
1 4
switches S1 –S4 . S1 –S4 are bidirectional switches comprising two MOSFETs connected back-to-back,
2. Proposed Cell Voltage Equalizer Using Selective Voltage Multiplier
as shown in the inset of Figure 3. The symmetric half-bridge resonant inverter is employed, but its
fundamental operation principle is identical to that of the conventional equalizer shown in Figure 1.
2.1. Topology
High- and low-side switches, QH and QL , are alternately driven in a complementary mode with a
The duty
fixed 50% proposed
cycle voltage equalizer
to generate using
resonant ACthe selective
current voltage
for the multiplier
transformer for four side.
secondary cells connected
A selectionin
series corresponding
switch is shown in Figure 3 as
to the an example.
least Thisisequalizer
charged cell activated,consists
and theofAC
thecurrent
resonant inverter and
transferred voltage
from the
equalizer with selection switches embedded. In comparison with the conventional
resonant inverter is rectified by the voltage multiplier, producing a DC equalization current for thepack-to-cell
equalizer
least chargedusing
cell. the
Thevoltage
detailedmultiplier
operation(see Figureis 1),
principle coupling
discussed in capacitors
Section 3. C1–C4 are replaced with
selection switches S1–S4. S1–S4 are bidirectional switches comprising two MOSFETs connected back-
to-back, as shown in the inset of Figure 3. The symmetric half-bridge resonant inverter is employed,
but its fundamental operation principle is identical to that of the conventional equalizer shown in
Figure 1.
 High- and low-side switches, QH and QL, are alternately driven in a complementary mode with
a fixed 50% duty cycle to generate resonant AC current for the transformer secondary side. A
selection switch corresponding to the least charged cell is activated, and the AC current transferred
from the2019,
Electronics resonant
8, 1303 inverter is rectified by the voltage multiplier, producing a DC equalization current
4 of 12
for the least charged cell. The detailed operation principle is discussed in Section 3.

for four
Figure 3. Proposed equalizer with selective voltage multiplier for four cells
cells connected
connected in
in series.
series.

2.2.
2.2. Features
Features
Conventional
Conventional selection
selection switch-based
switch-based equalizers
equalizers require
require at least nn ++ 11 bidirectional
at least bidirectional selection
selection
switches, as introduced in Section 1. The topology in Figure 2d comprises
switches, as introduced in Section 1. The topology in Figure 2d comprises the least number of the least number of selection
switches
selection (i.e., n + 1),(i.e.,
switches but itn requires
+ 1), but four
it unidirectional
requires four switches.
unidirectionalWith the proposed
switches. Withequalizer, on the
the proposed
other hand, the number of bidirectional selection switches and unidirectional
equalizer, on the other hand, the number of bidirectional selection switches and unidirectional switches can be reduced
to as low as
switches n and
can two, respectively,
be reduced to as lowreducing
as n andthe circuit
two, complexityreducing
respectively, and cost.the
Furthermore, the selection
circuit complexity and
switches in the proposed equalizer do not need to operate at a high frequency,
cost. Furthermore, the selection switches in the proposed equalizer do not need to operate and therefore, gate
at adriver
high
circuits for and
frequency, selection switches
therefore, gate can be circuits
driver simplerfor andselection
less powerful
switches than
canthose needed
be simpler andin less
conventional
powerful
cell-to-cell equalizer using selection switches [28–35]. Although diodes D –D and
than those needed in conventional cell-to-cell equalizer using selection switches [28–35]. Although
1 8 smoothing capacitors
C o1 –Co4Dare
diodes additionally necessary for the voltage multiplier, these are passive components and do not
1–D8 and smoothing capacitors Co1–Co4 are additionally necessary for the voltage multiplier,
need
these auxiliary
are passive circuits. Hence,and
components the added
do not complexity
need auxiliary duecircuits.
to the passive
Hence, components in the voltage
the added complexity due
multiplier would be minor compared to selection switches, for which auxiliary
to the passive components in the voltage multiplier would be minor compared to selection switches, circuits, including gate
drivers
for whichandauxiliary
power supplies, are indispensable.
circuits, including gate drivers and power supplies, are indispensable.
The
The resonant inverter in the proposed equalizer
resonant inverter in the proposed equalizer is is essentially
essentially identical
identical toto that
that in
in the
the convention
convention
equalizer shown in Figure 1 [19]. It operates in a discontinuous conduction
equalizer shown in Figure 1 [19]. It operates in a discontinuous conduction mode (DCM), mode (DCM), by by
which an
which
equalization
an equalization current supplied
current to cell(s)
supplied can becan
to cell(s) automatically constant
be automatically even without
constant feedbackfeedback
even without control.
This inherent constant current characteristic is a suitable feature for energy storage
control. This inherent constant current characteristic is a suitable feature for energy storage devices devices because
LIBs andLIBs
because EDLCs andare essentially
EDLCs a voltageasource.
are essentially voltage source.
3. Operation Analysis
3. Operation Analysis
3.1. Operation Modes
3.1. Operation Modes
The operation analysis is performed for the case that B1 is the least charged cell in the battery pack
The operation analysis is performed for the case that B1 is the least charged cell in the battery
and S1 is activated. All circuit elements are assumed ideal unless otherwise noted. Theoretical key
pack and S1 is activated. All circuit elements are assumed ideal unless otherwise noted. Theoretical
operation waveforms and current flow paths are shown in Figures 4 and 5, respectively.
key operation waveforms and current flow paths are shown in Figures 4 and 5, respectively.
Mode 1 (0 ≤ t < T1 ) (Figure 5a): The gating signal for QH , vGS.H , is applied to turn on QH ,
achieving zero current switching (ZCS) turn-on. Lkg and Cr start resonating, and the current of Cr ,
iCr , sinusoidally changes. On the transformer secondary side, the resonant current flows through the
activated selection switch of S1 and the high-side diode corresponding to B1 , D2 . This operation mode
lasts until iCr becomes zero.
Mode 2 (T1 ≤ t < T2 ) (Figure 5b): QH and QL are still on and off, respectively. The polarity of iCr
is reversed, while the low-side diode corresponding to B1 , D1 , starts to conduct. vGS.H is removed
before iCr comes back to zero in order to turn off QH at zero voltage switching (ZVS). At the same time,
the body diode of QH conducts. This operation mode ends when iCr becomes zero.
 Electronics 2019, 8, 1303 5 of 12
Electronics 2019, 8, x FOR PEER REVIEW 5 of 12

Mode 1 2 3 4 5 6

vGS
vGS.H vGS.L
0

vQH vQL
vQL vQH
0

iCr 0

0
vCr

iD1
iD

iD2
0
0 T1 T2 T3 T4 T5 Ts
Electronics 2019, 8, x FOR PEER REVIEW 6 of 12
Figure 4. 4.Theoretical
Figure Theoreticalwaveforms
waveformswhen
whenB1Bis the
1 is theleast
leastcharged
chargedcell.
cell.

Mode 1 (0 ≤ t < T1) (Figure 5(a)): The gating signal for QH, vGS.H, is applied to turn on QH, achieving
zero current switching (ZCS) turn-on. Lkg and Cr start resonating, and the current of Cr, iCr,
sinusoidally changes. On the transformer secondary side, the resonant current flows through the
activated selection switch of S1 and the high-side diode corresponding to B1, D2. This operation mode
lasts until iCr becomes zero.
Mode 2 (T1 ≤ t < T2) (Figure 5(b)): QH and QL are still on and off, respectively. The polarity of iCr
is reversed, while the low-side diode corresponding to B1, D1, starts to conduct. vGS.H is removed
before iCr comes back to zero in order to turn off QH at zero voltage switching (ZVS). At the same time,
the body diode of QH conducts. This operation mode ends when iCr becomes zero.
Mode 3 (T2 ≤ t < T3) (not shown): This mode is unique to the DCM operation. No currents flow
in this mode, except for the smoothing capacitors.
Mode 4 (T3 ≤ t < T4) (Figure 5(c)): The gating signal for QL, vGS.L is applied to turn on QL at ZCS.
(a) (b)
Lkg and Cr start resonating again. D1 on the secondary side conducts. This operation mode ends when
iCr becomes zero.
Mode 5 (T4 ≤ t < T5) (Figure 5(d)): QH and QL are still off and on, respectively. The polarity of iCr
is opposite to that in Mode 4. The current on the secondary side flows through D2. vGS.L is removed
before iCr comes back to zero so as to turn off QL at ZVS. As iCr becomes zero, the operation moves to
Mode 6.
Mode 6 (T5 ≤ t < Ts) (not shown): This mode is identical to Mode 3, and no currents flow in the
circuit.
In summary, the resonant current flows through the activated selection switch (S1) and diodes
connected to the least charged cell. The AC current is rectified by the diodes in the voltage multiplier,
and a DC equalization current is supplied to the least charged cell only.

(c) (d)

Figure 5. Current flow paths: (a) Mode 1; (b) Mode 2; (c) Mode 4; (d) Mode 5.
Figure 5. Current flow paths: (a) Mode 1; (b) Mode 2; (c) Mode 4; (d) Mode 5.

Mode 3 (T2 ≤ t < T3 ) (not shown): This mode is unique to the DCM operation. No currents flow
3.2. Operation Boundary and Equalization Current
in this mode, except for the smoothing capacitors.
As can be seen in Figure 4, half the switching period (0.5Ts) must contain a full resonant period
Tr. Hence, the following operation boundary needs to be fulfilled:
2 ≤ , (1)
where fs is the switching frequency and fr is the resonant frequency.
Electronics 2019, 8, 1303 6 of 12

Mode 4 (T3 ≤ t < T4 ) (Figure 5c): The gating signal for QL , vGS.L is applied to turn on QL at ZCS.
Lkg and Cr start resonating again. D1 on the secondary side conducts. This operation mode ends when
iCr becomes zero.
Mode 5 (T4 ≤ t < T5 ) (Figure 5d): QH and QL are still off and on, respectively. The polarity of iCr is
opposite to that in Mode 4. The current on the secondary side flows through D2 . vGS.L is removed
before iCr comes back to zero so as to turn off QL at ZVS. As iCr becomes zero, the operation moves to
Mode 6.
Mode 6 (T5 ≤ t < Ts ) (not shown): This mode is identical to Mode 3, and no currents flow in
the circuit.
In summary, the resonant current flows through the activated selection switch (S1 ) and diodes
connected to the least charged cell. The AC current is rectified by the diodes in the voltage multiplier,
and a DC equalization current is supplied to the least charged cell only.

3.2. Operation Boundary and Equalization Current

As can be seen in Figure 4, half the switching period (0.5Ts ) must contain a full resonant period Tr .
Hence, the following operation boundary needs to be fulfilled:

2 fS ≤ fr , (1)

where fs is the switching frequency and fr is the resonant frequency.

Since the resonant inverter in the proposed equalizer is identical to that in the conventional
pack-to-cell equalizer [19] (see Figure 1), the equalization current supplied to the least charged cell can
be expressed in the identical form, as:
2Nωs Vin
Ieq ≈ , (2)
πZ0 ωr
where ωs and ωr are the angular switching and resonant frequencies, respectively, Z0 is the characteristic
impedance of the resonant tank:
s
Lkg N2 q
Z0 = , ωr = ω20 − γ2 , (3)
Cr

where ω0 is the characteristic angular frequency, and γ is the damping factor given by:

N R
ω0 = q , γ= , (4)
Lkg Cr 2Lkg

where R is the sum of resistive components in the resonant current path.

The equalization current Ieq is independent on cell voltage, as Equation (2) does not contain the
cell voltage. By properly designing the resonant tank parameters, currents in the circuit can be limited
within desired levels even without feedback control.

3.3. Equalization Algorithm

The equalization algorithm for the proposed equalizer is shown in the form of the flow chart in
Figure 6. At the beginning, all the selection switches are off. Cell voltages are measured, and open-circuit
voltages VOC are estimated by compensating a voltage drop across the impedance of cells. Since the
equalization current Ieq supplied from the equalizer is known and constant (see Equation (2)), the voltage
drop across the internal impedance of the selected cell can be determined. The open-circuit voltage
of the selected cell, VOC.i , can be estimated by compensating the voltage drop across the internal
impedance Zint , as:
VOC.i = Vi − Ieq Zint , (5)
repeated until all cell voltages are balanced, and Vmax – Vmin will be within Vth.
A relative state of charge (SOC) compensated by the equalizer in a single cycle of the flow chart
is expressed as:
(
∆&' = ,
3600 ×
Electronics 2019, 8, 1303 (6)12
7 of

where C is the cell capacity in Ah. For the experimental verification test using a prototype with Ieq ≈
0.75 A V
where i isLIB
for thecells
terminal
with voltage
3400 mAhof the
(seeselected cell BXi (i
Section 4.3), was= 1determined
. . . 4). To compensate thethat
to be 180 s so voltage
∆SOCdrop
was
Iabout
Z , Z
eq int 1%.
int needs to be measured in advance.

Figure 6.
Figure 6. Equalization
Equalization algorithm.
algorithm.

The most and least charged cells with the highest and lowest VOC , Vmax and Vmin , are determined.
If the difference between Vmax and Vmin is less than the threshold voltage Vth , all selection switches
remain off. If Vmax − Vmin is greater than Vth , the selection switch corresponding to Vmin is turned on.
Finally, QH and QL are driven to perform voltage equalization for X seconds. This sequence is repeated
until all cell voltages are balanced, and Vmax − Vmin will be within Vth .
A relative state of charge (SOC) compensated by the equalizer in a single cycle of the flow chart is
expressed as:
Ieq X
∆SOC = , (6)
3600 × C
where C is the cell capacity in Ah. For the experimental verification test using a prototype with
Ieq ≈ 0.75 A for LIB cells with 3400 mAh (see Section 4.3), X was determined to be 180 s so that ∆SOC
was about 1%.

4. Experimental Results

4.1. Prototype
A prototype for twelve cells connected in series was built, as shown in Figure 7. Circuit elements
used for the prototype are listed in Table 1. The resonant frequency fr was approximately 320 kHz,
and the prototype was operated at fs = 120 kHz to fulfill (1).

Table 1. Components list.

Component Value
QH , QL N-Ch MOSFET, FDD390N15A, Ron = 40 mΩ
CH , CL Ceramic Capacitor, GRM31CB31H106KA12L 10 µF
Cr Film Capacitor, F161SP474M063V, 0.47 µF
Transformer N1 :N2 = 15:3, Lkg = 13.8 µH, Lmg = 100 µH
S1 –S12 N-Ch MOSFET, IRF7341PBF, Ron = 50 mΩ
Co1 –Co12 Ceramic Capacitor, JMK325ABJ277MM-P, 220 µF
D1 –D24 Schottky Diode, CRS04 (T5L, TEMQ), Vf = 0.49 V
 4.1. Prototype
A prototype for twelve cells connected in series was built, as shown in Figure 7. Circuit elements
Figure 7. Prototype of proposed equalizer for twelve cells.
usedElectronics
for the2019,
prototype
8, 1303 are listed in Table 1. The resonant frequency fr was approximately 8320
of 12kHz,
and the prototype was operated at fs = 120 kHz to fulfill (1).
Table 1. Components list.

Component Value
QH, QL N-Ch MOSFET, FDD390N15A, Ron = 40 mΩ
CH , CL Ceramic Capacitor, GRM31CB31H106KA12L 10 µF
Cr Film Capacitor, F161SP474M063V, 0.47 µF
Transformer N1:N2 = 15:3, Lkg = 13.8 µH, Lmg = 100 µH
S1–S12 N-Ch MOSFET, IRF7341PBF, Ron = 50 mΩ
Co1–Co12 Ceramic Capacitor, JMK325ABJ277MM-P, 220 µF
D1–D24 Schottky Diode, CRS04 (T5L, TEMQ), Vf = 0.49 V

4.2. Measured Waveforms and Characteristics of Equalizer

Figure 7. 7.Prototype
Figure Prototypeof
ofproposed equalizerfor
proposed equalizer fortwelve
twelve cells.
cells.
Characteristics of the prototype alone were measured by breaking the node A designated in
4.2. Measured Waveforms and Characteristics of Equalizer
Table 1. Components list.
Figure 3. The equalizer was powered by an external power supply with Vin = 48 V. All cells were
Characteristics of the prototype alone were measured by breaking the node A designated in
removed, and a variable resistor was connected in parallel
Component Value with Co1 to emulate the current flow path
Figure 3. The equalizer was powered by an external power supply with Vin = 48 V. All cells were
QH, QLresistor wasN-Ch
in Figure 5.removed, and a variable MOSFET,
connected FDD390N15A,
in parallel Ron = 40the
with Co1 to emulate mΩ current flow path in
C H , CL Ceramic Capacitor, GRM31CB31H106KA12L
The measured key operation waveforms are shown in Figure 8. TheseµFwaveforms agreed well
Figure 5. 10
The measured C key Film Capacitor,
r operation waveforms F161SP474M063V,
are shown 0.47
in Figure 8. These µF
waveforms agreed well
with the theoretical ones in Figure 4, verifying the operation of the prototype.
Transformer
with the theoretical N1:N2 = 15:3,
ones in Figure 4, verifying Lkg = 13.8ofµH,
the operation mg = 100 µH
the Lprototype.
S1–S12 N-Ch MOSFET, IRF7341PBF, Ron = 50 mΩ
Co1–Co12 60Ceramic Capacitor, JMK325ABJ277MM-P, 220 µF
D1–D24 40Schottky Diode, CRS04 (T5L, TEMQ), Vf = 0.49 V
vQL [V]

20
4.2. Measured Waveforms and Characteristics of Equalizer
0
Characteristics of the prototype alone were measured by breaking the node A designated in
6.0
Figure 3. The equalizer was powered
3.0 by an external power supply with Vin = 48 V. All cells were
iCr [A]

removed, and a variable resistor was connected in parallel with Co1 to emulate the current flow path
0.0
in Figure 5.
-3.0
The measured key operation waveforms are shown in Figure 8. These waveforms agreed well
-6.0
with the theoretical ones in Figure 4, verifying the operation of the prototype.
Time [2 µs/div]
Figure608. 8.
Figure Measured keyoperation
Measured key operation waveforms.
waveforms.
vQL [V]

Measured output equalization 40 current I characteristics and power conversion efficiencies are
eq
shown in Figure 9—VCo1 in Figure 20 9 corresponds to the voltage of Co1 . Ieq slightly declined with as
VCo1 increased but was nearly constant,
0 demonstrating the constant current characteristic in DCM.
6.0
The efficiency was lower than 60%, and diode forward voltage drops were considered to be the dominant
3.0portion of the output voltage. The measured efficiency characteristic
loss factor as it took a significant
iCr [A]

was somewhat inferior to that of 0.0conventional equalizers (e.g., 80% [31,35]). Nevertheless, the inferior
-3.0
efficiency performance would be acceptable in most applications because processed power in the
equalizer is one-hundredth to -6.0one-thousandth that of a main converter [36,37]. Therefore, the loss in
Time [2 µs/div]
the equalizer would be negligibly small from the system viewpoint.
Figure 8. Measured key operation waveforms.
the equalizer would
efficiency belower
was negligibly small
than 60%, fromforward
and diode the system viewpoint.
voltage drops were considered to be the dominant
loss factor as it took a significant portion of the output voltage. The measured efficiency characteristic
was somewhat inferior to that of conventional equalizers (e.g., 80% [31,35]). Nevertheless, the inferior
70

Power [W] Efficiency [%]

efficiency performance would be acceptable in most applications because processed power in the
equalizer is one-hundredth60to one-thousandth that of a main converter [36,37]. Therefore, the9 loss
Electronics 2019, 8, 1303 of 12
in
50
the equalizer would be negligibly small from the system viewpoint.
40
30 70

Power [W] Efficiency [%]

4.0 60
3.0 50
40
2.0 30
4.0
1.0
1.0 3.0
Ieq [A] 0.9 2.0
0.8
0.7 1.0
1.0
0.6 0.9
Ieq [A]
0.5 0.8
2.00.7 2.5 3.0 3.5 4.0 4.5 5.0
0.6 VCo1 [V]
0.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0
Figure 9. Measured output
VCo1 [V]characteristics.

Figure 9. Measured
Figure output
9. Measured characteristics.
output characteristics.
4.3. Equalization Test
4.3.4.3.
Equalization Test
Equalization Test
An equalization test was performed for series-connected LIB cells, each with a capacity of 3400
AnAnequalization
equalization test
testwas performed
wasSOC,
performed for
for series-connected
series-connected LIBcells,
LIB cells,each
eachwithwith a capacity
a capacity of
of 3400
mAh. Individual
3400 mAh.
cell voltages,
Individual cell
or
voltages, or
werewere
SOC,
intentionally
intentionally
imbalanced.
imbalanced. The
The experimental
experimental setup
setup for
for
mAh. Individual cell voltages, or SOC, were intentionally imbalanced. The experimental setup for
the equalization
thethe test istest
equalization shown
is shownin Figure
in in
Figure 10.
10.Individual
Individual cellvoltages
cell voltageswerewere measured
measured using using differential
differential
equalization test is shown Figure 10. Individual cell voltages were measured using differential
amplifies, and a TMS320F28335
amplifies, and
amplifies, a TMS320F28335
and a TMS320F28335 control
controlcard
card
control was
was
card used
used
was tototo
used generate
generate gating
gating
generate gating signals
signals
signalsand toand
and to perform
perform
to performthethe the
equalization
equalization algorithm
algorithm
equalization in
in Figure
algorithm Figure 6.
6. The
in Figure The equalization
equalization
6. The equalization was
was carried
wascarried out with
outwith
carried out V
with = 20 mV.
=th20=mV.
thVthV 20 mV.

Figure 10. Experimental setup of equalization test for twelve LIB cells.

The resultant equalization profiles are shown in Figure 11. B1 and B2, the least charged cells at
FigureFigure
10. Experimental setup
10. Experimental setupofof equalization
equalization testtest
for for twelve
twelve LIB cells.
LIB cells.
the beginning of the test, received an equalization current, and their voltages of V1 and V2 increased.
AtThe
the same time,equalization
resultant other cells supplied
profiles the
are input
shown current for the
in Figure 11. equalizer,
B1 and B2and, thetheir
leastvoltages
chargeddecreased.
cells at
Thethe
resultant
During equalization profiles are shown in Figure 11. B 1 and B
beginning of the test, received an equalization current, and their voltages of V 1 andand
the course of the equalization, cells became the least charged cell 2, the least
alternately chargedancells at
received
V 2 increased.
the beginning of the
Atequalization
the same test,
time, received
current
other based onan
theequalization
cells suppliedequalization current,
algorithm.
the input current for the and
The their and
voltage
equalizer, voltages
imbalance of V1 and
gradually
their voltages V2 increased.
vanished
decreased.
At the same time,
During the other
coursecells
of thesupplied thecells
equalization, input current
became for the
the least equalizer,
charged and their
cell alternately andvoltages decreased.
received an
equalization current based on the equalization algorithm. The voltage imbalance gradually
During the course of the equalization, cells became the least charged cell alternately and received an vanished
and decreased
equalization down to
current based onapproximately 20 mV.
the equalization The standard
algorithm. Thedeviation
voltageof cell voltages
imbalance at the endvanished
gradually
of the equalization test was as low as 10 mV, demonstrating the equalization performance of the
proposed equalizer.
Electronics 2019, 8, x FOR PEER REVIEW 10 of 12

and decreased down to approximately 20 mV. The standard deviation of cell voltages at the end of
the equalization
Electronics 2019, 8, 1303test
was as low as 10 mV, demonstrating the equalization performance 10 of ofthe
12
proposed equalizer.

Figure 11.
Figure 11. Resultant
Resultant equalization
equalization profiles.
profiles.

5.
5. Conclusions
Conclusions
The
The cell
cell voltage
voltage equalizer
equalizer using
using aa selective
selective voltage
voltage multiplier
multiplier for
for series-connected
series-connected LIB
LIB cells
cells has
has
been
been proposed
proposed in in this
this paper.
paper. The
The proposed
proposed equalizer
equalizer can
can be
be derived
derived byby embedding
embedding selection
selection switches
switches
into
into the
theconventional
conventional voltage multiplier-based
voltage cell voltage
multiplier-based cell equalizer. In comparison
voltage equalizer. with conventional
In comparison with
cell
conventional cell equalizers using selection switches, the proposed topology can reduce of
equalizers using selection switches, the proposed topology can reduce the number theselection
number
switches by embedding
of selection switches byselection
embedding switched intoswitched
selection the voltage multiplier-based
into equalizer, achieving
the voltage multiplier-based the
equalizer,
simplified circuit and reduced cost.
achieving the simplified circuit and reduced cost.
The
The equalization
equalization testtest using
using the
the prototype
prototype was was performed
performed forfor twelve
twelve LIBs
LIBs connected
connected in in series.
series.
The
The voltage
voltage imbalance
imbalance decreased
decreased toto approximately
approximately 20 20 mV,
mV,and
and the
the standard
standard deviation
deviationof
of cell
cell voltages
voltages
at
at the
the end
end of
ofthe
theequalization
equalizationtesttestwas
wasasaslow
lowasas1010mV,
mV,demonstrating
demonstrating thethe
equalization performance
equalization performance of
the proposed
of the proposed cellcell
equalizer.
equalizer.
Author Contributions:
Author Contributions: Conceptualization,
Author Contributions:M.U.;Conceptualization,
methodology, M.U.; M.U.; methodology,
simulation M.U.;
analysis, T.U.simulation
and K.Y.;
validation, T.U.;
analysis, T.U. andwriting—original
K.Y.; validation,draft
T.U.;preparation, M.U.; draft
writing—original writing—review
preparation,and editing,
M.U.; M.U.; supervision,
writing—review M.U.
and editing,
M.U.; supervision,
Funding: M.U.received no external funding.
This research
Conflicts
Funding:of Theresearch
Interest:This
Funding: authors received
declare no
noconflict
externaloffunding.
interest.

Conflicts of Interest: Conflicts of Interest: The authors declare no conflict of interest.

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