EECS140 ANALOG CIRCUIT DESIGN INTRODUCTION EECS140 ANALOG CIRCUIT DESIGN INTRODUCTION

I-1
University of California EECS 140
Berkeley
ANALOG INTEGRATED CIRCUITS
College of Engineering
Department of Electrical Engineering
and Computer Science
Robert W. Brodersen, 2-1779, 402 Cory Hall, rb@eecs.berkeley.edu
This course will focus on the design of MOS analog integrated circuits with extensive use of Spice for the simulations.
In addition, some applications of analog integrated circuits will be covered which will include RF amplification and dis-
Robert W. Brodersen crete and continuous time filtering. Though the focus will be on MOS implementations, comparison with bipolar circuits
EECS140 will be given.

Analog Circuit Design Required Text

Analysis and Design of Analog Integrated Circuits, 4th Edition, P.R. Gray, P. Hurst, S. Lewis and R.G. Meyer, John Wiley
and Sons, 2001

Supplemental Texts
B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.
Thomas Lee, The Design of CMOS Radio Frequency Integrated Circuits, Cambridge University Press, 1998
The SPICE Book, Andre Vladimirescu, John Wiley and Sons, 1994

Prerequisites
EECS 105: Microelectronic Devices and Circuits

ROBERT W. BRODERSEN LECTURE 1 ROBERT W. BRODERSEN LECTURE 1

EECS140 ANALOG CIRCUIT DESIGN INTRODUCTION EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

IC Design Course Structure at Berkeley I-2

EE40 University of California
Berkeley
College of Engineering
Department of Electrical Engineering
EE105
and Computer Science

Robert W. Brodersen
EECS140

EE140 EE142 EE141

Analog Circuit Design
Linear/Analog Non-Linear Digital

Linear Design
Lectures
on
Sensors, Interface Digital
MOS DEVICE MODELS
Transducers Circuits Processing

Amplifiers, Filters, A/D & D/A’s

ROBERT W. BRODERSEN LECTURE 1 ROBERT W. BRODERSEN LECTURE 2

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

M-1 2-Port Equivalent Circuit M-2

RL → ∞
Assumed Knowledge (Voltage in - Voltage out) νin
i in io u t R i n = -----
ii n iout → 0
+
a) KCL, KVL - Kirchoff Laws Rs + R out νout
+ νin +- νout R out = -------
- i out
Vs
R in aν ⋅ ν i n RL
R S = νi n = 0

b) Voltage, Current Dividers - - νout

A ν = -------
νin RL → ∞
c) Thevenin, Norton Equivalents
i in i out
d) 2-Port Equivalents + + + +
R out1 R out2
+- νin1 +- νout1 ν in2 + νout
Vs -
e) Phasors, Frequency Response Rin1 aν 1 ⋅ ν i n 1 Rin2 a ν2 ⋅ ν in2
- - - -

ν o u t = a ν 2 ⋅ ν i n 2 = a ν 2 ⋅ ν o u t 1 = aν 2 ⋅  aν 1 ⋅ ν i n 1 ⋅  ------------------------
R in2  
  R out1 + R in2 
ROBERT W. BRODERSEN LECTURE 2 ROBERT W. BRODERSEN LECTURE 2

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

M-3 M-4
MOS Large Signal Equations MOS Large Signal Equations (Cont.)
Cutoff :
D
n-channel
I DS V GS < V T

V DSAT
G B Linear :
VGS V GS > V T
I DS
NMOS
Saturation S V D S < V D S A T = VG S – V T

--- ⋅  V G S – V T – -------  ⋅ V D S
V DS
G I D S = k' ⋅ W
L  2 
Linear
Cutoff
S D
L
VDS Saturated :
n
p
n V GS > V T
V D S > V D S A T = VG S – V T

ID S = k'
--- ⋅ W
--- ⋅ ( V G S – V T ) 2 ( 1 + λ ⋅ V D S )
B
2 L

ROBERT W. BRODERSEN LECTURE 2 ROBERT W. BRODERSEN LECTURE 2

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

MOS Large Signal Equations (Cont.) M-5 MOS Large Signal Equations (Cont.) M-6

1
--- 1
--

V T = V T o + γ ⋅ [ ( 2 ⋅ φ f + V S B ) – ( 2 ⋅ φ f) ]
2 2

Body Effect :
(VSB > 0 )
G
1 VT
V T o ≡ Threshold Voltage @ V S B = 0
--
V T o + γ ⋅ VS B
2
S ++++++++ D
φ f ≡ Fermi Potential ≈ 0.3 µ n n

γ ≡ Body Effect Factor

λ ≡ Short Channel Effect E = V DS/L
1 ⋅
γ = ------ 2 ⋅ q ⋅ ε ⋅ NA
C ox
W ≡ Width of Device VTo

L ≡ Length νε 0

VBS
k' = µ ⋅ C ox
Oxide Capacitance E
mobility

ROBERT W. BRODERSEN LECTURE 2 ROBERT W. BRODERSEN LECTURE 2

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

MOS Large Signal Equations (Cont.) M-7 MOS Large Signal Equations (Cont.) M-8

Short Channel Effect (λ): I (DA ) = k' W ⋅ ( V – V )2

--- ⋅ -------- GS T
2 LEFF

Modeled as
S G D
k' W
I (DB) = --- ⋅ ----- ⋅ ( V G S – V T )2 ⋅ ( 1 + λ ⋅ V D S)
2 L
XJ = Junction Depth ∂I (DB)
= λ ⋅ I DS
XD ∂V DS

∂ID
( A)
L D = Lateral Diffusion ~ 0.75 X J k' W dL
= – --- ⋅ -------- ⋅ ( V G S – VT ) ⋅ E F F
2
L drawn
∂ VD S 2 L 2E F F d VD S
L = L drawn – 2 ⋅ L D
∂I (DA ) ID ⋅ dX D = λ ⋅ I
LE F F = L – X D = --------
∂V DS L EFF dV DS
D

X D = f ( VD S )

ROBERT W. BRODERSEN LECTURE 2 ROBERT W. BRODERSEN LECTURE 3

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

M-9
MOS Large Signal Equations (Cont.) MOS Large Signal Equations (Cont.)

λ = -------- ⋅  D  ≈ -- ⋅  D 
1 dX 1 dX G
L EFF dV DS L dV D S

Weak function of VDS λI D S

I DS
W
1 S D
⋅ ε ⋅ ( V D S – VD S A T )
--

XD ≈ 2
2
------------------------------------------- Ideal Longer Channel L
q ⋅ NA (Increasing L)

Fixed → ε = Dielectric constant of silicon

V DS
W/L is the parameter of interest
N A = Substrate doping
C G ∝ W ⋅ L ⋅ COX
1 1

2⋅ε
-- --

= - ⋅  -------------  ⋅  ------------------------ 
dX D 1 2
1 2

d VD S 2  q ⋅ N A  V D S – V D S A T 

ROBERT W. BRODERSEN LECTURE 3 ROBERT W. BRODERSEN LECTURE 3

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

M-10
M-11 MOS Small Signal Model (Cont.) M-12
MOS Small Signal Model (Low Frequency)

IDS In Saturation :
G D gm =
dID S W
= k' ⋅ --- ⋅ ( V G S – V T ) ⋅ ( 1 + λ ⋅ V D S )
+ gmν gs d VG S L
V GS ro -1-

g m ≈ k' ⋅ --- ⋅ ( V G S – V T ) = k' ⋅ ----- ⋅ V D S A T =  2 ⋅ k' ⋅ ----- ⋅ I D S

W W W 2

gmbs ν bs L L L
-
What is VDSAT ?
S B I D S = --- ⋅ W
k'
+
V SB
- ----- ⋅ ( V G S – V T ) 2 = k'
--- ⋅ W
----- ⋅ V D S A T
2
and from above,
2 L 2 L
G
+ W
ID S =
dID S
⋅ ν gs +
dID S
⋅ ν bs +
dI D S
⋅ νds g m = k' ⋅ ----- ⋅ V D S A T so,
d VG S d V BS dV DS L
S
-












2 ⋅ ID S  2
--

gm gmbs 1/ro V G S = VT + V D S A T V D S A T =  --------------------

k' ⋅ W ⁄ L

ROBERT W. BRODERSEN LECTURE 3 ROBERT W. BRODERSEN LECTURE 3

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

MOS Small Signal Model (Cont.) M-13 MOS Small Signal Model (Cont.) M-14

gmbs calculation : C ox

dI D S
gmbs = gmb = = –k' ⋅ W
----- ⋅ ( V G S – V T ) ⋅ ( 1 + λ ⋅ V D S ) ⋅ dV T 0.23 G
dV BS L d V BS
gmbs
------- = χ S D
dV T γ
= – ----------------------------------------- ≡ –χ
gm
dV BS 2 ⋅ ( 2 ⋅ φ f + V S B) 0.5 n n

0.1 C js
W
g mbs = k' ⋅ ----- ⋅ ( V G S – V T ) ⋅ ( 1 + λ ⋅ V D S ) ⋅ χ -5V V BS 0V
L Q c h a n n e lduetovgs ≈ C o x ⋅ ν g s













gm γ = 0.5
φf = 0.3 Q c h a n n e ld u e t o v b s ≈ C j s ⋅ ν b s
k’ = 90e-6
C js
g
-------
mbs
= χ γ λ = 0.01 χ = ------
χ = -----------------------------------------0.5 C ox
gm 2 ⋅ (2 ⋅ φ f + V S B ) V To=0.7

ROBERT W. BRODERSEN LECTURE 3 ROBERT W. BRODERSEN LECTURE 3

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

MOS Small Signal Model (Cont.) M-15 MOS Small Signal Model (Cont.) M-16

Comparison with Spice Level 1:

ro calculation :

--- =  g m d s = D S = d  k' VTO = V T o ∼ 0.5 → 1.0V

----- ⋅ ( V G S – V T ) 2 ⋅ ( 1 + λ ⋅ V D S ) 
1 dI
--- ⋅ W
ro  dV DS dV DS 2 L 

1 P H I = 2 ⋅ φ f ∼ 0.6
--- = k' W
--- ⋅ ----- ⋅ ( V G S – V T ) 2 ⋅ λ
ro 2 L
G A M M A = γ ∼ 0.05 → 0.5
1
--- = λ ⋅ I D S
ro L A M B D A = λ ∼ 0.01 → 0.1
A
1 K P = k' = µ ⋅ C o x ∼ n m o s → 50 – 100µ -----2
r 0 = ------------- V
λ ⋅ ID S pmos ≈ 1 -- nmos
3

ROBERT W. BRODERSEN LECTURE 3 ROBERT W. BRODERSEN LECTURE 3

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE

MOS Small Signal Model (Cont.)

Summary:
2 ⋅ I DS
1
--
University of California
g m ≈  2 ⋅ k' ⋅ ----- ⋅ ID S = k' ⋅ ----- ⋅ V D S A T = -------------
W 2
W
Berkeley
L L VD S A T
gmbs = χ ⋅ gm College of Engineering
Department of Electrical Engineering
γ and Computer Science
χ = -----------------------------------------0.5 V D S A T = VG S – V T
2 ⋅ ( 2 ⋅ φ f + V S B) Robert W. Brodersen
1

2 ⋅ I DS  2
--
EECS140
= V T +  --------------------
1
r 0 = ------------- VGS
λ ⋅ ID S k' ⋅ W ⁄ L Analog Circuit Design
I DS VGS – VT V DSAT
-----
gm
= ------------------
2
= ----------
2 ID S = k'
--- ⋅ W
----- ⋅ ( V G S – V T )2
1
2 L Lectures
2 ⋅ ID S 
--

=  --------------------
2 1 1
VDSAT
 k' ⋅ W ⁄ L
---
VT = V T o + γ ⋅ [ ( 2 ⋅ φ f + VS B ) – ( 2 ⋅ φ f ) ]
2
---
2
on
SPICE

ROBERT W. BRODERSEN LECTURE 4 ROBERT W. BRODERSEN LECTURE 4

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE

SP-1 SP-2
Spice Transistor Model : SPICE

M1 1 2 3 4 nch L=1µ W=10µ Initial Operationg Point

DC currents and Voltages
AD=( ) AS=( ) PD=( ) PS=( ) NRD=( )
Linearize New Operating
parasitic resistors Around OP Point Point
No Analysis Types :
G area of drain DC op point .op
Solve Eqn. DC Converge? DC sweeps
1 Yes AC & Transient
S W D Increment Time
2 4
L
3 No End of Yes
Time Interval STOP

ROBERT W. BRODERSEN LECTURE 4 ROBERT W. BRODERSEN LECTURE 4

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE

4 VA SP-3 SP-4

+-
R4 I4 G i = 1/Ri G 1+G 4 -G1 0 -G 4 1 0 V1 0
2 -G 1 G1 +G 2+G 3 -G 3 0 0 0 V2 0
1 3 0 -G3 -G 3 0 0 -1 V3 0
+- V B R1 R2 R3 =
I1 -G 4 0 0 -G 4 0 1 V4 0
1 0 0 0 0 0 I1 VB
Node 1 : ( G 1 + G 4 ) ⋅ V1 – G1 ⋅ V 2 – G 4 ⋅ V 4 + I1 = 0 0 0 -1 1 0 0 I4 VA

Node 2 : – G 1 ⋅ V 1 + ( G 1 + G 2 + G 3 ) ⋅ V2 – G 3 ⋅ V3 = 0 Current src

Node 3 : – G 3 ⋅ V2 + G 3 ⋅ V3 – I4 = 0 Total # of EQNS N=n + n v + nl
G F V C
Node 4 : –G4 ⋅ V 1 – G 4 ⋅ V 4 + I4 = 0 = n = # of circuit nodes
nv= # of independent voltage srcs
V1 = VB B R I E
nl= # of inductors
–V 3 –V 4 = VA
Votlage src
ROBERT W. BRODERSEN LECTURE 4 ROBERT W. BRODERSEN LECTURE 4

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE

SP-5 SP-6
Matrix Solution (1)
Then eliminate a32
(2 ) (1)
e1 = e1 x x x
A x = b (2 ) (1) Upper triangular matrix
e2 = e2 0 x x
we need (1)
a 32 ⋅ e (1 ) can be solved
e (32 ) = e 3 – ------
(1)
2
0 0 x
Solve by Gaussian Elimination a (221 )

(0) denotes iteration step (2) (2) (2)

a 1 1 a 1 2 a 13 x 1 b (10 )
0 a 2 2 a 23 x 2 =
(2) (2) (1 )
e (10) a (101) a (120 ) a (130) x 1 b (10 ) b2
(2)
e (20) a (201) a (220 ) a (230) x 2 = b2
(0) 0 0 a 33 x 3 b (32 )
( 0)
e 3 a (301) a (320 ) a (330) x 3 b (30 ) b (32 )
x 3 = ------
a (323)
Eliminate a 21,a 31 Solution
( b (21 ) – a (231 ) ⋅ x 3 )
x x x x 2 = ---------------------------------
a (0 )
a (0 )
a (221 )
e (11 ) = e (10) e (21) = e (20) – ------ ⋅ e (10 )
21
e (31) = e (30) – ------31
⋅ e (10 ) 0 x x
( b 1 – a 1 3 ⋅ x 3 – a 12 ⋅ x 2 )
(0 ) (0 ) (0 ) (0 ) ( 0)
a 11 a 11
0 x x x 1 = ------------------------------------------------------
a (101)

ROBERT W. BRODERSEN LECTURE 4 ROBERT W. BRODERSEN LECTURE 4

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE

SP-7 SP-8
Accuracy
To control accuracy
Can’t divide by 0 or small numbers, so pivoting is used
to reorder eqn’s (Basically renumbering nodes). Puts .options PIVTOL = <values> (1018)
maximum values on diagonal.
R 1 =1Ω This sets the allowable range of conductance values.
1 –1 V1 = 1
– 1 1.0001 V2 0 *ERROR* : Maximum entry ......at
1 1
-- – --------- = G 1 + G 2 STEP ....... is less than PIVTOL
1 10 k
1A R 2=10kΩ
If the computer only has 4 -Probably means you have an incorrect element
digits of precision then we get, or floating node

Actually, V1 – V2 = 1
1 –1 V 1 = 1
– V1 + V 2 = 0
V 1 = 10 , 001V –1 1 V 2 0
V 1, V 2 = ∞
V 2 = 10 , 000V

ROBERT W. BRODERSEN LECTURE 4 ROBERT W. BRODERSEN LECTURE 4

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE

SP-9 SP-10
Solution of the DC equations with non-linear models Newton-Raphson Iteration :

VD

ID = IS ⋅ e
---------
V TH
– 1
- Make guess of next operation point in iteration
 

IG = G ⋅ V
Start at initial guess and linearize diode eqn.
Need to find
+ IA this point +
IG
VD
IA G V D(0) ID0
IA G G D0
IG - ID ID,G
ID -

ROBERT W. BRODERSEN LECTURE 4 ROBERT W. BRODERSEN LECTURE 4

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE

SP-11
SP-12
Convergence

Keep iterating until all voltages and currents are within a

Current value Solution finds this point a tolerance value.
I D0 V (ni) = node voltage n at iteration i
Slope of GD0
ε Vn = R E L ( V ) ⋅ m a x ( V (ni + 1 ) , V (ni) ) + A B S ( V)
ID
The convergence check is :
VD V (ni + 1) – V (ni) ≤ ε Vn

Solve for V D, R E L ( V ) ∼ 10 – 4 (Default 10 – 3 )

Linearize at this point A B S ( V ) ∼ 10 –6 (Default 50µV )
becomes VD (1)
Find new point ABS(V) should be at least two orders of magnitude below
required accuracy.
These values would give 1 part in 104 accuracy down to
100µV resolution
ROBERT W. BRODERSEN LECTURE 4 ROBERT W. BRODERSEN LECTURE 4

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

SP-13

Current convergence is broken into two types; MOS and NOT MOS
A B S M O S ∼ A B S O L U T E ( 10 –6 )
MOS
R E L M O S ∼ RELATIVE ( 0.5 )

ABSI ∼ A B S O L U T E ( 10 – 9)
NOTMOS
R E L I ∼ RELATIVE ( 0.01 )

ITL = # of steps in iteration (200)

When you get
*ERROR* no convergence in DC analysis and the last node voltages
Then it hasn’t converged in 200 times - something is probably
wrong with your netlist

ROBERT W. BRODERSEN LECTURE 2