PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev.

April’03 1 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 2

Topics
IIT Bombay

IIT Bombay
1.General Considerations in Layout Design

PCB DESIGN 2.Layout Design for Analog Circuits

3.Layout Design for Digital Circuits
4. Artwork Considerations

Dr. P. C. Pandey References

W.C. Bosshart, Printed Circuit Boards: Design and Technology, TMH,
pcpandey@ee.iitb.ac.in

pcpandey@ee.iitb.ac.in
EE Dept, IIT Bombay
1992
Revised Aug’07
C.F. Coombs : Printed Circuits Handbook , McGraw-Hill, 2001
R.S. Khandpur : Printed Circuit Boards : Design, Fabrication, and
Assembly, McGraw-Hill, 2005.
♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>

PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 3 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 4

• GENERAL CONSIDERATIONS 1.1 Parasitic Effects

IIT Bombay

IIT Bombay

IN LAYOUT DESIGN
R & L of conductor tracks
C between conductor tracks
Main issues
• Component interconnections • Effects of parasitics Resistance
• Physical accessibility of components • Power dissipation
Resistance of 35 µm thickness, 1 mm wide conductor = 5 mΩ/cm
Change in Cu resistance with temperature = 0.4% / °C
Subtopics
pcpandey@ee.iitb.ac.in

pcpandey@ee.iitb.ac.in

Current carrying capacity of 35 µm thickness Cu conductor (for 10 °C

1.1 Parasitic effects temperature rise):
1.2 Supply conductors Width (mm) 1 4 10
1.3 Component placement Ic (A) 2 4 11

♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>

PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 5 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 6

Capacitance 1.2 Supply Conductors

IIT Bombay

IIT Bombay

• Tracks opposite each other

- Run supply lines above each other Unstable supply & ground due to
- Don’t let signal line tracks overlap for any significant distance • Resistive voltage drop
• Tracks next to each other • Voltage drop caused by track L and high freq. current
- Increase the spacing between critical conductors • Current spikes during logic switching ⇒ local rise in ground potential
- Run ground between signal lines & fall in Vcc potential ⇒ possibility of false logic triggering.

Inductance Solutions
pcpandey@ee.iitb.ac.in

pcpandey@ee.iitb.ac.in

To be considered in • Conductor widths : W (ground) > W (supply) > W(signal)

• High frequency analog circuits • Ground plane
• Fast switching logic circuits • Track configuration for distributed C between Vcc & ground
• Analog & digital ground (&supply) connected at the most stable point

♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>
 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 7 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 8

1.3 Component Placement

IIT Bombay

IIT Bombay
2. LAYOUT DESIGN FOR ANALOG
• Minimize critical conductor lengths & overall conductor length CIRCUITS
• Component grouping according to connectivity
• Same direction & orientation for similar components • Supply and ground conductors
• Space around heat sinks • Signal conductors for reducing the inductive and capacitive
• Packing density coupling
• Uniform • Special considerations for
• Accessibility for • Power output stage circuits
pcpandey@ee.iitb.ac.in

pcpandey@ee.iitb.ac.in
• adjustments • component replacement • test points • High gain direct coupled circuits
• Separation of heat sensitive and heat producing components • HF oscillator /amplifier
• Mechanical fixing of heavy components • Low level signal circuits

♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>

PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 9 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 10

2.1 Ground & Supply Lines

IIT Bombay

IIT Bombay

2.2 HF Oscillator / Amplifier

• Separate GND (& Vcc) lines for analog & digital circuits
• Independent ground for reference voltage circuits • Decoupling capacitor between Vcc & GND → Capacitive load on o/p
• Connect different ground conductors at most stable • Reduce capacitive coupling between output & input lines
reference point • Vcc decoupling for large BW ckts. (even for LF operation)
• Separation between signal & GND to reduce capacitive loading
• Supply lines with sufficient
width and high capacitive
coupling to GND
pcpandey@ee.iitb.ac.in

pcpandey@ee.iitb.ac.in

(use decoupling capacitors)

• Supply line should first
connect to high current drain
ckt blocks
• Supply line independent for voltage references

♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>

PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 11 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 12

2.3 Circuits with High Power O/P Stage

IIT Bombay

IIT Bombay

2.4 High Gain DC Amplifier

Resistance due to track length & solder joints → modulation
Solder joints → thermocouple jn
of Vcc & GND and low freq. oscillations
Temp gradients → diff. noisy voltages
• Large decoupling capacitors
• Separate Vcc & GND for power & pre- amp stages
• Temp.gradients to be avoided
• Enclosure for stopping free movement of surrounding air
pcpandey@ee.iitb.ac.in

pcpandey@ee.iitb.ac.in

♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>
 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 13 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 14

High -Z circuits
IIT Bombay

IIT Bombay
2.5 Low Level Signal Circuits
If R » 1⁄ jw(Cxy+Cy)
then coupled Vy = Va × [Cxy/(Cy+Cxy)]
A) High impedance circuits - Capacitive coupling
• Increase separation between low level
B) Low impedance circuits - Inductive coupling
high Z line and high level line
(decrease Cxy)
• Put a ground line between the two
pcpandey@ee.iitb.ac.in

pcpandey@ee.iitb.ac.in
(guard line)
Example: Guard for signal leakage
from FET output to input

♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>

PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 15 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 16

Low – Z Circuits
IIT Bombay

IIT Bombay

• Voltage induced in ground loops due to external magnetic fields

3. LAYOUT DESIGN FOR DIGITAL
• Current caused in the low- Z circuit loop due to strong AC currents in CIRCUITS
nearby circuits
Vm= - (d/dt) ∫B dA Main problems
• Avoid ground loops • Ground & supply line noise
• Keep high current ac lines away from • Cross-talk between neighboring signal lines
pcpandey@ee.iitb.ac.in

pcpandey@ee.iitb.ac.in

low level,low Z circuit loops • Reflections : signal delays, double pulsing

• Keep circuit loop areas small

♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>

PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 17 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 18
IIT Bombay

IIT Bombay

3.1 Ground & Supply Line Noise Solution for ground & supply noise
Noise generated due to current spikes during logic level switching, • Decoupling C between Vcc & ground for every 2 to 3 IC’s :
drawn from Vcc and returned to ground ceramic, low L cap. of 10 nf for TTL & 0.5 nF for ECL & CMOS
•Stabilizes Vcc-GND (helps against internal spikes
• Internal spike: charging & discharging of transistor junction • Not much help for external spikes
capacitances in IC ( 20 mA, 5ns in TTL) • Low wave impedance between supply lines (20 ohms):
• External spike: charging & discharging of output load capacitance 5 to 10 mm wide lines opposite each other as power tracks
• Ground plane : large Cu area for ground
pcpandey@ee.iitb.ac.in

pcpandey@ee.iitb.ac.in

Ground potential increases, Vcc decreases: improper logic triggering. to stabilize it against external spikes
Problem more severe for synchronous circuits. • Closely knit grid of ground conductors
Severity of problem (increasing): CMOS, ECL, TTL. (will form ground loops, not to be used for analog circuits)
• Twist Vcc & GND line between PCBs

♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>
 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 19 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 20

3.2 Cross-talk 3.3 Reflections

IIT Bombay

IIT Bombay
• Occurs due to parallel running signal lines Caused by mismatch between the logic output impedance
(ECL: 10cm,TTL: 20 cm, CMOS: 50 cm) & the wave impedance of signal tracks.
• Problem more severe for logic signals flowing in opposite directions • Signal delay (low wave imp.) • Double pulses (high wave imp.)

TTL (Z: 100 - 150 Ω)

Solutions
0.5 mm signal line with GND plane, 1 mm without GND plane.
• Reduce long parallel paths
Signal lines between PCBs twisted with GND lines.
• Increase separation
pcpandey@ee.iitb.ac.in

pcpandey@ee.iitb.ac.in
betw. signal lines ECL (Z: 50 Ω)
• Decrease impedance 1 - 3 mm signal line with GND plane, or nearby gnd conductor.
betw. signal & ground lines
• Run a ground track CMOS (Z: 150 – 300 Ω)
between signal lines 0.5 mm signal line without GND plane. Gnd not close to signal lines.
♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>

PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 21 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 22

Summary of Layout Design Considerations 4. ARTWORK RULES

IIT Bombay

IIT Bombay

(for 1.6 mm thickness, double sided boards)

Logic Family: TTL ECL CMOS

Conductor orientation
Ω)
Signal–GND Zw (Ω 100 - 150 50 - 100 150 - 300 • Orientation for shortest interconnection length.
• Conductor tracks on opposite sides in x-direction & y-
Signal line width 0.5 with gnd 1 - 3 with gnd 0.5, no gnd direction to minimize via holes.
(mm) 1, no gnd • 45° or 30° / 60° orientation for turns.
Ω)
Vcc -GND Zw (Ω <5 < 10 < 20
pcpandey@ee.iitb.ac.in

pcpandey@ee.iitb.ac.in

Conductor Routing
Vcc line (mm) 5 2 to 3 2 • Begin and end at solder pads, join conductors for reducing
GND line (mm) Very broad Broad 5 interconnection length.
(plane /grid) (plane/grid) • Avoid interconnections with internal angle <60°.
• Distribute spacing between conductors .
♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>

PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 23 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 24
IIT Bombay

IIT Bombay

Solder Pads
Conductor × √
routing Hole dia
examples • Reduce the number of different sizes.
• 0.2 - 0.5 mm clearance for lead dia.

Solder pad
• Annular ring width
pcpandey@ee.iitb.ac.in

pcpandey@ee.iitb.ac.in

≥ 0.5 mm with PTH

≈ 3 × hole dia without PTH
• Uniformity of ring around the hole.
• Conductor width d > w > d/3.

♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>> ♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>
 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 25
IIT Bombay
pcpandey@ee.iitb.ac.in

♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>

 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 1

IIT Bombay
PCB DESIGN
Dr. P. C. Pandey
EE Dept, IIT Bombay

Revised Aug’07

pcpandey@ee.iitb.ac.in
♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>
 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 2

Topics

IIT Bombay
1.General Considerations in Layout Design
2.Layout Design for Analog Circuits
3.Layout Design for Digital Circuits
4. Artwork Considerations

References
W.C. Bosshart, Printed Circuit Boards: Design and Technology, TMH,
1992

C.F. Coombs : Printed Circuits Handbook , McGraw-Hill, 2001

R.S. Khandpur : Printed Circuit Boards : Design, Fabrication, and

pcpandey@ee.iitb.ac.in
Assembly, McGraw-Hill, 2005.
♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>
 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 3

• GENERAL CONSIDERATIONS

IIT Bombay
IN LAYOUT DESIGN
Main issues
• Component interconnections • Effects of parasitics
• Physical accessibility of components • Power dissipation

Subtopics
1.1 Parasitic effects
1.2 Supply conductors
1.3 Component placement

pcpandey@ee.iitb.ac.in
♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>
 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 4

1.1 Parasitic Effects

IIT Bombay
R & L of conductor tracks
C between conductor tracks

Resistance
Resistance of 35 µm thickness, 1 mm wide conductor = 5 mΩ/cm
Change in Cu resistance with temperature = 0.4% / °C
Current carrying capacity of 35 µm thickness Cu conductor (for 10 °C
temperature rise):
Width (mm) 1 4 10
Ic (A) 2 4 11

pcpandey@ee.iitb.ac.in
♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>
 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 5

Capacitance
• Tracks opposite each other

IIT Bombay
- Run supply lines above each other
- Don’t let signal line tracks overlap for any significant distance
• Tracks next to each other
- Increase the spacing between critical conductors
- Run ground between signal lines

Inductance
To be considered in
• High frequency analog circuits
• Fast switching logic circuits

pcpandey@ee.iitb.ac.in
♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>
 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 6

1.2 Supply Conductors

IIT Bombay
Unstable supply & ground due to
• Resistive voltage drop
• Voltage drop caused by track L and high freq. current
• Current spikes during logic switching ⇒ local rise in ground potential
& fall in Vcc potential ⇒ possibility of false logic triggering.

Solutions
• Conductor widths : W (ground) > W (supply) > W(signal)
• Ground plane
• Track configuration for distributed C between Vcc & ground

pcpandey@ee.iitb.ac.in
• Analog & digital ground (&supply) connected at the most stable point

♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>

 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 7

1.3 Component Placement

IIT Bombay
• Minimize critical conductor lengths & overall conductor length
• Component grouping according to connectivity
• Same direction & orientation for similar components
• Space around heat sinks
• Packing density
• Uniform
• Accessibility for
• adjustments • component replacement • test points
• Separation of heat sensitive and heat producing components
• Mechanical fixing of heavy components

pcpandey@ee.iitb.ac.in
♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>
 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 8

2. LAYOUT DESIGN FOR ANALOG

IIT Bombay
CIRCUITS
• Supply and ground conductors
• Signal conductors for reducing the inductive and capacitive
coupling
• Special considerations for
• Power output stage circuits
• High gain direct coupled circuits
• HF oscillator /amplifier
• Low level signal circuits

pcpandey@ee.iitb.ac.in
♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>
 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 9

2.1 Ground & Supply Lines

• Separate GND (& Vcc) lines for analog & digital circuits

IIT Bombay
• Independent ground for reference voltage circuits
• Connect different ground conductors at most stable
reference point
• Supply lines with sufficient
width and high capacitive
coupling to GND
(use decoupling capacitors)
• Supply line should first
connect to high current drain
ckt blocks

pcpandey@ee.iitb.ac.in
• Supply line independent for voltage references

♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>

 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 10

2.2 HF Oscillator / Amplifier

IIT Bombay
• Decoupling capacitor between Vcc & GND → Capacitive load on o/p
• Reduce capacitive coupling between output & input lines
• Vcc decoupling for large BW ckts. (even for LF operation)
• Separation between signal & GND to reduce capacitive loading

pcpandey@ee.iitb.ac.in
♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>
 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 11

2.3 Circuits with High Power O/P Stage

IIT Bombay
Resistance due to track length & solder joints → modulation
of Vcc & GND and low freq. oscillations
• Large decoupling capacitors
• Separate Vcc & GND for power & pre- amp stages

pcpandey@ee.iitb.ac.in
♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>
 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 12

2.4 High Gain DC Amplifier

IIT Bombay
Solder joints → thermocouple jn
Temp gradients → diff. noisy voltages

• Temp.gradients to be avoided
• Enclosure for stopping free movement of surrounding air

pcpandey@ee.iitb.ac.in
♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>
 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 13

2.5 Low Level Signal Circuits

IIT Bombay
A) High impedance circuits - Capacitive coupling
B) Low impedance circuits - Inductive coupling

pcpandey@ee.iitb.ac.in
♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>
 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 14

High -Z circuits

IIT Bombay
If R » 1⁄ jw(Cxy+Cy)
then coupled Vy = Va × [Cxy/(Cy+Cxy)]

• Increase separation between low level

high Z line and high level line
(decrease Cxy)
• Put a ground line between the two
(guard line)
Example: Guard for signal leakage
from FET output to input

pcpandey@ee.iitb.ac.in
♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>
 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 15

Low – Z Circuits
• Voltage induced in ground loops due to external magnetic fields

IIT Bombay
• Current caused in the low- Z circuit loop due to strong AC currents in
nearby circuits
Vm= - (d/dt) ∫B dA

• Avoid ground loops

• Keep high current ac lines away from
low level,low Z circuit loops
• Keep circuit loop areas small

pcpandey@ee.iitb.ac.in
♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>
 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 16

3. LAYOUT DESIGN FOR DIGITAL

IIT Bombay
CIRCUITS
Main problems
• Ground & supply line noise
• Cross-talk between neighboring signal lines
• Reflections : signal delays, double pulsing

pcpandey@ee.iitb.ac.in
♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>
 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 17

3.1 Ground & Supply Line Noise

IIT Bombay
Noise generated due to current spikes during logic level switching,
drawn from Vcc and returned to ground

• Internal spike: charging & discharging of transistor junction

capacitances in IC ( 20 mA, 5ns in TTL)
• External spike: charging & discharging of output load capacitance

Ground potential increases, Vcc decreases: improper logic triggering.

Problem more severe for synchronous circuits.
Severity of problem (increasing): CMOS, ECL, TTL.

pcpandey@ee.iitb.ac.in
♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>
 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 18

Solution for ground & supply noise

IIT Bombay
• Decoupling C between Vcc & ground for every 2 to 3 IC’s :
ceramic, low L cap. of 10 nf for TTL & 0.5 nF for ECL & CMOS
•Stabilizes Vcc-GND (helps against internal spikes
• Not much help for external spikes
• Low wave impedance between supply lines (20 ohms):
5 to 10 mm wide lines opposite each other as power tracks
• Ground plane : large Cu area for ground
to stabilize it against external spikes
• Closely knit grid of ground conductors
(will form ground loops, not to be used for analog circuits)
• Twist Vcc & GND line between PCBs

pcpandey@ee.iitb.ac.in
♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>
 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 19

3.2 Cross-talk

IIT Bombay
• Occurs due to parallel running signal lines
(ECL: 10cm,TTL: 20 cm, CMOS: 50 cm)
• Problem more severe for logic signals flowing in opposite directions

Solutions
• Reduce long parallel paths
• Increase separation
betw. signal lines
• Decrease impedance
betw. signal & ground lines
• Run a ground track

pcpandey@ee.iitb.ac.in
between signal lines

♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>

 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 20

3.3 Reflections

IIT Bombay
Caused by mismatch between the logic output impedance
& the wave impedance of signal tracks.
• Signal delay (low wave imp.) • Double pulses (high wave imp.)

TTL (Z: 100 - 150 Ω)

0.5 mm signal line with GND plane, 1 mm without GND plane.
Signal lines between PCBs twisted with GND lines.

ECL (Z: 50 Ω)
1 - 3 mm signal line with GND plane, or nearby gnd conductor.

CMOS (Z: 150 – 300 Ω)

pcpandey@ee.iitb.ac.in
0.5 mm signal line without GND plane. Gnd not close to signal lines.
♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>
 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 21

Summary of Layout Design Considerations

(for 1.6 mm thickness, double sided boards)

IIT Bombay
Logic Family: TTL ECL CMOS
Signal–GND Zw (Ω
Ω) 100 - 150 50 - 100 150 - 300

Signal line width 0.5 with gnd 1 - 3 with gnd 0.5, no gnd
(mm) 1, no gnd
Vcc -GND Zw (Ω
Ω) <5 < 10 < 20

Vcc line (mm) 5 2 to 3 2

GND line (mm) Very broad Broad 5
(plane /grid) (plane/grid)

pcpandey@ee.iitb.ac.in
♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>
 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 22

4. ARTWORK RULES

IIT Bombay
Conductor orientation
• Orientation for shortest interconnection length.
• Conductor tracks on opposite sides in x-direction & y-
direction to minimize via holes.
• 45° or 30° / 60° orientation for turns.

Conductor Routing
• Begin and end at solder pads, join conductors for reducing
interconnection length.
• Avoid interconnections with internal angle <60°.

pcpandey@ee.iitb.ac.in
• Distribute spacing between conductors .
♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>
 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 23

Conductor × √

IIT Bombay
routing
examples

pcpandey@ee.iitb.ac.in
♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>
 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 24

Solder Pads

IIT Bombay
Hole dia
• Reduce the number of different sizes.
• 0.2 - 0.5 mm clearance for lead dia.

Solder pad
• Annular ring width
≥ 0.5 mm with PTH
≈ 3 × hole dia without PTH
• Uniformity of ring around the hole.
• Conductor width d > w > d/3.

pcpandey@ee.iitb.ac.in
♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>
 PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 25

IIT Bombay
pcpandey@ee.iitb.ac.in
♠♠ • General • Analog Ckts • Digital Ckts • Artwork ♦♦ <<< >>>