Assignment - 3

Note: Unless otherwise stated, notation used is as defined in the class.

1. Given two Boolean functions F1 and F2 :

(a) Show that the Boolean function E = F1 + F2 , obtained by ORing the two functions,
contains the sum of all the minterms in F1 and F2 .
(b) Show that the Boolean function G = F1 F2 , obtained from ANDing the two functions,
contains those minterms common to both F1 and F2 .

2. Use a K-map to simplify the Bollean function F together with the don’t care conditions d in
product-of-sums form. X
F (w, x, y, z) = (0, 2, 4, 9, 12, 15),
X
d(w, x, y, z) = (1, 5, 7, 10).

3. With the use of maps, find the simplest form in sum of products of the function F = f g,
where f and g are given by:
f = wxy + yz + wyz + xyz
g = (w + x + y + z)(x + y + z)(w + y + z)

4. The following Boolean expression:

BE + BDE
is simplified version of expression:

ABE + BCDE + BC DE + B CDE

Are there any don’t care conditions? If so, what are they?

5. Use the Quine-McCluskey method to simplify the sum-of-products expression for

f (x, y, z) = xyz + xyz + xyz + xy z + xyz + x yz + x y z

6. Implement the following function with two-input NOR gates. Assume that both the normal
and complement inputs are available.

ABCD + ABCD + AB CD + ABCD

7. A sequential circuit has two D flip-flops A and B, one external input x, and one output z.
The flip-flop input equations and the circuit outputs are as follows:

DA = x′ A + xA′
DB = x′ A + xB
z = xB ′

(i) Draw the logic diagram of the circuit.

(ii) Tabulate the state table and derive the state diagram.
——-P.T.O.———
 8. Design a modulo-8 counter that counts in the way specified in Table 1. Use JK flip-flop in
your realization.

Table 1:
Decimal Gray code
0 000
1 001
2 011
3 010
4 110
5 111
6 101
7 100

9. For the machine in Table 2, find the equivalence partition and the corresponding reduced
machine.

Table 2:
N S, z
PS x=0 x=1
A F, 0 B, 1
B G, 0 A, 1
C B, 0 C, 1
D C, 0 B, 1
E D, 0 A, 1
F E, 1 F, 1
G E, 1 G, 1

10. For the incompletely specified machine shown in Table 3,

(i) Construct a merger table and find the set of maximal compatibles.
(ii) Draw the merger graph and the compatibility graph.
(iii) Determine a minimum-state reduced machine containing the original one.

Table 3:
N S, z
PS I1 I2 I3
A C, 0 E, 1 —
B C, 0 E, − —
C B, − C, 0 A, −
D B, 0 C, − E, −
E — E, 0 A, −

——-P.T.O.———
11. Analyze the synchronous circuit of Figure 1 (the clock is not shown, but is implicit).

y y
2 1 1
x J2 1 J1

y2
0 K1 y
0 1
x K2

AND AND AND

OR

Figure 1:

(i) Write down the excitation and output functions.

(ii) Form the excitation and state tables.

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