FIFO memory consist of write pointer ,read pointer, write address and read address

synchronous FIFO mean read operation and write operation asserted depends on clk.

condition :

1.read and write pointer should be one bit higher than read and write
address.
Empty is asserted your write pointer and read pointer in same position ( When the
read pointer reaches the write pointer, the FIFO is empty).

Full is asserted your write pointer one step behind read pointer.(If the write pointer
catches up with the read pointer, the FIFO is full)

Here is verilog code for synchronous FIFO:

module FIFO

#(

parameter DWIDTH=8,

parameter AWIDTH=2

input clk,

input reset_i,

input w_en_i,

input r_en_i,

input [DWIDTH-1:0]wdata_i,

output reg [DWIDTH-1:0]rdata_o,

output full,

output empty

);

localparam depth=2**AWIDTH;

reg [AWIDTH:0] wptr;

reg [AWIDTH-1:0] waddr;

reg [AWIDTH:0] rptr;

reg [AWIDTH-1:0] raddr;

reg [DWIDTH-1:0]mem[0:depth-1];

assign full = {!wptr[AWIDTH],wptr[AWIDTH-1:0]} == rptr ? 1'b1 : 1'b0;

assign empty = wptr == rptr ? 1'b1 : 1'b0;

always @(posedge clk)

begin

if(reset_i)

begin

rptr<=0;

wptr<=0;

waddr<=0;

raddr<=0;

rdata_o<=0;

end

else

begin

if(w_en_i && ~full)

begin

mem[waddr] <= wdata_i;

wptr <= wptr+1;

waddr <= waddr +1;

end

if(r_en_i && ~empty)

 begin

rdata_o <= mem[raddr];

rptr <= rptr+1;

raddr <= raddr+1;

end

end

end

endmodule

Correct code
1. module FIFO_memory(clk,reset,din,read,write,dout,empty,full);
2.  
3. input clk;
4. input reset;
5. input [15:0]din; //16-bit data input
6. input read;
7. input write;
8.  
9. output [15:0]dout; //16-bit data output
10. output empty; //flag to indicate that the memory is
empty
11. output full; //flag to indicate that the memory is full
12.
13. parameter DEPTH=3, MAX_COUNT=3'b111;
14. //DEPTH is number of bits, 3 bits thus 2^3=8 memory locations and
MAX_COUNT is the last memory location.
15.
16. reg [15:0]dout;
17. reg empty;
18. reg full;
19.  
20. /*head is write_pointer and tail is read_pointer*/
21.  
22. reg [(DEPTH-1):0]tail;
23. // tail(3bits) defines memory pointer location for reading
instructions(000 or 001....111)
24.
25. reg [(DEPTH-1):0]head;
26. // head(3bits) defines memory pointer location for writing
instructions(000 or 001....111)
27.
28. reg [(DEPTH-1):0]count;
29. // 3 bits count register[000(0),001(1),010(2),....,111(7)]
30.
31. reg [15:0]fifo_mem[0:MAX_COUNT];
32. // fifo memory is having 16 bits data and 8 memory locations
33.
34. reg sr_read_write_empty; // 1 bit register
flag
35.  
36. ///////// WHEN BOTH READING AND WRITING BUT FIFO IS EMPTY ////////
37.  
38. always @(posedge clk)
39. begin
40. if(reset==1)
41. //reset is pressed

42. sr_read_write_empty <= 0;

43. else if(read==1 && empty==1 && write==1)
44. //when fifo is empty and read & write both 1
45. sr_read_write_empty <= 1;
46. else
47. sr_read_write_empty <= 0;
48. end
49.  
50. //////////////////////// COUNTER OPERATION ///////////////////////
51.
52. always @(posedge clk)
53. begin
54. if(reset==1)
55. //when reset, the fifo is made empty thus count is set to zero
56. count <= 3'b000;
57. else
58. begin
59. case({read,write})
60. //CASE-1:when not reading or writing
61. 2'b00: count <= count;

62. //count remains same

63. //CASE-2:when writing only
64. 2'b01: if(count!=MAX_COUNT)

65. count <=

count+1;
66. //count
increases
67. //CASE-3:when reading only

68. 2'b10: if(count!=3'b000)

69. count <= count-

1;
70. //count
decreases
71. //CASE-4
72. 2'b11:
if(sr_read_write_empty==1)
73. count <=
count+1;
74. //(if) fifo is empty => only write, thus count increases
75. else
76. count <= count;
77. //(else) both read and write takes place, thus no change
78. //DEFAULT CASE
79. default: count <= count;
80. endcase
81. end
82. end
83.  
84. ////////////////////// EMPTY AND FULL ALERT /////////////////////
85.
86. // Memory empty signal
87. always @(count)
88. begin
89. if(count==3'b000)
90. empty <= 1;
91. else
92. empty <= 0;
93. end
94.  
95. // Memory full signal
96. always @(count)
97. begin
98. if(count==MAX_COUNT)
99. full <= 1;
100. else
101. full <= 0;
102. end
103.  
104. ///////////// READ AND WRITE POINTER MEMORY LOCATION /////////////
105.  
106. // Write operation memory pointer
107. always @(posedge clk)
108. begin
109. if(reset==1)
110. //head moved to zero location (fifo is made empty)
111. head <= 3'b000;
112. else
113. begin
114. if(write==1 && full==0)
115. //writing when memory is NOT FULL
116. head <= head+1;
117. end
118. end
119.
120. // Read operation memory pointer
121. always @(posedge clk)
122. begin
123. if(reset==1)
124. //tail moved to zero location (fifo is made
empty)
125. tail <= 3'b000;
126. else
127. begin
128. if(read==1 && empty==0)
129. //reading when memory is NOT ZERO
130. tail <= tail+1;
131. end
132. end
133.  
134. //////////////////// READ AND WRITE OPERATION ////////////////////
135.  
136. // Write operation
137. always @(posedge clk)
138. //IT CAN WRITE WHEN RESET IS USED AS FULL==0
139. begin
140. if(write==1 && full==0)
141. //writing when memory is NOT FULL
142. fifo_mem[head] <= din;
143. else
144. //when NOT WRITING
145. fifo_mem[head] <= fifo_mem[head];
146. end
147.  
148. // Read operation
149. always @(posedge clk)
150. begin
151. if(reset==1)
152. //reset implies output is zero
153. dout <= 16'h0000;
154. else if(read==1 && empty==0)
155. //reading data when memory is NOT EMPTY
156. dout <= fifo_mem[tail];
157. else
158. //no change
159. dout <= dout;
160. end
161. endmodule