Universidad del Valle de Guatemala

Engineering Faculty
Electronics Engineering Department
Digital Electronics

Laboratory 06 - Sequential Logic & Moore FSM

Instructions:
All excercises must be delivered via BlackBoard no later than 23:59hrs of the day of the lab. Failure to
comply will result in a deduction of 10 points from your grade. If you deliver your report over 12hrs
late the deduction will be of 25 points. This is a personal laboratory; everyone must deliver it.

All excercises must include a thorough explanation.

Exercise 01:

A JK flip-flop receives a clock and two inputs, J and K. On the rising edge of the clock it updates the
output Q. If J and K are both 0 Q retains its old value. If only J is 1 Q becomes 1. If only K is 1, Q
becomes 0. If both J and K are 1 Q becomes the opposite of its present state.

Construct a JK flip-flop using a D flip flop and some combinational logic.

Exercise 02:

Design a Moore Finiste State Machine (FSM) synchronous (all flip-flops change simultaneously) decade
counter using D resettable flip-flops.

A decade counter is a binary counter designed to count up to 1010b (decimal 10; this means 4 bits). It
counts from 0 to 9 and then resets to 0. The counter output can be set to zero by pulsing the reset line
low. The count then increments on each clock pulse until it reaches 1001b (decimal 9).

Exercise 03:

Modify your designed counter to work with JK flip-flops.