Spring 2022 (Akhan.Almagambetov@nu.edu.

kz)

ELCE 202 HW #08

Due: F 8 Apr 2022 23:59

PROBLEM #16.1 PROBLEM #19.1

Generate the Q output for a D flip-flop based on the clock Create a T flip-flop using VHDL. The device should only have
and D inputs below. (Redraw the waveform on a separate 3 ports: t and clk as inputs and q as output (no credit will be
sheet of paper. Use one square of engineering paper for given if more than 3 ports are present). Since you cannot read
every 2.5 ns.) data from output ports, you will have to create a temporary
signal and initialize it to zero:
1
signal qtemp : STD_LOGIC := ’0’;
CLK
1
Signals are implemented as “buffers”, so you can both read
D from and write to them.
1
The := operator initializes the signal to the specified value.
Q
Provide a simulation of the device.
10 ns 20 30 40 50 60 70 80

PROBLEM #16.2
Generate the Q output for a T flip-flop based on the clock and
T inputs below. (Redraw the waveform on a separate sheet
of paper. Use one square of engineering paper for every PROBLEM #19.2
2.5 ns.)
Based on the in-class VHDL design of a D flip-flop that had
1
three ports (d, clk, and q), create a D flip-flop that also has
CLK a reset (rst) pin.
1
The reset pin, when pulled high, should immediately set q to
T zero, regardless of the state of d. Think about the order of the
conditions in the ‘if’ statement and also which pins should be
1

Q included in the sensitivity list.

Provide a simulation of the device.
10 ns 20 30 40 50 60 70 80

PROBLEM #16.3
In class, we went over an example of an asynchronous “up”
counter, which ran through all possible number combinations
in ascending order.
Design an asynchronous 3-bit “down” counter using T (tog-
gle) flip-flops, which goes through all possible numbers in
descending order (i.e., 7-6-5-4-3-2-1-0, repeating).
Verify the functionality by drawing appropriate waveforms;
assume 1/8 clock period delay. Draw the waveforms in the
landscape orientation, using 6 squares per a single period of
the clock (a full transition from 0 to 1).