Buffers

Dr. Mohammed Najm Abdullah

1. In circuits where a logic gate has to drive a large capacitive load, buffers are
often used to improved performance
2. Buffers can be created with different amounts of drive capability (depending
on the size of the transistors used to construct them)
a) Larger transistors => more current handling capability
b) A common use of a buffer is to control a light emitting diode (LED)
c) Buffers have greater fan-out than other(regular) logic gates.

Tri-state Buffers (Gates)

• In a large system, the address lines would have to “drive” a very large number
of inputs--exceeding the “fan-out” capacity of the chip controlling the address
line

• The solution is using “tri-state” gates: gates with 3 states: a “1” state, a “0”
state, and a high impedance state

A tri-state buffer (gate) has

 One input (x)
 One output (f)
 One control input (e)

 When e=1, the buffer drives the value of x onto f, causing f=x
 When e=0, the buffer is completely disconnected from the output f

Dr. Mohammed Najm Abdullah

 Four type of tri-state buffers

Dr. Mohammed Najm Abdullah

Dr. Mohammed Najm Abdullah
Dr. Mohammed Najm Abdullah
 Gray Codes

•Invented by Emile Baudot (1845-1903)

•Originally called a “cyclic-permuted” code
•Telegraph -5 bit codes
 Bits stored on a code wheel in the receiver
 Wheel connected to the printing disk
 Matched pattern on wheel and received pattern and then actuated head to
print.
•Exhibited at Universal Exposition, Paris (1878)

Why Gray Codes?

•Single output changes at a time

 Asynchronous sampling
 Permits asynchronous combinational circuits to operate in fundamental mode
 Potential for power savings
•Multiphase, multi frequency clock generator

Dr. Mohammed Najm Abdullah

Question
Convert the Gray coded number 10011011 to its binary
equivalent.
Answer
The rules of conversion from Gray code to binary are given
in the Gray code summary
0T 0T

• The Gray code number has 8 bits so the Binary

equivalent will also have 8 bits
• The most significant bit (left-most bit) is the same in
both cases
• The next-to-most significant bit in the binary number
comes from adding the most significant bit in the binary

Dr. Mohammed Najm Abdullah

 number to the next-to-most significant bit in the Gray
coded number, the sum is noted and any carry ignored.
• Generally, working from left to right i.e. from most
significant bit to least significant bit, then the nth bit
(counting from right to left) in the binary number is
formed from summing the n+1th bit in the binary
number with the nth bit in the Gray coded number. The
corresponding sum is noted and any carry ignored.
In the case of this example

Gray Binary (same as Gray

10011011 =1
Code Digit 1 code)
Gray Binary =0+1
10011011
Code Digit 2 =1
Gray Binary =0+1
10011011
Code Digit 3 =1
Gray Binary =1+1
10011011 (carry 1)
Code Digit 4 =0
Gray Binary =1+0
10011011
Code Digit 5 =1
Gray Binary =0+1
10011011
Code Digit 6 =1
Gray Binary =1+1
10011011 (carry 1)
Code Digit 7 =0
Gray Binary =1+0
10011011
Code Digit 8 =1

and so
10011011 gray = 11101101 bin
R R R R

Dr. Mohammed Najm Abdullah

Programmable logic array
A programmable logic array (PLA) is a programmable device used to implement combinational
logic circuits. The PLA has a set of programmable AND gate planes, which link to a set of
0T 0T 0T 0T 0T 0T

programmable OR gate planes, which can then be conditionally complemented to produce an

0T 0T

output. This layout allows for a large number of logic functions to be synthesized in the sum of
products (and sometimes product of sums) canonical forms. 0T 0T

One application of a PLA is to implement the control over a datapath. It defines various states in an 0T 0T

instruction set, and produces the next state (by conditional branching). [eg. if the machine is in state
2, and will go to state 4 if the instruction contains an immediate field; then the PLA should define
the actions of the control in state 2, will set the next state to be 4 if the instruction contains an
immediate field, and will define the actions of the control in state 4]. Programmable Logic Arrays
should correspond to a state diagram for the system.
0T 0T

Other commonly used programmable logic devices are PAL, CPLD and FPGA. 0T 0T 0T 0T 0T 0T

Note that the use of the word "Programmable" does not indicate that all PLAs are field- 0T

programmable; in fact many are mask-programmed during manufacture in the same manner as a
0T

mask ROM. This is particularly true of PLAs that are embedded in more complex and numerous
0T 0T

integrated circuits such as microprocessors. PLAs that can be programmed after manufacture are
0T 0T

called FPLA (Field-programmable PLA).

Programmable Logic Array (PLA)

Introduction
One way to design a combinational logic circuit it to get gates and connect them with wires. One
disadvantage with this way of designing circuits is its lack of portability.

You can now get chips called PLA (programmable logic arrays) and "program" them to implement
Boolean functions. I'll explain what it means to program a PLA.

Fortunately, a PLA is quite simple to learn, and produces nice neat circuits too.

Starting Out
The first part of a PLA looks like:

Each variable is hooked to a wire, and to a wire with a NOT gate. So the top wire is x 2 and the one R R

just below is its negation, \x 2 . R R

Then there's x 1 and just below it, its negation, \x 1 .

R R R R

Dr. Mohammed Najm Abdullah

The next part is to draw a vertical wire with an AND gate. I've drawn 3 of them.

Let's try to implement a truth table with a PLA.

x2 x1 x0 z1 z0
R R R R R R R R R R

0 0 0 0 0
0 0 1 1 0
0 1 0 0 0
0 1 1 1 0
1 0 0 1 1
1 0 1 0 0
1 1 0 0 0
1 1 1 0 1

Each of the vertical lines with an AND gate corresponds to a minterm. For example, the first AND
gate (on the left) is the minterm: \x 2 \x 1 x 0 .
R R R R R R

The second AND gate (from the left) is the minterm: \x 2 x 1 x 0 . R R R R R R

The third AND gate (from the left) is the minterm: x 2 \x 1 \x 0 . R R R R R R

I've added a fourth AND gate which is the minterm: x 2 x 1 x 0 . R R R R R R

The first three minterms are used to implement z 1 . The third and fourth minterm are used to
R R

implement z 0 .
R R

This is how the PLA looks after we have all four minterms.

Dr. Mohammed Najm Abdullah

Now you might complain. How is it possible to have a one input AND gate? How can three inputs
be hooked to the same wire to an AND gate? Isn't that invalid for combinational logic circuits?

That's true, it is invalid. However, the diagram is merely a simplification. I've drawn the each of
AND gate with three input wires, which is what it is in reality (there is as many input wires as
variables). For each connection (shown with a black dot), there's really a separate wire. We draw
one wire just to make it look neat.

The vertical wires are called the AND plane. We often leave out the AND gates to make it even
easier to draw.

We then add OR gates using horizontal wires, to connect the minterms together.

Dr. Mohammed Najm Abdullah

Again, a single wire into the OR gate is really 4 wires. We use the same simplification to make it
easier to read.

The horizontal wires make up the OR plane.

This is how the PLA looks when we leave out the AND gates and the OR gates. It's not that the
AND gates and OR gates aren't there---they are, but they've been left out to make the PLA even
easier to draw.

Dr. Mohammed Najm Abdullah

Dr. Mohammed Najm Abdullah
Dr. Mohammed Najm Abdullah
Dr. Mohammed Najm Abdullah
Dr. Mohammed Najm Abdullah
Dr. Mohammed Najm Abdullah