2014 Fifth International Symposium on Electronic System Design

A Low voltage Inverter based Differential Amplifier for Low Power Switched
Capacitor Applications

Jagadish D. N., M. S. Bhat

Department of Electronics and Communication Engineering
National Institute of Technology Karnataka
Surathkal, India
email: jagadishdn.ec11f02@nitk.edu.in

Abstract—A low voltage and low power inverter based
differential amplifier is presented. The input stage is fully
differential in operation and the output stage employ class C
inverter to enhance the gain. An on-chip body bias improves
the slew rate performance. The amplifier is implemented in
UMC 90 nm technology. With load capacitance of 100fF, the
amplifier delivers DC gain of 81dB and unity gain bandwidth of
33.88MHz at 41◦ phase margin. For a dual power supply volt-
age of ±350mV, the quiescent current and power consumption
are 2.37μA and 1.66μW respectively. The amplifier achieves a
figure of merit of 2117. With the bulk of all the transistors
slightly forward biased by a fixed bias potential, the power
dissipation of 672nW and figure of merit of 5431 are achieved.
Keywords-inverter based amplifier; class C inverter; differ-
ential amplifier; on-chip bias; switched capacitor integrator;
I. I NTRODUCTION
Design of high gain amplifiers at lower voltages are
challenging. Cascoded structures could deliver, but will
exhibit lower output voltage swings. Inverter based cascaded
structures on the other hand achieve high gain and output
voltage swing close to rail to rail supply voltage. The
high dc gain is obtained by cascading multiple inverter
stages. The compensation gets quite complex in order to
make the amplifier in the close loop stable. In addition the
conventional CMOS inverter draw a larger quiescent current.
The transconductance of the devices increase tremendously,
for the same amount of current conduction as that of
saturation region, if operate in subthreshold region [1]. For
the switched capacitor integrator circuit, in addition to the
dc gain, the amplifier has to offer larger slew rate. The
slew rate (SR) is worst for the ’slow-slow’ corner. Class
C inverter structure on the other hand offer more gain at
lower quiescent current.
Inverter based amplifier structure in [2] show good per-
formance for PVT variations. The replica biasing circuit
draws power in addition to the main amplifier. Also the
mismatch between the transistors of the first stage of the
actual amplifier and the replica bias amplifier throw large
input offset voltage. The switched capacitor integrator in
[3] make use of gain boosted class C cmos inverter. Pseudo
differential topology is adopted to improve the performance
of the integrator. To reduce the variation of transconductance
across all process corners, a method of biasing the bulk of
the transistor is employed [4]. An auxiliary circuit with off
chip resistive load is meant to sense the corner indirectly by
reading the quiescent current.
In this work we present a low voltage and low power
inverter based true differential amplifier. The differential
input inverter based amplifier [5] is used as the first stage of
the amplifier followed by the class C inverter. The amplifier
is compensated by a small miller capacitance at the output
stage. All the transistors are designed to operate in the
subthreshold region. A dual power supply is used, thereby
eliminating requirement of body bias voltage generation.
The common mode voltages of input and output are at
GND. To improve the SR, the threshold voltage of all
NMOS transistors are reduced by fixed body bias and that
of the PMOS transistors are reduced by connecting the body
terminal to an on chip body bias circuit.
The rest of the paper is organized as follows. The section
II discusses the amplifier and the body bias scheme. In
Section III we use the amplifier in a switched capacitor
integrator circuit. Simulations are performed in section IV
and comparison with other designs are done in section V.
The paper concludes in section V.
II. D ESIGN
A. The Amplifier
Figure 1 shows the inverter based differential amplifier.
All the transistors operate in the subthreshold region. The
design uses N-Well technology. The N-Wells are biased
using an on-chip bias circuitry, while the p-substrate is
connected to common mode terminal GND. In the first
stage, transistors M1A and M1B form the NMOS differential
pair, while the transistors M2A and M2B are the PMOS
differential pair. The current sources formed by M3 and
M4 are self biased by the output of M1A and M2A inverter
pair. The source terminal of transistors M1A and M2A are
degenerated by the negative feedback. This ensures proper
biasing of the input differential pair against all variations
in the PVT. Since four amplifier devices are present the
differential gain is 6dB higher than the conventional inverter.

978-1-4799-6965-4/14 $31.00 © 2014 IEEE 58

DOI 10.1109/ISED.2014.20
 Figure 1. The Amplifier circuit.

Figure 2. Simplified small signal model of the amplifier.

The gain of the first stage is given by

A1 = (gm1 + gm2 )rd1−2 (1)
where gm1 and gm2 are the transconductances of transistors
M1A−B and M2A−B respectively and rd1−2 is the equiva-
lent output resistance at the first stage.
The output of the first stage is fed to the class C inverter
constituting M5A−B and M6A−B in complementary cascode
structures. The gain of the second stage could be written as Figure 3. The on-chip bias circuit for the amplifier.

A2 ≈ gm5 gm6 rd5 rds6 (2)

where gm5 and gm6 are the transconductances of transistors
M5A−B and M6A−B respectively. rd5 and rds6 are their
respective output resistances. The total DC gain is given by
AV = A1 A2 (3)
The second stage offers a high voltage gain as evident from
(2). Owing to this large gain, a small capacitance in Cc is
sufficient and is been connected across to provide necessary
compensation.
Figure 2 shows the simplified small signal model. v1
and v2 are the intermediary voltages at the pole locations.
C1 is the capacitor equivalent to the sum of drain capaci-
tances at node having voltage v1 and the Miller capacitance
(1+A2 Cc ). Due to the Miller effect, a dominant pole fp1
exist close to the origin and other poles are pushed to high
frequency region, providing good phase margin and thus
enabling good stability.
1 III. S WITCHED C APACITOR I NTEGRATOR
fp1 = (4)
2πrd1−2 C1
B. On-chip body bias
In order to improve the SR the threshold voltages of all the
transistors are lowered by slightly forward biasing the body
terminal, but away from large leakage current conduction.
With the N-Well process, the body terminals of all the
NMOS transistors are connected to fixed bias potential,
GND. However all the PMOS transistors are connected to
bias potential VBP to keep up to the SR at slow process
corners. The threshold voltage increase due to slow process
corner drives the transistor M7 from subthreshold to cutoff
region. The resulting increase in voltage at the drain terminal
of transistors M7 and M8 reduces the bias potential VBP .
This reduction of the bias potential forward biases the
bulk terminal of the PMOS transistors of the amplifier to
enhance the SR at slow process corners. The bulk of all the
PMOS could optionally be connected to fixed bias potential,
GND, as done for NMOS transistors, to lower the power
dissipation.
Figure 3 shows the bias circuit. The transistors M7 and
M8 track the threshold voltage change. The transistors M9
and M10 form the active load NMOS inverter.
The presented differential amplifier is used as a switched
capacitor integrator. The gain error of the integrator could
be expressed as
(Cin /CI + 1)
|gain error| ≈ (5)
AV

59
 (a)
Figure 4. Switched capacitor integrator circuit.

Figure 4 shows the switched capacitor amplifier. Due

to transistor mismatch non-idealities, the amplifiers posses
a DC offset voltage. The auto-zeroing technique [6] is
commonly employed to eliminate the low frequency noise
such as the offset voltage and the 1/f noise. Auto-zeroing
technique essentially stores offset voltage to a capacitor
during sampling phase and feeding back the the stored offset
such as to cancel the offset voltage from the signal path.
(b)
This is equivalent to shifting the virtual ground point of the
differential amplifier to the junction node of capacitors CI , Figure 5. Transient response of the amplifier for a square wave input
signal. (a) Without forward biasing of body terminal. (b) With on-chip
Cin and Co . The switches are operated in phases φ1 and φ2 . body biasing.
The SR of the integrator is enhanced by increased sizing
of the transistors in class C inverter circuit and by biasing
the body terminal of the transistors as well. The SR improve-
ments for different process corners are verified by subjecting
the integrator with square wave as input. The simulation
results are shown in the next section.
IV. S IMULATION R ESULTS
The presented amplifier has been designed and simulated
using Cadence tools with UMC 90 nm library cells. A dual
power supply of ±350mV is used. The transistors are sized
such as to have all of them in subthreshold region under
DC operating point. The amplifier in total draws quiescent Figure 6. Frequency response of the amplifier.
current of 2.37μA. The amplifier is connected with a load
capacitor of 100fF capacitance.
Figure 5(a) shows the transient response of the switched
capacitor integrator, for various process corners, with the
transistors having their body terminal shorted to their source
terminals.The SR for typical and slow-slow corners shows
1.6V/μS and 0.33V/μS respectively. Figure 5(b) shows the
transient response of the switched capacitor integrator, for
various process corners, with the NMOS transistors having
their body terminal slightly forward biased by being con-
nected to potential GND and PMOS transistors biased with
on-chip bias circuitry. The SR under body biased condition Figure 7. PSRR of the amplifier vs frequency.
is improved. The SR for typical and slow-slow corners
shows 15V/μS and 5V/μS respectively. The integrating and
sampling capacitors are chosen to be 100fF each in both the bandwidth of 33.88 MHz and the phase margin 41◦ . The
cases. gain variation for other process corners is close to ±10dB.
Figure 6 shows the frequency response of the amplifier. The total quiescent current is reduced by bypassing the on-
The DC gain for typical corner is 81dB with the unity gain chip bias circuitry for good process corners.

60
 Figure 11. Layout of the amplifier including body bias circuit.

voltage of the amplifier for all process variations and device

Figure 8. CMRR of the amplifier vs frequency. mismatch. The layout of the designed amplifier with body
bias circuit measured 14.8μM x 4.6μM and is shown in
figure 11.
V. C OMPARISON
Table I provides the comparison of the implemented
amplifier with other recently published high performance
amplifier designs. The amplifier is able to deliver voltage
gain greater than 80dB without any stability issues. The
implemented amplifier shows low power consumption and
operates at lower supply voltage. The figure of merit (FoM)
is computed as in [7] is higher.
Figure 9. Input referred noise of the amplifier (amplitude in log scale).
Table I
C OMPARISON WITH OTHER HIGH PERFORMANCE AMPLIFIER DESIGNS

[8] [7] [9] [10] This work

Tech. (μM) 0.18 0.13 0.18 0.05 0.09
DC gain (dB) 74 70 46 74 81 (82.3† )
GBW (MHz) 160 35 0.4 4.8 34 (36.5† )
PM (deg) - 45 - 49 41
Cap. Load (pF) 1.75 5.5 1.8 20 0.1
Input ref-noise - 14.1 - 59 74
√
(nV/ Hz)
Slew Rate (V/μS) 26.7 19.5 - - 15
Figure 10. Input referred offset voltage computed against process corner
variation and device mismatch of the amplifier. Supply Voltage (V) 1.8 1.2 0.7 0.5 ±0.35
Power (μW) 362 110 0.145 100 1.6 (0.672† )
FoM 772 1750 5746 960 2117 (5431† )
The PSRR performance is simulated with the amplifier (MHz*pF/mW)
†
in unity feedback configuration. Owing to the higher gain Refers to the simulated results when the on-chip bias circuit is replaced
by fixed bias, with potential equal to GND.
offered by the class C inverter, the PSSR achieved at lower
frequencies are close to 47dB and 45dB, respectively, for
VDD and VSS supply sources. The same could be verified
from figure 7. The true differential nature of operation of the VI. C ONCLUSION
amplifier supports a good CMRR ratio as evident in figure 8. A low voltage and low power inverter based differential
In order to achieve a low power consumption, the tran- amplifier is been presented. The amplifier provides high
sistors are restricted in size, thereby tends to increase noise. gain and remain stable at all process corners. The input
Figure 9 shows the input referred noise at various frequen- stage of the amplifier is fully differential giving high CMRR
cies. At frequency
√ of 1Mz the simulated input referred noise and the output stage employs class C inverter to provide
is 74nV/ Hz. high differential gain. An on-chip biasing of transistors is
A Monte carlo analysis with the transistor matching of 0.8 suggested to improve the slew rate. The presented amplifier
and σ of 3, is carried out with 200 runs, to estimate the offset could be used in the design of low voltage low power
voltage due to process corner variation and device mismatch. switched capacitor integrators for discrete time delta sigma
Figure 10 shows the histogram of the input referred offset modulators and filters.

61
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