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OPEN ENDED EXPERIMENT

LAB FILE
VERILOG PROGRAMMING (ECE 423)
AIM: TO IMPLEMENT VERILOG HDL CODE FOR
UART

DEPARTMENT OF ELECTRONICS AND COMMUNICATION


ENGINEERING
AMITY SCHOOL OF ENGINEERING AND TECHNOLOGY
AMITY UNIVERSITY, UTTAR PRADESH

Submitted to : Submitted by
Dr. Pradeep Kumar Yatharth Gupta(A2305116069)
Department of ECE, P. Uday Ashish(A2305116072)
Amity School of Engineering
and Technology, AUUP

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TABLE OF CONTENT

S.NO TITLE PAGE NO.

1. AIM 4

2. APPARATUS REQUIRED 4

3. THEORY 4-6

4. DESIGN 7

5. OBSERAVTIONS 8

6. RESULT 9

LIST OF FIGURES
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S.NO NAME OF FIGURE PAGE NO.

1. PROJECT LAYOUT 7

2. MAX. Q FACTOR VS. TIME 8

3. BER ANALYZER 8

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