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Performance Analysis and Propagation Delay Time Estimation of Logic

Families with HBTs

Conference Paper · November 1997

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 Performance Analysis and
Propagation Delay Time Estimation
of Logic Families with HBTs
J.del Pino, A.Hernández, J. García, B.González and A. Nunez
Centre for Applied Microelectronics. University of Las Palmas (Spain).

Abstract.
A study of the operation and performance of ECL and CML families implemented with HBTs
has been carried out. We have analyzed, by simulation, the behaviour of both logic families and
compared their performances with other high-speed FET based families. As in silicon
BJT-based circuits compared with CMOS, the HBT-based families are faster but more power
is consumed with regard to the other FET families. We have also developed timing models
expressed with simple equations. These equations are technology dependent and predict the
timing operation of logic circuits as function of load capacitances and of fan-out. It fits well the
behaviour of the gates against HSPICE simulations with errors smaller than 4% in all studied
cases.

1. Introduction
Heteroestructure Bipolar Transistors are bipolar devices exhibiting a similar
operation to the homoestructure bipolar transistor (BJT). The emitter region is
usually formed with a semiconductor material dissimilar to the base and collector
material, introducing a discontinuity in band diagrams and, therefore, putting in
technologist hands a new degree of freedom in the design of these kind of
devices. The main advantage of using HBTs is a larger value in current gain
compared with BJTs.
The logic families to be implemented with these transistors are the same as with
BJTs. BJT Gummel Poon SPICE model can also be used in simulations
involving HBTs as proposed in [2].
We will begin focusing our efforts in the evaluation of inverters based on these
logic families. DC parameters including transfer characteristic (Vo-Vi), noise
margins, fan-in (FI), fan-out (FO) and power consumption will be the object of
our study. Transient characteristics such as propagation delay and its dependence
with fan-in, fan-out and power consumption will also be attended.
Once evaluated the inverters, timing models will be developed. These are simple
expressions that allow us to know the propagation delay of circuits based on the
logic families under consideration. They will also be useful for showing which
of the circuit parameters are critical in the design of ECL and CML circuits
based on HBTs.
The performance of these HBTs gates are quantitatively compared with other
high-speed logic families demonstrating greater speed but higher power
consumption.
2. ECL and CML families
2.1 DC Operation
ECL and CML circuits are based on the non saturated emitter-coupled pair
depicted on figure 2. The CML circuit (figure 2) is a simplified version of a
ECL circuit (figure 1) in which the emitter follower is omitted for a higher
integration density. This emitter follower acts as a level shifter and as an
impedance adapter (it supplies current to the output and as a result the circuit
speed and fan-out are higher).

Fig. 1. ECL inverter. Fig. 2. CML inverter.

A direct consequence of using the emitter follower, is that the Q1 collector

voltage is isolated against any output load.
Taking the proper values for RL and Io, the circuit can be designed so that the
emitter-coupled pair transistors will never operate in the saturation region. This
is the main reason for the low propagation delay time of the ECL and CML
circuits. The reference voltage on the base of Q2 is Vref=-0.2V, and Vin is applied
to the base of Q1. The current source (Io) and the load resistance (RL) values are
1.5mA and 270Ω, respectively. The bias voltage value (Vee) is -3V. A
compromise between low power consumption and low propagation delay leads
to a voltage swing of ∆V=400mV [1]. This work has been carried out using
AlGaAs/GaAs HBTs model parameters taken from [2], [3] and [4]. Non supplied
parameters were taken by default. All measurements are computed from
simulations.
The simulated noise margins for ECL and CML circuits using the transistors
under study are shown in table I.
The maximum fan-out for ECL and CML circuits are listed on table II. It can
be seen that ECL gates have a larger fan-out than CML ones. As discussed
above, this is because the emitter follower in the ECL gate supplies current to
the following stages. Furthermore, the load current is the base current of non
saturated transistors.
The fan-in measurement was carried out using multi-input NOR gates, which are
made adding to the inverter circuit parallel transistors as inputs. Also in table II
the obtained fan-in values are listed. It can be seen that, in most cases, both,
fan-out and fan-in are not determinant factors in this kind of circuits. However,
 Table I. Noise margins measured in mV. Table II. Fan-out and fan-in.

ECL ECL CML CML FO FI

NMH NML NMH NML ECL CML ECL CML
[2] 59 60 65 65 [2] 40 6 70 85

[3] 70 77 83 83 [3] 100 40 100 100

[4] 71 71 22 22 [4] 3 2 100 30

this is true only in DC design. In transient design, if a high circuit operation

speed is desired, the propagation delay has to be taken into account and the
number of gates loading a given gate has to be limited. The study of the
problems related to transient design is the object of the next section.

2.2 Transient Analysis

There are several factors that contribute to a logic circuit propagation delay. One
of them is the wiring capacitance. This capacitance appear mainly due to the
coupling between the interconnections and the surface material. At this point, it
should be stated that, GaAs and its alloys show smaller capacitances than Si for
the same structure. This leads to a higher operation speed in III-V HBTs as
compared with silicon BJTs. Another source of capacitance is fan-out. Gates
inputs are outputs capacitances to the preceding gates associated with the active
components. This capacitance varies with the voltage, making difficult the
estimation of the propagation delay. Another effect is the intrinsic delay
associated with the electron transit time across the transistor. This transit time
τ is characterized by the intrinsic frequency fT; in fact, τ=1/2πfT. The transit time
τ can be minimized using materials or structures with high electron mobilities
[5]. The propagation delay (tpLH, tpHL, and tp defined as (tpLH+tpHL)/2) were
measured by transient analysis simulations for several fan-outs. The results of the
propagation delay of ECL and CML circuits based on transistor [3] (ECL91 and
CML91) are shown in figures 3 and 4, respectively.

Fig. 3. Prop. delay times for ECL91 inverter. Fig. 4. Prop. delay times for CML91 inverter.
From these plots it can be concluded, as expected that both, the propagation
delay tp and rising and falling times (tpLH and tpHL) degrade with fan-out.
For a given fan-out, ECL gates demonstrate a faster response than CML ones.
Besides, ECL gates have a higher fan-out. However, as it will be discussed later,
the power consumption of an ECL gate is greater than that of a CML circuit.
Furthermore a CML circuit has fewer components, hence a higher integration
density for a given package.
The linear wiring capacitance has a decisive influence on the transient response.
In logic circuitry this capacitance ranges over a wide range depending on the
interconnection length. The circuit propagation delay can be estimated by the
well known expression,
dv (1)
i C
dt
It is necessary to increase the available current for charging and discharging this
load capacitance when the gate is strongly loaded. For the ECL circuit, this is
obtained adding an emitter follower to the output which contributes to charge the
load capacitance. This is better than enlarging all transistors active area because
it has the advantage of a smaller power consumption increase. The propagation
delay of ECL91 and CML91 gates varying with the load capacitance CL is
shown in figure 5. It is clear that the propagation delay variation with the load
capacitance is smaller than with the fan-out. Besides, CML gates are more
sensitive to a load capacitance variation than ECL gates.

Fig. 5. Prop. delay for ECL91 and CML91 vs. CL.

The average power consumption of a logic circuit can be expressed as a linear

combination of the average static power consumption and the average dynamic
power consumption.
P Psta Pdyn (2)

We calculate the static power consumption, i.e. the power consumption when
there is a high level at the output (POH) and the power consumption when there
is a low level at the output (POL). For the ECL circuit POH can be calculated
from,
( Vee V1 )2
POH Io ( Vee) Vref Iref (3)
Ref

where V1 is the high level voltage. Similarly, POL can be expressed as,
( Vee V0 )2
POL Io ( Vee) Vref Iref (4)
Ref
where V0 is the low level voltage.
These expressions can also be used for the CML circuit shown in figure 2
removing the term related to the emitter follower. Because of this, the power
consumption of CML gates is smaller than that of ECL gates. Furthermore, if a
little current Iref is supposed for both gates (this is valid because it is a base
current), it can be seen that, for the ECL gate, the power consumption varies
with the input (Vin), while for the CML gate the power consumption does not
depend on the input. As a consequence, the POH and POL difference for the ECL
circuit is greater than that of an CML circuit. This can be seen from the SPICE
simulation data shown in table III. In this table, the average static power
consumption is also shown.

Table III. Power consumption measured in mW.

P in ECL CML
mW POH POL Pst POH POL Pst
[2] 7.6 7.0 7.3 4.5 4.5 4.5
[3] 7.4 6.6 7.0 4.5 4.5 4.5
[4] 7.1 6.8 7.0 4.4 5.0 4.7

These values have to be added to the dynamic power consumption. The dynamic
power consumption is a direct consequence of the required energy to charge and
discharge the circuit capacitances in a unit time. For ECL and CML circuits,
these capacitances are concentrated in a unique load capacitance CL. This
capacitor models the wiring capacitance between two consecutive stages. The
required energy to charge and discharge this capacitor, being ∆V the voltage
swing, is given by CL∆V 2/2 .
If the input signal is a periodic signal, and its frequency is f, the capacitor
charges and discharges once a cycle. Consequently, the dynamic power
consumption can be expressed as,
 PD f CL∆V 2 (5)

In typical designs, the contribution of PD to the overall power consumption at the

working frequency can be neglected. For example, for a CL of 100 fF and a
frequency of 1GHz the dynamic power consumption is 16µW. This dynamic
power consumption is three orders of magnitude less than the static power.
Therefore, the term Pdyn in equation (2) can be neglected.
As a result, the total average power consumption can be expressed approximately
as the average static power consumption. The corresponding values are listed on
table III and can be seen with the meaning of total power consumption.

3. Timing Model
There are two groups of delay expressions empirical models and analytical
models. The main object of the former model is to find a simple expression
based on simulation that quickly predicts the propagation delay for a huge set
of logic gates and even gate networks. This kind of models are useful for ASICs
development tools. The latter model analyses the dependence of the propagation
delay upon the electrical parameters. In turn, these parameters are related with
the fabrication process parameters. This kind of expressions, although more
complicated, provides a clear insight into the relationship between the
propagation delay of a circuit and its electrical parameters, and therefore it
provides an effective method to optimize the process and improve the circuit
speed.
In this section, an empirical model will be presented. Analytical expressions can
be found in [1] and [6].
The propagation delay of ECL and CML circuits are mainly affected by two
elements: the wiring capacitance (CL), and the fan-out (FO). We first present the
derivation of the propagation delay for an ECL91 gate. Then expressions for the
other gates and some conclusions will be presented. MATLAB [7] was employed

Fig. 6. tp vs. CL (SPICE results: solid line; Fig. 7. tp vs. FO (SPICE results: solid line;
model equation (6): dotted line). model equation (8): dotted line).

to calculate the timing models. We work under the assumption that the
propagation delay of the logic circuit can be expressed as a linear combination
of CL and fan-out delay contributions. So in the first part the tp variation with CL
will be computed, and then, in the second part, the same will be done with the
tp variation with fan-out.
The propagation delay of an ECL91 gate varying with the load capacitance is
shown in figure 6 (solid line). From this plot, it can be concluded that the
behaviour of the propagation delay is quite linear over a wide range of CL
values. Therefore the following expression can be written,
tp 16.4 83.5 CL (ps) (6)

with CL measured in fF.The predicted tp values from equation 6 are also

presented in figure 6 (dotted line). From this plot, it can be seen that the
prediction of the propagation delay expression is excellent as compared with
SPICE simulation. The maximum relative error is 1.22%.
In section 2.2 it was shown that the propagation delay dependence with fan-out
is not linear. We propose a polynomial model as,
tp 16.4 83.5 CL K1 K2 FO K3 FO 2 (7)

By minimum squares adjustment we have,

tp 28.68 83.5 CL 6.56 FO 0.02 FO 2 (8)

Figure 7 shows how the timing equation (8) agrees with SPICE simulation. This
figure demonstrates that the accuracy of the propagation delay expression is quite
good. The maximum relative error is 1.8%. The timing models for the other
gates under study and some conclusions extracted from them are summarised in
the following section. The propagation delay expressions for the remainder gates
are shown in table IV. There, the maximum relative error for each expression is
also shown. The agreement is quite good for most of the circuits, being the
maximum relative error in all cases less than 3.25%. In some cases, the tp
dependence with the fan-out is linear as opposed to what may be expected.
Table IV. Model equations and maximun relative error for all gates
under consideration.

GATE Model equation Error(%)

ECL90 tp=30+112.4 CL+4 FO 3.25
ECL91 tp=28.7+83.5 CL+6.6 FO-0.02 FO2 3.09
ECL93 tp=101.3+95.3 CL+7.4 FO+0.1FO2 0.1
CML90 tp=35+235.8 CL+4 FO 0.98
CML91 tp=30+207.0 CL+13 FO 0.2
CML93 tp=100+208.5 CL+5 FO2 0.03
Figure 8 depicts the propagation delay variation with both, the load capacitance
(CL) and the fan-out (FO) for the ECL91 gate. It is clearly seen that the tp is
more sensitive to fan-out variations than to CL variations. In fact, the propagation

Fig. 8. tp vs. CL for various FO values (SPICE results:

solid lines; model equation (8): dotted lines).

delay varies from 1.5ps for FO=1 to 500ps for FO=100, whereas for a given
fan-out, given the nearly horizontal line, the propagation delay has a little
variation with CL. For this reason, in a design using ECL circuits, the designer
has to put more attention to fan-out requirements than to the wiring capacitances
requirements. On the other hand, in figure 8 are also shown the predicted tp
values. In spite of the error committed (see table IV), the delay expressions
presented can be useful for an IC designer who used this basic logic gates. The
obvious advantage of using these timing models to predict the propagation delay
of a bipolar circuit over a circuit analysis program such as SPICE is that it can
save CPU time. What is more important, they are very useful in design,
optimization and performance prediction of bipolar logic circuits.

4. Conclusions
The logic circuits based on ECL and CML gates studied in this work for several
HBT technologies have demonstrated ultra-high speed operation. The propagation
delay of a set of high speed ECL and CML technologies based in HBTs are
shown in figure 9 for FO=1 and CL=0. In the figure CMOS data belongs to a
1µm technology, DCFL(1) and SDCFL(1) correspond to EGAS89 process
technology (Triquint) and DCFL(2) is for a H-GaAsIII process technology. It can
be seen that, as a general rule, the faster logic is ECL, followed by CML. So,
the ECL inverter, with a propagation delay of 16.9ps is the fastest, being
followed by ECL90, CML90, and CML91 with 17.6, 19.5 and 21.7ps
respectively. ECL93 and CML93 gates with 54.4 and 52.1ps, respectively, had
a worst response than the above, being even slower than the H-GaAsIII
MESFETs inverters whose tp is 46.1ps.
However, this needs to be explained because ECL93 and CML93 circuits are
based on transistor [4] which was developed primarily for microwave and not
for digital circuits. Even so, all ECL and CML studied circuits have demons-

Fig. 9. Propagation delay for FO=1 and CL=0 for different

technologies.

Fig. 10. Power consumption for different technologies.

Fig. 11. Power-delay product for different technologies.

Fig. 12. Power-delay product per fan-out for different

technologies.

trated faster operation than all the remainder circuits listed in figure 9. We have
further evidence that even higher speeds can be achieved with them. GaAs
SDCFL and DCFL inverters and CMOS inverters with 95.9, 108.6 and 115ps
 respectively are all slower than these ECL and CML circuits.
However, CML and even more ECL circuits have a higher power consumption
than the other circuits being compared. According to figure 10, the ECL and
CML power consumption is approximately 7 and 4.5mW respectively, whereas
the power consumed by other circuits like MESFETs are less than 0.45mW. For
this reason, ECL and CML gates are only useful for high performance circuits
where the power consumption is not so critical, or specific applications where
the logic gates are strongly loaded. An example of this kind of application is a
circuit with high wiring capacitance or with high fan-out.
A figure of merit used in logic circuits evaluation is the power-delay product
shown in figure 11. MESFETS circuits are better in this regard than the other
circuits even HBTs ones. Another figure where the fan-out is included is
presented in figure 12. There we have the power-delay product divided by the
maximum fan-out of the logic family. This figure provides evidence for using
HBTs in digital circuits with high loads in its nodes. This graph points out the
bad performance of transistor [4].
The delay expression shown in section 3 is a useful tool for the evaluation of a
large circuit propagation delay time. Another use is for performance prediction
and timing verification. The delay expressions presented in this paper can be
useful for porting ASICs development tools to novel HBT-based technologies.

References
[1] Wen Fang: "Accurate Analytical Delay Expressions for ECL and CML
Circuits and Their Applications to Optimizing High-Speed Bipolar Circuits,"
IEEE Journal of Solid-State Circuits, VOL.25, NO.2, pp 572-583 April 1990.
[2] Madjid E. Hafizi, Clarence R. Crowell, Matthew E. Grupen: "The DC
Characteristics of GaAs/AlGaAs Heterojunction Bipolar Transistors with
Application to Device Modeling," IEEE Trans. Elect. Dev., VOL.37, NO. 10 ,
pp. 2121-2129, October 1990.
[3] Andre Hagley, Derek Day, Duljit S. Malhi, y J. M. Xu: "High-Speed
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[4] Douglas A. Teeter, Jack R. East, Richard K. Mains, George I. Haddad: "
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[5] Stephen L. Long, Steven E. Butner, "Galium Arsenide Digital Circuit
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[6] Eng-Fong Chor, Arthur Brunnschweiler, Peter Ashburn: "A
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