An Asynchronous Delta-Sigma Converter
Implementation
Dazhi Wei, Student Member IEEE, Vaibhav Garg, Student Member IEEE and John G. Harris, Member IEEE
Department of Electrical and Computer Engineering, University of Florida,Gainesville
Email: {dazhiwei, vaibhavg, jgharris} @ufl.edu
Abstract- In this paper an architecture, signal reconstruction
algorithm and first-ever implementation of an asynchronous
delta-sigma converter are presented. The signal reconstruction
algorithm can mathematically perfectly reconstruct the original
signal only using timing events. A prototype circuit designed and
fabricated in a standard 0.5 ,um CMOS process with a 5V power
supply is presented. The tests show that an 8-bit resolution with
6kHz signal bandwidth and only 715 ,um power consumption is
possible.
I. INTRODUCTION
There is great interest in reducing the power and/or in-
creasing the speed of delta-sigma analog-to-digital converters
(ADCs). Continuous-time delta-sigma modulation is one av-
enue to increase converter speed by using a continuous-time
integrator but keeping the clocked quantizer [1]. Alternatively
Allier et al have designed a new class of asynchronous ADCs
based on level crossing sampling and time quantization [2]
but do not present a reconstruction algorithm to convert non
uniformly sampled sequences to uniformly sampled sequences.
Asynchronous delta-sigma converters which means converters
without clocks of any kind [3], [4] on the other hand,
have promise for ultra-low power consumption because of the
extreme simplicity of the required analog circuitry without any
oversampling requirements.
x(t) Xcld t + :)
g-
dt -o Schmid trIgge ~~~~~~~~~~~~x()
cf 0
L _ * , ~~~~~~~~~~Nyquist
1-bit DAC
Fig. 1. Architecture of the asynchronous delta-sigma converter
Figure 1 shows the architecture of a typical asynchronous
delta-sigma converter based on the scheme proposed by Lazar
and Toth [4].This architecture does not use a clock to sample
the analog signal, and no quantization operation is involved
during the data conversion. The difference between the input
signal -(t) and the fedback analog value corresponding to
the Schmitt trigger output y(ti) is continuously integrated,
The Schmitt trigger output y(th ) switches from low to high
if the integrator output rises above the high relerence voltage
0-7803-9390-2/06/$20.00 ©C2006 IEEE
Vrh, switches from high to low if the integrator output drops
below the low reference voltage Vr1, and otherwise remains
unchanged. If there are no nonidealities during the data
conversion, the nformation in the analog signal Si losslessly
encoded in the transition timings t9 of the Schmitt trigger
output. The asynchronous converter described here requires
no oversampling in principle, however a small amount of
oversampling increases the signal to noise ratio (SNR) in
practice.
II* SIGNAL RECONSTRUCTION ALGORITHM
The Schmitt trigger output is discrete in amplitude and
continuous in time and necessitates time quantization to obtain
digital output. Moreover, since most current digital systems
can only process uniformly sampled data, the nonuniform
nature of the Schmitt trigger output requires another signal
processing block to convert to a uniformly sampled sequence
for subsequent digital processing. The overall ADC perfor-
mance is not only dependent on the accuracy of the encoding
circuit, but also on the efficiency of the signal reconstruction
block. We have implemented a variation of the reconstruction
algorithm proposed by Lazar and Toth [4] which has roots
in mathematical frame theory [5]. We have also applied our
algorithm to reconstruct signals from a variety of hardware
spiking neuron models [6]. We assume the input signal x(t) is
bandlimited to [-Qs, Qs], and therefore can be expressed as
a sum of weighted Sinc functions:
sin(QS(t Sf)(1
-
if the maximum interval between adjacent sj is less than the
period wr/Qs. Here Wj is the scalar weight of the Sinc
~~~~~function at time s.
The encoding operation of the converter can be summarized
as
t+ ftL+I x(t)dt (-1)ia(2ti - -ti) (2)
t
We can substitute Equation 1 into Equation 2, and obtain a
system of linear equations
j i )a2i1 t+ i 3
N
where coefficients
fI+2 sin(Qs(t -s)dt
'Li Q(t - t
4903 ..ISCAS 2006
 Vdd
M;3 Vbl 10 M1i t E1
g. o
0i M5 M6 Schmitt trigger
~~~~~~~~~~~~~~~~~~~~~~~~~~~outpu

M7 M~~~8 MLC 12 M14

Vin Vin+ Vout andVin
VbOi ~~~~~~~~~~~~~~~
output
Mu ~~Vb M12

ml M14
M8 ~~M6 M71M9 M13 M1
Gnd G
VCM - a

Fig. 2. Circuit Implementation of Integrator Fig. 3. Circuit of the Schmitt trigger (MO-13) and the 1-bit DAC (Mi4-15)

are constants depending only on the transition timings ti,

andas dows nong iny tors. The second
i Eq(tj + tj±2)/2 Finally we solve Equation 3 to obtain the
weights wj, and then use Equation 1 to reconstruct the signal
very f input pand dOe require
tany t reference tansistors.nd
l input ar MO3 i r transconductanc
x(t). From Equation 3 we can see that the reconstructed signal amplifier (M4-13) to form the positive feedback that provides
is only dependent on the DAC output a and the Schmitt trigger hysteresis. The inverter (M12-13) is needed to increase the
output transition timings tf and is immune to process variation loop gain and to produce the digital output. It turns out lb, has
or other device parameters such as Gm,, C, and (Vrh - l7r1). to be larger than 'b2 for proper operation. The Schmitt trigger
The sufficient condition to meet the bandwidth requirement works as follows. Assuming initially the output Vdstt is low and
p sEquation 1 is that the maximum interval between adjacent the in sV . much lower than the reference Vgifn transistors
timings sj and sj±i, or equivalently between adjacent transi- MI and M5 are off and transistors M2 and M4 are on. Current
tion timings tI and t is less than w/Q,. We can show that lb, flows through M4 and the currentsb2 through M2 and thus
the condition for all signals which requires that the magnitude 'bl + eb2 flows through M6 while no current flows through
of signal x(t) be bounded by transistors MI, M5 and M7, and the output V,,, is kept low.
If Vj, decreases it will not change the current flow and thus not
CA.rh Vrl)Qs
affect this state. IfVto increases, current begins to switch from
TX(t e a - C(Vrh - is (5)
7]Gma M4 to M5, and thus current through M6 increases and current
III. CIRCUIT IMPLEMENTATION through M7 decreases. Once the currents through M6 and M7
A. Integrator are both equal to (Ibl + Ib2)/2, an increase in Vi will cause
more current to flow through M7 than M6, and thus cause
The integrator shown in Figure 2 is implemented with a the output Vo,, to increase. Meanwhile the increase of V0"
transconductance amplifier Gm, [7] with a capacitive load C. will also switch more current from M2 to MI, which further
Two PMOS transistors M5 and M6 working in the triode causes more current to flow through M7 than M6. A positive
region provide a conductance with a wide linear region. Since feedback mechanism is activated and Votl is exponentially
transistors MI and M2 have smaller W/L ratios compared to increased from low to high. Similar analysis can be applied
the load transistors M3 and M4 and the corresponding voltage to the case of switching Votl from high to low. It turns out
gain gml/gm3 is less than one, the linear input region of that the high and low reference voltages are the input voltages
the integrator is further increased. A larger linear input region which cause the current through M4 to equal (Ibl - Ib2)/2
is critical since it means larger allowable signal power with and (Ibl + Ib2)/2 respectively. For above-threshold square-law
decreased high-order harmonic distortions introduced in the operation we can obtain the reference voltage swing vrh - Vr1
signal band. However this decrease in harmonic distortion is as
at the cost of more input referred noise. Therefore transistor 2( 'bl + Ib2 - bl Ib2)
sizes must be chosen carefully to make the tradeoff between Vrh2- r-l =,C (/L) (6)
linearity and noise. The transconductance can be written as 0/ o xr(W/L)4
Gm = 4507 i,(w/L) ,and can be tuned via the bias which can be tuned via bias currents after fabrication. We can
current IB 1 after fabrication. also derive the transconductance of the Schmitt trigger at the
B. Schmitt
Trigger ~~~~~~~switching
points as
The circuit implementations of a novel Schmitt trigger and _2
the 1-bit DAC are shown in Figure 3. The Schmitt trigger is Ym 1/9m4 + 1 /9m6

4904
 2 6

j7 _2
bl 4b2
bl
bl
b2 pCox(W/L)4
,u+
/:9 (7)
40
The 1-bit DAC is just a simple inverter with sources con-
nected to appropriate analog voltages VCM + a and VCM- a. z
VCM is the common mode voltage and a is half of the full cn
scale analog voltage, which are determined by the input linear 20
region of the integrator. 10
C. Non Idealities and Tradeoffs
The signal reconstruction algorithm discussed in section II -60 -50 -40 -30 -20 -10 0
assumed that the integrator is ideal. However in practice the Sine wave amplitude (dBFS)
amplifier has finite output resistance which results in a leaky
integratr hasnd e mutcoir *itsne ntherecons truction Fig. 4. Plot of the SNR vs. sine wave amplitude of the asynchronous delta-
sigma converter chip(the sine wave frequency is I kHz, the converter signal
Assuming the output resistance of the amplifier is R, the bandwidth is 6 kHz, and 0 dBFS refers to 0.2 V full scale amplitude)
integration operation is described by
dVo V0 ___
C dt° Gm V Gm (V - A (8) input referred noise. Larger transconductance, or equivalently
dt R ADC larger unity gain bandwidth with constant load capacitance, is
where ADC = GmR is the DC voltage gain of the transcon- also preferable because the regeneration speed of the positive
ductance amplifier and VO and Vi are output and input voltages feedback is faster [8] and thus the output requires less delay
respectively. The last term in Eq. 8 represents the non ideality to reach logical states. Actually it is the variance of the delay
and we need to give guidelines on how to minimize its that affects the reconstruction performance since the mean of
effect on the output. Mathematically we can achieve perfect the delay can be cancelled in the algorithm. The variance of
reconstruction for the converter with the leaky integrator if the delay arises from its dependence on the slew rate of the
all the parameters a, R, and C and transition timings ti are input voltage of the Schmitt trigger. The variance of the delay
known using is smaller for larger unity gain bandwidth which results in

j j (-laRC(e
e
-ci )
= ( )ii+l
(9) better performance. It is clear from Eq 6 and 7 that a tradeoff
must be made between the reference voltage swing and the
transconductance to choose proper transistor W/L ratio for
where cofficients given bias currents. Also from Eq 8 less reference voltage
[ti+l sin(Qs(t - s) t-t±i+ swing, vrh - vrl i.e. VO, is helpful to reduce the noise power
ci) 'i Q (t j) - C dt+ due to the leaky integrator, which is yet another tradeoff.
sin(Qs(t - sj)
It~2 i+2()
d IV. CHIP TEST RESULTS
(i+t e C t The chip was fabricated using AMI 0.5 ,um CMOS Tech-
are constants depending only on the transition timings ti, and nology using MOSIS. The core die area is 27600 ,um2. For
Si = (tj + tj+2)/2. However in practice the output resistance the integrator, the capacitance is 10 pF, and the bias currents
R is usually a signal and process dependent term ro = 1/Al 'bo and lbl are 5 ,uA and 4 ,uA respectively, the common
and exhibits some nonlinearity and unpredictability, moreover, mode input voltage is 2.6 V and the common mode output
the algorithm is sensitive to the estimated value of the output voltage is 1.8 V. For the Schmitt trigger, the reference voltage
resistance, therefore it is difficult to have satisfactory recon- Vref is 1.8 V, the bias currents lbl and 'b2 are 36 ,uA and
struction using Eq. 9 and 10. However we may consider the 26 ,uA, and the corresponding (vrh - vr1) = 0.5 V. For
leaky term -VO/ADC in Eq. 8 as input referred noise whose the 1-bit DAC, logic high and logic low correspond to 2.7
variance degrades the reconstruction performance. So, from V and 2.3 V, which means a = 0.2 V. The input voltage
Eq. 8 we see that higher output voltage swing(VO) and lower sine wave is x(t) = 2.5V + A sin(27ft). A logic analyzer is
DC gain(ADC) would increase noise power and therefore used to capture transition timings of the chip output, and then
degrade performance. By adjusting the DC gain and output the signal is reconstructed in Matlab to a uniformly sampled
voltage swing we can estimate the desired noise power and sequence using the algorithm discussed in Section II. We have
hence the signal to noise ratio. implemented two tests to characterize the chip performance
The Schmitt trigger is a critical component to perform based on the IEEE standard 1241 for ADC test [9].
the sampling operation of the converter. A larger reference a) 4-parameter sine wavefitting test. Figure 4 shows the
voltage swing vrh -vrl is usually preferable since essentially measured SNR vs. the amplitude of the sine wave with 1 kHz
the performance is determined by the value of vrh -vrl frequency, where the signal bandwidth of the converter is 6
divided by reference variations caused by nonidealities such as kHz (Qs 12000wr rad/sec), and 0 dBFS refers to a sine wave

4905
 55 a7
,__
50
m 40
c/) -O
35~~~~ --- ---
1 o0 1 03
Sine wave frequency (Hz)
Fig. 5. Plot of the SNR vs. sine wave frequency of the asynchronous delta-
sigma converter chip(the sine wave amplitude is -2.5 dBFS)
with 0.2 V amplitude. As the sine wave amplitude increases,
the SNR increases with a slope of ldB/ldB to reach the peak
of 51 dB at around -2.5 dBFS, and then quickly drops to
0 dB. The SNR drop is due to the increased nonlinearities
caused by the larger amplitude signal input and the frequency
aliasing caused when the maximum interval between adjacent
transition timings grows larger than the Nyquist period 7/Q,.
We conclude that the chip can achieve 51 dB SNR (more
than 8-bit resolution). The power consumption of the chip
excluding pads and buffers is around 715 uW. In order to show
that the performance is consistent for different frequencies, we
also provide a plot of the SNR vs. the frequency of the sine
wave with a -2.5 dBFS amplitude in Figure 5. The SNR is
above 50 dB for frequencies up to 6 kHz bandwidth.
b) Sine wave histogram test: Sine wave histogram testing
iS also performed to measure the differential nonlinearity
(DNL) and integral nonlinearity (INL).The input signal to the
chip is a sine wave with a 1 kHz frequency and a -2.5dBFS
r and Systems, Vancouver, May 2003, pp. 196-205.
amplitude. The sampling frequency of the reconstructed signal
is not harmonically related to the sine wave frequency as
required by the IEEE standard 1241. With the assumption of
bit. reoltin,teoninaitesar
8 bit resolution, the nonlinearities are calculated
alulte and plotted
ndpl
in Figure 6. We can see both DNL and INL are less than 1
LSB, which verifies that the chip achieves an 8-bit resolution.
V. CONCLUSION
We have shown how to implement an asynchronous delta-
sigma converter for analog to digital conversion. The schmitt
trigger presented here is a completely novel idea.To the best of
our knwledg,this
our knowledge, thi implmentaion
implementation iiS the
the irst synchonous
first asynchronous
delta-sigma converter chip to have been successfully built for
analog to digital conversion. We believe this architecture has
promise for low power consumption because of the extreme
simplicity of the required analog circuitry and no need for high
oversampling. The circuit design can be improved to lower
power requirements and increase usable input linear region
for AC signal.
1
.5
0 50 100 150 200 250
z
.5
Sn 0 50 100 150 200 250
1 04'-
- 50 100 150 200 250
Output Code
Fig. 6. Plots of the DNL and INL from the sine wave histogram test of the
asynchronous delta-sigma converter chip
The overall ADC performance is determined by the ac-
curacy of the sample time and will take advantage of the
faster circuitry provided by the VLSI process scaling. Since
the nonuniform sample sequence is discrete in amplitude and
robust to transmission noise, the sample sequence can be trans-
mitted out of the converter front end and the reconstruction
algorithm can be run remotely in locations where power and
circuit size are not a big issue. These characteristics determine
that the asynchronous delta-sigma converter will likely be
suitable for power limited applications such as remote sensing
and implanted biomedical devices.
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