FPGA Implementation of Shaped Offset QPSK

Modulator
Dominik Rieth∗† , Christoph Heller† , Gerd Ascheid∗ ,
∗ Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, Germany
dominik.rieth@rwth-aachen.de, ascheid@ice.rwth-aachen.de
† Airbus Group Innovations, Munich, Germany

{dominik.rieth, christoph.heller}@airbus.com

Abstract—This paper presents a novel architecture for the the proposed SOQPSK modulator within this paper highlights
modulation scheme Shaped Offset QPSK (SOQPSK), which the fact that it is worth having a closer look into the transmis-
belongs to the class of Continuous Phase Modulations (CPMs). sion part of a CPM modulator, too.
These waveforms have recently regained remarkable popularity,
due to the increasing demand of highly energy and spectral The rest of the paper is organized as follows: An introduction
efficient communication systems for deep-space, telemetry and to SOQPSK is given in Section II. It is followed by Section III,
Unmanned Aerial Vehicle (UAV) links, for example. To the best explaining the proposed architecture with an optimized CPM
of the authors’ knowledge, this is the first SOQPSK modulator part and a precoder, requiring a minimal amount of hardware
architecture and implementation reported in literature. The mod- after its complexity reduction. Section IV contains the results
ulation task itself is divided into a SOQPSK-specific precoding
part, with minimal hardware complexity, as well as an optimized of the proof-of-concept, an FPGA implementation of the
quadrature CPM modulator. With a proof-of-concept FPGA SOQPSK-TG modulator.
implementation, the feasibility of the proposed architecture is
shown together with its close to optimal algorithmic performance. II. SOQPSK M ODULATION
SOQPSK, a special case of binary CPM, is explained in
detail throughout this section. A description of all single index
I. I NTRODUCTION (only one particular modulation index h) CPM schemes is
CPM is a family of highly efficient modulation schemes given by the complex envelope

in terms of the required spectrum and transmission energy. A Es jφ(t)
comprehensive introduction to CPM is given in [1]. Due to s(t) = e , (1)
Ts
the constant envelope property, non-linear amplification and
thus the use of simple and efficient amplifiers in saturation where Es and Ts are symbol energy and symbol duration,
is possible. The ability to smooth phase transitions is the key respectively. Phase φ(t) is a pulse train following equation

enabler to CPM’s excellent spectrum properties. φ(t) = 2πh αi q(t − iTs ), (2)
Many fields of application emerge for this class of waveforms. i
A few highlights thereof are mentioned now. Power and with the time index i ∈ Z, the M -ary data symbols αi and
spectral efficient modulation techniques have been investigated the phase pulse
for deep space satellite communication in [2]. It turns out ⎧
that constant envelope modulations are highly suitable for ⎪
⎪ 0 t<0
⎪
⎨t
the needs of deep space scenarios and SOQPSK, one of the
q(t) = g(τ )dτ 0 ≤ t < LTs , (3)
candidates, convinces with spectral containment and detection ⎪
⎪
⎪0
⎩
performance. 1/2 t ≥ LTs
Many requirements like power efficiency, narrow bandwidth
transmission and low transceiver complexity are also beneficial with the frequency pulse g(t), with low-pass characteristic,
for UAV communication. This becomes obvious in the case and the duration L. Generally, one distinguishes between full
of High Altitude Pseudo-Satellite (HAPS), which is an un- response (L = 1) and partial response (L > 1). Knowing
manned solar powered airplane, flying in the stratosphere with the boundaries of the changing part of q(t), the phase can be
extremely limited resources for payload weight and energy rewritten to
consumption. n
 n−L

Furthermore, telemetry in general is use case of SOQPSK. φ(t) = 2πh αi q(t − iT ) + πh αi (4)
i=n−L+1 i=0
This fact lead to the standardization of a particular SOQPSK
 
 
parameter set in [3], which is elaborated in the next section.
= θ(t) + θn−L . (5)
The vast majority of research focuses on the complexity
reduction and implementation of the receiving part of wireless In this equation, the phase is described by its phase state θn−L
communication systems. Nevertheless, the proof-of-concept of and the time varying filtered transition θ(t). The latter one

978-1-4799-8058-1/15/$31.00 ©2015 IEEE. 790

 0/0 0/0 Q
S3
1/ 1/−
1 1 S1

0/0 0 /1
S2
1/ 1/0
−
1 I
1
−
0/ 0/0 S2 S0
S0
1/0 1 /1

1
0/ 0/−
1
S1
1/0 1/0
i-even i-odd S3

Fig. 2. SOQPSK Trellis and Phase State Mapping

Fig. 1. Time-varying SOQPSK trellis with four states and transition labels
ai /αi .
0.5 Freq. Pulse g(t)
Phase Pulse q(t)
incorporates inter symbol interference effects due to the phase
0.4
pulse in the case where L > 1.
Shaped Offset QPSK (SOQPSK), a highly bandwidth-efficient
Amplitude

constant-envelope modulation, is presented based on [4]. Its 0.3

binary input ai is precoded into a ternary representation αi ,
with M = 3 and the symbols αi ∈ {−1, 0, 1}, which can be 0.2
described by equation
αi = (−1)i+1 (2ai−1 − 1)(ai − ai−2 ). (6) 0.1
These ternary symbols are the input of a conventional CPM
modulator. Simplified and in brief, their effect is the following: 0
αi = 0 lets the phase keep its state and αi = ±1 results in a
−4 −2 0 2 4
phase change of ± π2 . The precoder, described by Equation (6),
is an implementation of the following rules (recited from [5]): Time /T
• In any symbol interval, the ternary αi can only be drawn
Fig. 3. Frequency and Phase Pulse of SOQPSK-TG.
from one the binary sets, either 0, 1 or 0, −1.
• The binary set for αi+1 switches from the set used for
αi , if αi = 0 and it does not switch, when αi = 0. Thus, with the window function
a symbol αi = 1 cannot be followed by αi+1 = −1 and ⎧
⎪ t
vice versa. ⎨1
⎪   0 ≤ | 2T | < T1
1 1 π t t
These rules are essential for the good spectral containment w(t) = 2 + 2 cos T2 ( 2T − T1 ) T1 ≤ | 2T | ≤ T1 + T 2
⎪
⎪
of SOQPSK, as transitions from negative to positive or vice ⎩0 T1 + T2 < | 2Tt
|
versa without a zero in between would result in faster phase (9)
changes and thus in a broader power spectrum. and the parameters T1 = 1.5, T2 = 0.5, ρ = 0.7, B = 1.25
There are multiple different SOQPSK versions, distinguishable ∞
by their particular frequency pulses. The most popular ones are and A is chosen such that gTG (t)dt = 12 . See Figure 3
−∞
the full response SOQPSK-MIL ( [6]), and partial response for a plot of the frequency and phase pulse with this set of
SOQPSK-TG (L = 8), which is described in the Telemetry parameters.
Group Standard [3]. Aiming for an efficient spectrum use, the phase filtered version
SOQPSK-MIL has a rectangular frequency pulse SOQPSK-TG is preferable for the requirements of the use

1
if 0 ≤ t < T cases mentioned in the introduction. For the sake of simplicity,
gMIL (t) = 2T , (7) the abbreviation TG is mostly omitted in the remaining part
0 else of this paper.
whereas SOQPSK-TG uses the raised cosine pulse given by Considering the modulation SOQPSK as the inner code in a
  serially concatenated coded communication system, a trellis-
 
cos πρBt
2T sin πBt based representation is convenient for demodulation and de-
2T
gTG (t) = A w(t) (8)
1 − 4( ρBt
2T )
2 πBt
2T
tection tasks. With the binary state variables ai−1 , ai−2 and

791
 I(t)
CPM Modulator cos(·) ×
a ∈ {0, 1} α ∈ {−1, 0, 1}
cos(2πf0 t)
g(t) 
Precoder φ(t) Local s(t)
Filter +
Oscillator
π
2
− sin(2πf0 t)
sin(·) ×
Q(t)

Fig. 4. SOQPSK Quadrature Modulator Schematic.

i even/odd, eight different combinations are conceivable. This a

usually leads to an eight state trellis representation. Neverthe-
less, the authors of [5] propose a time-varying trellis, with
particular sections for i-even and i-odd, reducing the number
of states to four. This trellis is depicted in Figure 1 with
an ”input bit/output symbol”-label attached to each transition. ≡ 0 −
There exists a one to one mapping between the trellis states
Sk , k ∈ {0, ..., 3} and the phase states in the constellation ±
diagram, which is shown in Figure 2. α
In order to understand the signal flow of the modulator archi-
tecture, an explanation of a quadrature type modulator is given Fig. 5. SOQPSK Precoder Architecture without Multipliers.
now. See Figure 4 for a schematic of a SOQPSK quadrature
modulator with the highlighted CPM part. Its ternary input,
a
coming from the precoder, is filtered by the frequency pulse
Precoder
g(t) and afterwards integrated to obtain the phase φ(t) of
the signal. Inphase and quadrature components are outputs CPM
↑N
of cos(·) and sin(·) computation blocks, respectively. The
remaining part of the modulator schematic shows the principal g(t)
of local oscillator frequency mixing to get the transmission
signal s(t).
+
III. FPGA A RCHITECTURE
An explanation of the reduced complexity SOQPSK-TG CORDIC

architecture is given throughout this section. The complete I Q

modulator consists of two parts, the SOQPSK specific pre-

coder and an optimized CPM quadrature modulator.
A. SOQPSK Precoder
Translating binary inputs to their ternary representation is
the task of the SOQPSK precoder in Equation (6). Among
other things, a straight-forward approach would require two
multiplications to perform the calculation. However, Figure 5
shows the proposed precoder architecture without any multi-
plier. A inverter feed-back loop realizes the alternating sign
(−1)i+1 , allowing the whole part (−1)i+1 (2ai−1 − 1) to be
realized by an XOR-controlled negator. Additionally, it can
be highlighted that all registers, the inverter as well as the
XOR gate are single bit and only the subtraction and the
output negation compute with a bit width of two. In total,
the precoder shows an outstanding implementation capability
with only very few basic blocks.
Fig. 6. SOQPSK Modulator Architecture with Highlighted CPM Modulator
Part.
B. Quadrature CPM Modulator
Computing the baseband quadrature components of a CPM
modulated signal is performed by upsampling, filtering, in-
tegration and finally sin(·) and cos(·) evaluation of the in-
coming symbols. See Figure 6 for an architecture schematic
of the complexity reduced SOQPSK modulator. It includes a
precoder instance from Figure 5, which calculates the ternary
input of the subsequent CPM quadrature modulator. In a first
step, these symbols are upsampled with zeros by a factor N
and then filtered with the frequency pulse g(t). Taking into
account the symmetry of the odd number of filter coefficients,
a folded delay line structure Finite Impulse Response (FIR)

792
 10−1 TABLE I
FPGA R ESOURCE U SAGE R ESULTS

Resource Used (total) Used (percentage)

10−2 Slice LUTs 1078 2.02

Slice Registers 1154 1.08
Bit Error Rate

Slices 346 2.6

10−3
10−4 Simulation
Optimum
Implementation
0 2 4 6 8 10
Eb /N0 /(dB)
Fig. 7. Bit Error Rate Performance of SOQPSK-TG: Optimum, Simulation
and Fixed-Point Implementation.
filter helps to reduce the number of required multiplications
from N L+1 down to N L/2+1. The following integration task
is also a source of large complexity reduction. Therefore, a
simple Multiply and Accumulate (MAC) unit with a ”wrap on
overflow”-adder and zero pre-decimal positions is a hardware-
efficient integrator with an output in the range of [0; 1).
Adjusted to the range [−0.5, 0.5), it is a sufficient input to
the Coordinate Rotation Digital Computer (CORDIC) block
because it can be configured to work with scaled radians phase
inputs. All other values range adjustments in the signal flow
of the modulator, like a matching between the filter output and
the integrator input, are performed solely by fixed bit shifts,
which cost nothing in hardware. For the sake of simplicity,
shifting operations are not shown in Figure 6.
IV. I MPLEMENTATION R ESULTS
As a proof-of-concept, the proposed SOQPSK modulator
architecture has been implemented on the programmable logic
part of a Xilinx Zynq xc7z020-2clg4x4 system on chip.
Synthesis and implementation of the System Generator 2014.4
design have been done with the Vivado 2014.4 tool. In
addition to the precoder word widths, which are described
in Section III-A, the configuration is as follows. The over-
sampling factor is N = 4, resulting in N L/2 + 1 = 17
filter taps. As the proposed modulator is part of a design
using an Analog Devices AD9361 transceiver chip, each of the
quadrature components has a word length of twelve bit. The
15 step CORDIC is configured, accordingly, to have exactly
this output precision for I and Q.
In Table I, the FPGA resource usage of the implemented
SOQPSK modulator is listed. Especially the relative numbers
show that the proposed architecture uses only a minimal
amount of hardware. Additionally, the relatively high percent-
age in the DSPs line reveals the importance of a clever filter
implementation. Paying attention to the coefficient symmetry
LUT as Logic 1046 1.96
LUT Memory 32 0.18
LUT FF Pairs 1204 2.26
DSPs 17 7.72
has helped to drastically reduce the amount of required DSPs.
To show the maintained algorithmic performance, Figure 7
shows a plot of the bit error rate curves of SOQPSK simulation
and hardware implementation, together with the optimum
reference values, which are computed according to [7]:
    
1 Eb Eb
Pe ≈ Q 1.60 +Q 2.58 . (10)
2 N0 N0
The difference between reference and simulation results from
the approximations in the pulse truncation SOQPSK demod-
ulator from [8]. The FPGA implementation has been tested
against the same demodulation model revealing almost iden-
tical performances for both.
V. C ONCLUSION
The energy and power spectrum efficiency demands of mul-
tiple wireless communication scenarios, including telemetry
links and UAV communication systems, can be fulfilled by
the binary CPM modulation scheme SOQPSK. A modulator
hardware architecture is proposed that is tailored and opti-
mized to enable a low-complexity hardware implementation,
which helps to design low size, weight and power transmitters.
The feasibility of the introduced architecture is shown with an
FPGA implementation with minimal resource usage and close
to optimal algorithmic performance.
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