Lab Manuals - Electronics PDF

M. Sc.
Physics Lab Manuals
Electronics Lab (PHY 505)

List of Experiments Page
Numbering
1. Diode Rectifier & Filters 1 (1-10)

2. Zener Diode Shunt Voltage Regulator 11(1-4)
3. Hartley Oscillator 15 (1-4)
4. Colpitt Oscillator 19 (1-4)
5. 555 Timer multivibrators 23 (1-9)
6. Diode Clipping & Clamping Circuit 32 (1-4)
7. Transistor Common Emitter Amplifier 36 (1-3)
8. H - Parameters of Transistor. 39 (1-4)
9. Transistor Multivibrators 43 (1-6)
10. Op Amp Parameters & Application 49 (1-11)

DIODE RECTIFIER & FILTERS
This board is designed to study of diode as half wave/ full wave/bridge
rectifier and filter circuits. The board contains, step down transformer hav-
ing centre tap 100 - 0 - 100V @ 100 mA, four silicone rectifier diodes, one
inductor, two capacitors,RL and 2 meters 300Vdc and 100mAdc.
Half wave rectifier : A diode is device which conducts in one direction
only. It conducts only when its anode is more positive than its cathode. In a
half wave rectifier circuit the diode conducts during positive half cycles only.
The current passes through the load RL and a directional voltage devloped
across it. During negative half cycle of the input it stops conducting and
voltage across the load resistance during this period is zero. In this way a
unidirectional voltage ( signal ) achieved from an alternating voltage ( signal
). The magnitude of this unidirectional voltage is called Vdc and it's theoratical
value equal to, Vm / . As stated earlier that these dc voltages are half wave
rectified which devlope and denoyed alternately in each cycle. Thus an ac
voltage is imposed which is called as ripple voltage. In a half wave rectifier
its ratio is about 1.2, between ac voltage and dc voltage at output.
T   Input
D +
vvv
Pri Sec RL
-  Output
Fig 1. Half wave rectifier and its input / output waveforms.

Diode Rectifier & filter ch - 2
Full wave rectifier : In a full wave rectifier circuit there are two diodes and
a transformer with centre tap in its secondary. It provide out of phase volt-
age to both diodes. Thus each diode conducts successively on its turn in
each half cycle. As both diodes has same configuration thus an directional
voltage devloped across RL, which is equal to 2Vm / . The 2Vm is taken
since both half of input cycle is converted into dc. There is still load current
falls to zero when the cycle crossover. Thus a ripple voltage generated at
output, which has magnitude equal to 0.48 approx, between ac and dc
voltages at output.
T Input
CT D1 - vvv +
Pri
Sec RL Output
D2
Fig 2. Full wave rectifier and its input / output waveforms.
Full wave bridge rectifier : In a full wave bridge rectifier circuit there are
four diodes and a transformer with its single secondary. A pair of diode
conducts successively on its turn in each half cycle producing +ve and -ve
dc. As both pair of diodes has same configuration thus an directional volt-
age devloped across RL, which is equal to (2Vm / Vd. The 2Vm is taken
since both half of input cycle is converted into dc, and Vd (= 0.6V) is taken
because there is one more diode in circuit.There is still load current falls to
zero when the cycle crossover. Thus a ripple voltage generated at output,
which has magnitude equal to 0.48 approx, between ac and dc voltages at
output.
Rectifier with C filter : Also called shunt capacitor filter filter circuit. As
shown below an electrolytic capacitor is connected across the output of
rectifier circuit. The capacitance offers a low reactance to the ripple current
of ac component (at 100Hz in shown fig ). Since the RL is > than the capactive
reactance (Xc) a small ripple current flows in load. The capacitor charges to
peak value of dc = Vm, and than discharges through load. The slope shown
AB depends upon XC of C and value of RL.
Note : The Xc is greater at half wave configuration since ripple freq is 50Hz.
+
T Input
CT D1 - C
vvv
Pri RL A
Sec B Output
D2
Fig 3. Shunt capacitor filter and its input / output waveforms.
Rectifier with L filter : Also called series inductor filter filter circuit. As
shown in fig 4, an inductor is connected between the output of rectifier and
load circuit. The inductance offers a high reactance to the ripple current of
ac component. Since the RL is > than the dc resistance of L, a small loss of
dc voltage obtained across load. The inductive reactance (XL) of L increase
with the frequency better filteration obtained at higher harmonic frequency

( in half wave rectifer it is 50 Hz and in full wave it is 100 Hz ). The output
voltage thus have ripple current of low amplitude of relative frequency. For
dc the dc resistance of L is low thus VL = Vdc ( RL / ( Rchoke + RL )). The
Vr load = Vr ( RL / XL + RL )).
+
T Input
L
CT D1 -
vvv
Pri RL
Sec VL
Output
D2
Fig 4. Series inductor filter and its input / output waveforms.
Rectifier with L-C filter : Also called series inductor shunt capacitor filter
circuit. As shown in fig 5, an inductor is connected between the output of
rectifier and load circuit, with a shunt capacitor across the load. The induct-
ance offers a high reactance to the ripple current of ac component, while
capacitor offers a low reactance to the ripple. Since the RL is >> than the dc
resistance of L, a small loss of dc voltage obtained across load. As the
circuit is similar to series inductor filter with a difference is added C. The
ripple across the load is now Vr load = Vr L ( XC / XL ), where Vr L is the
ripple voltage as before in fig 4 circuit.
Note : In half wave configuration the Vr are greater since the ripple fre-
quency is low i.e. 50 Hz, rather then 100 Hz in full weave.

+
T Input
L
CT D1 - C
vvv
Pri RL
Sec VL
Output
D2
Fig 5. L - C filter and its input / output waveforms.
Rectifier with Pye filter : It is same as L - C filter, where another capacitor
added in the circuit connected across the rectifier output. It is the most
efficient filter circuit, since double the capacitor brings XC lower and a bet-
ter filteration offered by it.
+
T
Input
L
CT D1 - C C
vvv
Pri RL
Sec VL
Output
D2
Fig 6. PYE (  ) filter and its input / output waveforms.
Experiment procedure
a. To study half wave rectifier circuit. ( AC meter is external).
1. Connect the circuit as shown in fig 7. It becomes a half wave rectifier
circuit since only diode D1 is in circuit, note L is short circuited and C open.
2. Switch on the power. Adjust RL for 50mA load current.
3. Measure AC across the transformer secondary. (connect external ac

voltmeter across -ve socket and socket at secondary S1).
4. Note the reading of dc voltage from fitted meter as Vdc. Calculate the
theoratical value and compare it with found value, where theoratical value,
Vdc = {VAC ( rms ) x 2 / }.
5. Connect the AC voltmeter (one lead previously connected with -ve socket)
at the dc output socket fitted at +ve of RL side. Note the AC ripple voltage
as Vr. Calculate ripple factor as,
Ripple factor r = Vr / Vdc.
7. Tabulate all observations.
Input ac Vdc Vrms at dc out r
... volt ... V ... V ....
b. To study full wave ( centre tapped ) rectifier circuit.
1. Connect the circuit as shown in fig 8, this will bring diode D3 in the circuit
and it becomes a full wave rectifier circuit. Note that there is only one more
patch cord is inserted in the previous circuit to convert half wave to full wave.
2. Remaining steps are same as before.
c. The full wave bridge rectifier circuit.
1. Connect the circuit as shown in fig 9. Now the four diodes are in circuit.
2. Remaining steps are same as before.
d. The shunt capacitor filter with full wave rectifier.
1. Connect the circuit as fig 10, it will bring C1 in the circuit. Note there is one
more patch cord is used to convert the full wave rectier circuit with capacitor
filter.
2. Note the introduction of C1 increase the dc voltage since capacitor is
goes to charge for Vm value.
3. Measure the Vdc and Vr across the RL.
4. Made the half wave circuit disconnecting the patch cord between socket
2 and 3. Note the Vdc and Vr across RL.
5. Tabulate the result. Compare the reduction of Vr in full wave ( due to
ripple frequency ).
e. The series inductor filter.
1. Plug out the patch cord connected between L. Disconnect C1 from the
circuit, refer to fig 11.
2. Note Vdc and Vr voltage across the RL.
3. Convert the circuit in half wave as exp d and note Vdc and Vr.
4. Tabulate the result.
f. The L filter.
1. Refer to fig 12.
2. The remaining process is same as before.
g. Pye filter.
1. Connect the circuit as fig 13.
2. Remining procedure as before.
Prepare a table from the results obtained for each experiment done and
write the performance of each configuration.

Table for comparison load current is same adjust by RL
Ripple factor: Capacitor filter Inductor filter L type Pye
Half wave : ...... ...... ........ ......
Full wave : ...... ...... ........ ......
To observe the waveforms upon C.R.O (use 1 : 10 atten probe) connect its
leads across the given RL sockets (across voltmeter) in such way that C.R.O
ground lead with -ve and hot lead with +ve socket. The fig 12,13 circuit is
also reffered as dc power supply.
L
VAC D1 +VE
+ mA -
SW2 Vr
D2 + +
VVV
S1
C1 C2 +
P 0 D4 - -
S2
V
V RL
~ -
VVV
V
SW1 SW3
D3
-VE
Fig 7 : Connection diagram for half wave rectifier circuit. SW2 is closed.
L
VAC D1 +VE
+ mA -
SW2 Vr
D2 + +
VVV
S1
C1 C2 +
P 0 D4 - -
S2
V
V RL
~ -
VVV
V
SW1 SW3
D3
-VE
Fig 8 : Connection diagram for full wave rectifier circuit. SW2 is closed.
L
VAC D1 +VE
+ mA -
SW2 Vr
D2 + +
VVV
S1
C1 C2 +
P 0 D4 - -
S2
V
V RL
~ -
VVV
V
SW1 SW3
D3
-VE
Fig 9 : Connection diagram for full wave bridge rectifier circuit. SW2 is closed.
L
D1 +VE
+ mA -
SW2
Vr
S1 D2 + +
VVV
C1 C2
P 0 D4 - - +
S2
V
V RL
~ -
VVV
V
SW1 SW3
D3
-VE
Fig 10 : Connection diagram for full wave rectifier with C filter circuit. SW1, SW2 is
closed. For half wave, remove patch cord from D3 and S2 of transformer.
L
D1 +VE
+ mA -
SW2
Vr
S1 D2 + +
VVV
C1 C2 +
P 0 D4 - -
S2
V
V RL
~ -
VVV
V
SW1 SW3
D3
-VE
Fig 11 : Connection diagram for full wave rectifier with inductive filter circuit. For half wave,
remove patch cord from D3 and S2 of transformer. SW1,2 and 3 are open.
L
D1 +VE
+ mA -
SW2
Vr
S1 D2 + +
VVV
C1 C2
P 0 D4 - - +
S2
V
V RL
~ -
VVV
V
SW1 SW3
D3
-VE
Fig 11 : Connection diagram for full wave rectifier with L filter circuit. For half wave, re-
move patch cord from D3 and S2 of transformer. SW1,2 are open & SW3 closed.
L
D1 +VE
+ mA -
SW2
Vr
D2 + +
VVV
S1
C1 C2
P 0 D4 - - +
S2
V
V RL
~ -
VVV
V
SW1 SW3
D3
-VE
Fig 12 : Connection diagram for full wave rectifier with pye filter circuit. For half wave,
remove patch cord from D3 and S2 of transformer. SW1,3 are closed & SW2 open.
ZENER DIODE SHUNT VOLTAGE REGULATOR
The zener diodes are specified in term of zener voltage V Z, at some re-
verse current IZ. This is on the linear portion of the characteristics curve
corrosponding to one quarter of maximum reverse current. The zener di-
odes are also rated for this dissipation of power which is a product of VZ and
IZ. Since there is some curvature in reverse characteristics at low value of IZ,
it is specified as knee current IZK, where the zener voltage are not stable.
There is another specification called dynamic impedance, ZZ, which is the
reciprocal of the slope. In ideal zener it should be zero, but in practice there
is finite value occurs which pronounce the change in voltage that will occur
across the diode due to change in current through the diode.
(a) Zener diode as voltage regulator :- The prime function of a zener diode
is to regulate or say stablize the voltage across a given load. The study of its
function as a voltage regulator proceed following steps.
1. Connect the circuit as shown in fig 1.
2. Keep load RL at (MAX) 5k ohms.
3. Decrease the load RL in given steps and note voltage V and current I
(mA). where V is = Vz, and I is the load current.
3. Plot curves between voltage and current, voltage and RL. Fix an operat-
ing point (Q point) in linear region of curve for 10% regulation. From the plot
and calculate regulation percentage as , load reg % = [ (Vz / Vzq) x100]
where Vz, is voltage difference, at minimum - maximum load current on
both side of operating point.

Zener diode shunt voltage regulator - 2.
4. From plot 2 RL v/s Vz, the optimum load value can be selected which
should be confind with operting point.
5. The series resistor can be changed to 300 in place of 200. Avoid to
use 100, since it cause to flow more current in zener, which will heat it if RL
is above a certain value.
V mA
+ - + -
R series = 100 +100
= 200
VVV VVV VVV
100 100 100
K ZD
+ BZX7.5
12V A
dc
VVV
RL
Fig 1 : Connection diagram for zener diode regulator characteristics.
(b) Transistor shunt voltage regulator : The zener diodes are used for low
current applications, otherwise power zeners (which are much costlier) are
used. The output current can furthur raised using transistor in conjunction of
zener diode.
1. Connect the circuit as shown in fig 2.
2. Keep load RL at (MAX) 5k ohms.
3. Decrease the load RL in given steps and note voltage V and current I
(mA). where V is = Vz, and I is the load current.
3. Plot curves between voltage and RL. Observe the output is far more
wider than zener diode alone.
Note : The output is more than zener voltage and are = (Vz + Vbe)
V mA
+ - + -
R series =100
VVV VVV VVV

100 100 100
K ZD
C
+ B BZX5.6
12V A
D139
dc
VVV
V
E RL
VVV
1K
Fig 2 : Connection diagram for transistor shunt regulator characteristics.

Vz
10
Q
Vz
RL 
2
10 3
10 103
Fig 3 : curve RL v/s Vz, for zener diode regulator characteristics.
Vz
10
Vz
IL mA
0 25 50
Fig 4 : curve IL v/s Vz, for zener diode regulator characteristics.

Vz
10
Q
Vz
5
RL 
2
10 3
10 103
Fig 5 : curve RL v/s Vz, for transistor shunt regulator characteristics.

HARTLEY OSCILLATOR
The Hartley oscillator is simplest type of oscillator used in RF applications. in these
oscillators only one capacitor is used across one tapped inductor, where the tap point
of inductor is connected with ground to forms L - C tuned circuit. The amount of
feedback depends upon the coupling ratio L1 : L2. Generally these oscillators are used
in variable frequency applications.
Ciruit description : In fig 1, shows the circuit of given Hartley's oscillator using a
transistor as an amplifier biased through resistance R2 and R4 in base - emitter junc-
tion. Where the collector is connected with the supply through a resistance R3 and L.
The base is also connected to another portion of the coil through a capacitor C3. The
portion of inductor L and C3 forms the positive feedback loop.
When the supply applied to the circuit the current flows in transistor through lower part
of Lin such direction that an opposed current flow across upper portion of L. The
capacitor C get charged to the voltage value appeared across the coil. As reistance of
L is very much smaller for this sharp rise current, the mutual transfer of opposed
current bias Q harder. This leads to saturation of Q, which ceased to accept no more
current. Now C discharges across the lower portion of L and Q1, provide sharp falling
current across upper portion of L in opposite direction as the discharge of C has
reverse polarity.The voltage devloped across C provides regenerative action to sus-
tained oscillations. The falling current across L pulls base of Q in reverse - bias, hence
Hartley oscillator - 2.
leads to cut - off. This prevent to flow of current in the circuit and cycle repeat again.
The charge - discharge rate (frequency of oscillation) depends upon the value of C
and L Smaller the values, higher the cycle hence higher the frequency. The frequency
of oscillation is;
1
fo =
2 LC
where C is equal to dial position.
Object : To verify the condition of oscillation in given Hartley oscillator. To prepare tank
calibration curve between frequency of oscillation and capacity C.
Other apparatus required : A general purpose cathode ray oscilloscope.
1. Connect The circuit as shown in fig 1. Connect CRO across the RF output sockets.
Keep C ( variable capacitor ) in middle. Switch ON the power.
2. Adjust CRO, Y amplitude and its sweep frequency to obtain stable waveforms.
Observe the waveforms appeared upon CRO screen. Vary the C and observe that the
number of cycle ( waveforms ) changes with the value of C.
3. Return C to middle. Reverse the patch cord position, (connect VCC with R1 and tap
of coil with base R2 socket). Note there is no oscillations, because of no positive
feedback occurs.
4. Revert the connections to made oscillation again. Fix knob to maximum value of C
(600 pF), measure its frequency f, from CRO (or use a freq counter). Measure other
frequencies at different value of C.
5. Plot a smooth curve between C and f, known as calibration curve.
R1
100
VVV
VCC L
C3 R2 630uH C1
VVV
9V
.01uF 180K
C VVV
B
Q1 R3
V
C560 470
E
VVV
R4
100
CD
OUTPUT to
CRO
Fig 1 : Connections for Hartley's oscillator.

f
KHz
1000
500
C pF
300 600
Fig 2 : calibration curve for given Hartley's oscillator.

COLPITT OSCILLATOR
The colpitt oscillator is another simplest type of oscillator used in RF applications. in
these oscillators only one coil is used across two capacitors, where the joining point of
capacitors is connected with ground to forms L - C tuned circuit. The amount of feed-
back depends upon the capacitance ratio c1 : c2. Generally these oscillators are used
in fixed or small deviation frequency applications.
Ciruit description : In fig 1, shows the circuit of given colpitt oscillator using a transistor
as an amplifier biased through resistance R2 and R4 in base - emitter junction. Where
the collector is connected with the supply through a resistance,R3, RFC and L. The
base is also connected to another portion of the coil through a capacitor C3. The
portion of capacitor C1 and C3 forms the positive feedback loop. When the supply
applied to the circuit the current flows in transistor through L, in such direction that an
opposed current flow across c1 and c2. The capacitors get charged to the voltage value
appeared across the coil. As reistance of L is very much smaller for this sharp rise
current, the mutual transfer of opposed current bias Q1 harder. This leads to saturation
of Q1, which ceased to accept no more current. Now Cs discharges across the L
provide sharp falling current across L in opposite direction as the discharge of C2 has
reverse polarity.The voltage devloped across C2 provides regenerative action to sus-
tained oscillations. The falling current across L pulls base of Q1 in reverse - bias, hence
leads to cut - off. This prevent to flow of current in the circuit and cycle repeat again.
Colpitt oscillator - 2.
The charge - discharge rate ( frequency of oscillation ) depends upon the value of C1 :
C2 (since L is fixed). Smaller the values, higher the cycle hence higher the frequency.
The frequency of oscillation is;
fo =
2 LC
where C is equal to {(C1.C2) / (C1+C2) }, since both are in series.
Object : To verify the condition of oscillation in given colpitt oscillator. To prepare tank
calibration curve between frequency of oscillation and capacity C.
Other apparatus required : A general purpose cathode ray oscilloscope.
1. Connect The circuit as shown in fig 1. Connect CRO across the RF output sockets.
Keep C ( variable capacitor ) in middle. Switch ON the power.
2. Adjust CRO, Y amplitude and its sweep frequency to obtain stable waveforms.
Observe the waveforms appeared upon CRO screen. Vary the C and observe that the
number of cycle ( waveforms ) changes with the value of C.
3. Return C to middle. plug out the patch cord in 'link' position. Note there is no
oscillations, because of no feedback occurs.
4. connect the connection to made oscillation again. Fix knob to maximum value of C
(300 pF), measure its frequency f, from CRO (or use a freq counter).
Measure other frequencies at different value of C.
5. Plot a smooth curve between C and f, known as calibration curve.
VCC
9V
RFC
R1
100
VVV
LINK C1
L
C3 R2
VVV
630uH
.01uF 180K
R3 C2
470
C VVV
B
C560
V
E
VVV
R4
100
CD
OUTPUT
Fig 1 : Connections for Colpitt's oscillator.

f
KHz
1200
600
C pF
150 300
Fig 2 : calibration curve for given Colpitt's oscillator.

TIMER I.C NE555 MULTIVIBRATORS
Timer I.C is designed to generate accurate and stable R - C defined periods, for use as
monostable and astable pulse generators. The popular timer I.C 555 is a versatile chip which
has many features like operating wide voltage range, can sink or source high currents while
itself consumes very little current, can generate pulse width modulation frequencies and even
can be frequency modulated.
In fig 1, basic block diagram of 555 is shown. It contains two voltage comparators, one flip -
flop, one inverter and two transistors as reset and discharge device. the two voltage compa-
rators is provide a voltage refrence by a resistive chain in such manner that, generates 1/ 3
vcc refrence voltage to lower comparator non - inverting input and 2/ 3 vcc to inverting input of
upper comparator. The outputs of comparators are coupled with a R - S flip - flop which set or
reset by these voltages. The lower comparator is called as trigger comparator and the upper
as threshold comparator. The flip - flop output goes low as soon as the voltage at inverting pin
of trigger comparator crosses the 1/ 3 vcc refrence. The output available from I.C is in in-
verted form thus it goes high. The output of flip - flop remains in this state untill the voltage at
non - inverting input of threshold comparator goes high than 2/ 3 vcc refrence. This reset the
flip - flop and its output Q goes high, whether the available output goes low due to invertion.
The discharge transistor comes into saturation and provide a low ohmic path from pin 7 (
discharge ) to ground. The Q2 work as reset transistor and reset the flip - flop as soon as it is
pulled to ground, ignoring any operation is done by comparators. This simple artitecture of
555 is very useful for many applications. This board is designed to familirize some of these
applications as multivibrators.
a. The monostable operation
The fairly large application of 555 is to use it as monostable multivibrator. In fig 2, where the
555 discharge and threshold pins are tied together and biased to vcc through a resistance R
( as selectable ). A capacitor CT ( selectable ) is grounded from similar point.

IC NE 555 multivibrators - 2.
The trigger input is also pulled to vcc through resistance 10 K, where a pulse arrangement is
made to pull trigger pin towards ground momentarily. The output is connected to LED diode
which indicate the status of output voltage visually. As soon as the key is pressed momentar-
ily an negetive voltage ( pulse ) is apllied to trigger input which set the ic and in turn its output
goes high which is commenced by glow of LED. The capacitor CT start charging via R to-
wards vcc. The ic reverts its state as the voltage across CT just crosses the 2 / 3 vcc refrence
for threshold comparator. The dischrge pin swings towards ground through internal transistor
Q1, which discarges CT and the cycle is complete. The monotime is equal to 1.1 RCT, where
time in seconds if CT in mFD and R in megohms.
b.Timer ic 555 astable operation
In fig 3, a circuit is shown where ic 555 is connected in astable mode. In this circuit the 555
operate in free run mode. Initially the output of 555 is low after power on, means that its
internal Q output is high which discharges the CT and also pull trigger pin to low level. As
described earlier the low trigger set the ic which means its output is high at pin 3. The timing
capacitor CT starts charging through R1 + R towards vcc. As the voltage level at pin 6 ap-
proaches just over than 2/ 3 vcc the ic goes to reset and CT start discharging through R. The
effect of R1 is negliable due to low impedance of dischrge transistor. As soon as the voltage
across CT just drops to 1/ 3 vcc the ic retriggered again and the cycle contineous. There are
two resistances involved in this charge - discharge sequence thus the period of generated
wave is T = t1 + t2 = 0.7 R1 + R ( CT ) + 0.7 R2CT. If the value of R is much greater ( >> 50 )
than R1 than a square wave obtained at output with a time period app = 1.4 R2C corrosponding
to frequency f = 0.72 / CTR2.
c. Timer ic 555 in bistable mode
In fig 4, ic 555 is shown as bistable multivibrator, where the trigger pin is held to vcc via
R1 and threshold pin through R2 towards ground. As described earlier that the ic is set when
the trigger input is kept lower than 1/ 3 vcc refrence and it is reset when threshold input goes
higher than 2/ 3 vcc refrence. This internal function makes the 555 as versatile bistable latch.
Applying negetive going pulse at trigger set the ic and its pin 3 goes high. Similarly applying
positive going pulse at threshold pin reset the ic and its output goes low.
a. Other apparatus required : Stop watch, Sine / square wave generator and CRO.
Object : To study IC 555 as monostable multivibrator.
1. Connect the circuit as shown in fig 2, selecting CT equal to 100 uF and R = 30K. Switch on
the power. Observe the LED status ( in timer off position the LED will not glow ).
2. Momentarily ground socket (EXT TRIG). The LED will change state as soon as ic get
triggered. Note the time from stop watch till ic goes into off position again. Repeat the step
two or three time and note the time. Change the R = 20K and repeat the step. Calculate the
theoratical time and compare the result. The error produced by the large value electrolytic C
having tolrence 20%.
3. Select lower value of C ( .01 mFD ) in place of previous capacitor. Connect CRO at the
output of ic and connect a function generator ( F.G or square wave oscillator ) at trigger input
as shown in dashed lines in fig 2, while remove the LED and pulser key connections.
3. Raise the square wave( 100 HZ ) amplitude till a waveform appears upon the CRO screen.
Trace the waveform appearing upon screen. Connect CRO at input and trace the waveform.
4. Change the frequency of square wave say 200HZ and trace the input waveform. Connect
CRO back with the output of ic 555. Trace the waveform appearing.
5. Observe the waveforms from the input and the output. It is cleared that the monotime of ic
is constant in both input triggering frequencies.

b. Other apparatus required : CRO and frequency counter ( optional ).
Object : To study ic 555 in astable mode.
1. Connct the circuit as shown in fig 3. connect CRO across the output, select C = .01 uF and
R 30K. Switch on the power. Observe the trace and copy it upon the paper. Measure its time
period from the calibrated CRO time / div or with a frequency counter. Note the values of R(s)
and C and evaluate the theoratical value.
2. Change the R value to 20 K. Observe the waveform. Is it slightly asymmetric ? Find out the
period from the trace or by frequency counter.
3. Connect CRO across the C and observe the waveform appearing. Is it exponential tringular
? Plot all waveform one after one in sequence and conclude the result.
c. Object : To study ic 555 as bistable multivibrator.
1. Connect the circuit as shown in fig 4. Connect two loose patch cords one with ground and
other with vcc sockets.
2. Switch on the power. Observe LED, if it is glowing ( the IC is set) determine theic state
either set or reset.
3. If LED glows than momentarily touch loose end of vcc ( +5V) patch cord with the pin 6
( TR ). Observe the LED changes its state and goes off. Touch again grounded lead with
pin 2 ( TR ) The LED comes on. Wait for few time. Observe that the LED is remain lit, which
show the IC output remain in this stable state. Touch grounded lead with pin 2 again and note
it does not affect the stable state.
4. Touch momentarily positive connected ( +5V ) with pin 6 ( TH ) input and observe the effect
at the output. Retouch positive connected lead again observe it does not affect the stable
state. Conclude the result from the experiment.
The IC 555 as sawtooth oscillator
In fig 5, a sawtooth oscillator is shown where, ic 555 acts as an comrator which compare the
voltages at trigger and threshold pins. A capacitor CT get linear chraged via current source
T1, to wards +Vcc. As soon as the voltage across CT approach 2/3 VCC, the IC toggles its
output and internal transistor Q is on. The capacitor CT discharge through it and after 1/
3VCC, trigger input brings IC 555 output high and internal transistor Q cut - off. The CT get
again charge via T1. The output is taken via T2 , which acts as vuffer, thus prevent loading of
output device such as CRO. The charge current is
d. Other apparatus required : CRO .
Object : To study ic 555 as sawtooth generator.
1. Connct the circuit as shown in fig 5. connect CRO across the output as shown in fig , select
CT = 0.1 uF and R 10K. Switch on the power. Observe the trace and copy it upon the paper.
2. Increase R to 20K and observe the time period get increased, due to low charging current
pass through T1.

VCC(8) RST(4)
VVV
5K
TH(6)
R
CV(5)
VVV
5K FLIP
FLOP
S Q
TR(2)
Q
DIS(7)
OUT(3)
VVV
5K
GND(1)
Fig 1. The IC 555 block representation. The number in paranthesis are designated to pin
nos of dip package.
+9V
VVV
VVV
10K 1K 8 4
VCC RST
VVV
R
7
DIS
see
procedure
VVV
3
10K 6 Q
TH
C 555 OUTPUT
B
E T2 2
V
B TR
V
T1 E
LED
C .01uF
VEE CV
1 5
VVV
VVV
EXT
10K
10K CT
TRIG .01uF
see
procedure
F.G
Fig 2. The IC 555, as monostable multivibrator. Thick lines show the connections.
H
INPUT
L
H
OUTPUT
T T
L
Typical plot of monostable input and output waveforms. Note that monotime T has constant width irrespec-
tive to input frequency.
VVV +9V
VVV
10K 1K 8 4
VCC RST
VVV
R
7
DIS
VVV
3
10K 6 Q
TH
C 555 OUTPUT
B TO
E T2 2 CRO
V
B TR
V
T1 E
LED
C .01uF
VEE CV
1 5
VVV
VVV
EXT
10K
10K CT
TRIG .01uF
Fig 3. The IC 555, as astable multivibrator. Thick lines show the connections.
OUTPUT
PIN 3
T
OUTPUT
PIN 2
C charge C discharge
Typical plot of astable output waveforms. Note that varying R effects time T
+9V
VVV
VVV
10K 1K 4
8
VCC RST
VVV
R
7
DIS
RESET
VVV
3
10K 6 Q
TH
C 555 OUTPUT
B
E T2 2
V
B TR
V
T1 SET
E
LED
C .01uF
VEE CV
1 5
VVV
VVV
EXT
10K
10K CT
TRIG .01uF
Fig 4. The IC 555, as bistable multivibrator. Thick lines show the connections.
Dotted lines are temprary connection used to set - reset the output.
+9V
VVV
VVV
10K 1K 8 4
VCC RST
VVV
R
7
DIS
VVV
3
10K 6 Q
TH
C 555 OUTPUT
B
E T2 2
V
B TR
V
T1 E
LED
C .01uF
VEE CV
1 5
VVV
VVV
EXT
10K
10K CT
TRIG .01uF
OUTPUT
TO
CRO
Fig 5. The IC 555, as satooth generator. Thick lines show the connections.
CT charge CT discharge
Typical plot of astable output waveforms. Note that varying R effects time T
DIODE CLIPPING & CLAMPING CIRCUIT
The clamper : Clamping circuit are used to superimpose ac signal on some dc level,
hence called the dc inserter. As shown in fig 1, an ac signal source is coupled with a
capacitor C with diode D1 with shown direction. Applying sinusoidal signal, during 1st
quarter cycle ( /2) diode is forward biased and C starts charging from 0 to Vm in such
direction that plate b is -ve. As input goes from Vm to zero the diode is cut - off since C
has
-ve charge at plate b. If there is an RL included than C discharge through it with rate
CR. For a periodic input has time t >> CR the output is standstill at -ve clamped level Vm
- Vd. Reverse the diode direction will produce +ve clamp level.
The clipper : Clipping circuits are the circuits which are used for waveshaping by
removing a portion of either part of applied wave. The removal of part is called clipping.
The bias level : In clipper circuits the predeteremined part is clipped using diode and
bias voltage which are applied to cut - off diode. In fig 1, such clipper circuits is shown.
In fig 1, +ve bias is applied to the cathode of diode D1 by closing switch S1. The clipper
circuit is in parallel with the output stage. The diode is remain cut - off during -ve half
cycle of input waveform and still cut - off on +ve half to a level ( +Vb + Vd ) where +vb is
the bias level and Vd is the diode forward breakdown voltage.
In similar fig , the diode D2 is again reverse biased with battery -Vb after closing S2 the
input +ve half of waveform is passed to the output but a portion of -ve half is get clipped
by diode conduction which occurs at ( -Vb + Vd ).
In same fig, both diodes are applied with bias voltages +Vb , -Vb by closing S1 - S2.The
diodes D1 and D2 clip their halves which depends upon the level defined before.
Diode clipping & clamping ckt - 2.
Experiment procedure, clipper circuit
Other appararus required : CRO and sine wave oscillator.
1. Connect the sine wave oscillator ( or function generator , sine selected ) with the
signal input of the circuit (fig 1) . Keep supply control to minimum.Connect CRO across
the signal output.
2. Apply input sine wave 1 Khz, to obtain 5 to 6 Vpp signal upon CRO.
3. Introduce diode D1. Observe the trace appearing. Increase Vb voltage and observe
its effect upon the waveform. The introduced Vb level may be found from DVM.
4. Plug off D1 and plug on D2. Repeat step 3, and trace the waveform.
5. Conclude the result.
Experiment procedure, clamper circuit
Other appararus required : CRO and sine wave oscillator.
1. Connect the sine wave oscillator ( or function generator , sine selected ) with the
input of the circuit. Keep both diodes unplug circuit. Connect CRO across the output.
2. Apply input sine wave 1 Khz, to obtain 3 to 5 Vpp signal upon CRO.
3. Plug on D1. Observe the trace appearing. Trace it upon paper. Measure the intro-
duced clamp level (dc) from the CRO screen (The DVM can be used to measure dc).
4. Plug off D1 and connect D2 in circuit. Observe the polarity of restored dc is reverted.
5. Conclude the result.

C uF
DVM
1K + -
VVV
+
D1 D2
SIGNAL SIGNAL
INPUT OUTPUT
0 - 10VDC
SIGNAL CRO
SOURCE Fig 1A. The diode positive clipper circuit with connection.
C uF
DVM
1K + -
VVV
+
D1 D2
SIGNAL SIGNAL
INPUT OUTPUT
0 - 10VDC
SIGNAL CRO
SOURCE Fig 1B. The diode negative clipper circuit with connection.
+Vm +Vm +Vm

+Vp +Vp
+Vb + Vd
0 wt 0 0
-Vb + Vd
-Vp -Vp
-Vm -Vm -Vm
(a) The input wave (b) The +ve clipped (c) The -ve clipped
wave, Vd = 0.6V wave, Vd = 0.6V
C uF
DVM
1K + -
VVV
+
D1 D2
SIGNAL SIGNAL
INPUT OUTPUT
0 - 10VDC
SIGNAL CRO
SOURCE Fig 1C. The dual diode clipper circuit with connection.
C uF
DVM
1K + -
VVV
+
D1 D2
SIGNAL SIGNAL
INPUT OUTPUT
0 - 10VDC
SIGNAL CRO
SOURCE Fig 2. The diode clamping circuit with connection.
Connect D! and D2 alternately.
+Vm
+Vm +Vm
dc
0 wt inserted
0 wt 0 wt
dc
-Vm inserted
-Vm
(d) The double clipped -Vm
wave (e) The -ve clamped wave (f) The +ve clamped wave
TRANSISTOR COMMON EMITTER AMPLIFIER
To amplify a small signal an amplifier is used. In general purpose amplifier circuit
common emitter transistor amplifiers are used. These amplifier circuits has modrate
voltage gain and resonable frequency response. The input - output circuit is capactively
coupled, where emitter is bypassed with a capacitor for virtual earth in view of signal ac
components. The capactive reactance of all capacitors leads to loss of low frequency
response while the interjunction capacitances produce an undesired effect (Miller ef-
fect) upon high frequency response.
This kit is designed to evaluate the amplification factor and frequency response of such
transistor amplifier, with and without terminating RL .
Experimental Procedure
Other apparatus required :AC mVmeter and A.F. generator upto 200 Khz.
Object : To study common emitter single stage transistor amplifier frequency (gain
bandwidth ) response . To find out the voltage gain.
Connect the circuit as in given fig 1.
1.Connect the A.F generator across the input of amplifier as shown in fig 1. Apply an
input signal of sine, 1 Khz, 18 ~20mV measuring the input across the amplifier input as
shown in fig 1, as Vin displayed upon ac millivoltmeter.
2. Measure the input voltage (Vin) at input, and output voltage (Vo) at output. Find out
the voltage gain Av = [ Vo / Vin].
3. Now vary the frequency of generator and note the output voltage varying the fre-
quency of the oscillator to either side from 20Hz to maximum frequency ( > 100Khz ).
Transistor C.E. amplifier - 2.
Care should be taken that input voltage must be constant for each step of increasing /
decreasing frequency at Vin points as shown in fig 1.
4. Plot the bandwidth curves for different terminating resistances. Mark -3dB
corrosponding to 70 % of maximum output voltage points upon both side of the curves.
6. From the experiment the voltage gain Av = .......
The gain bandwith product is ..... dB from f1 to f2.
5. Now disconnect the patch cord (J) to observe the effect of bypass capacitor upon
gain and frequency response. Repeat the experiment steps and find out the effect of
bypass capacitor upon voltage gain and frequency response. The input signal ampli-
tude must be raise to 100 ~ 120mV.
Note : The output may be loaded by terminating it in given RL. While the frequency
response should be plotted without termination.
Table for observations, Vin = 20mVconstant, f1 ...Hz, f2 .... Khz.
Sr Freq Output voltage Gain dB
1 x20Hz ...... ..
2 x200Hz ..... ..
3 x2KHz ..... ..
4 x20KHz ..... ..
The input voltage 20.0 +1mV held constant, with C in emitter ckt. The input voltage
120.0 +1mV held constant, without C in emitter ckt.

Transistor C.E. amplifier - 3.
VCC
+12V
RC
VVV
VVV
3K9 10uF
Vo
VS 1K Vin 1uF

VVV Q1
BC547
V
R2 RE
VVV
VVV
10K 100uF
150
RL
VVV
INPUT 3K
J
A.F Gen AC AC
mVmeter mVmeter
Fig 1. Single stage (CE) amplifier connections for experiment. J OUT for cut off C2
Below : typical frequency response curve for gain - bandwidth product.
dB
40 J
in
30
20
J
out
10
0
101 102 103 104 105 106
Freq Hz
f1 f2
h - PARAMETERS OF TRANSISTOR.
In a two port device, the terminal behaviour is specified by two voltages and two currents.
It can be select two of the four quantities as the independent variables and remaining two
can be expressed as chosen independent variables. In a two port device input voltage can
be written as VIN and input current as IIN. The corrosponding output voltage is VO and output
current as IO. From the statement an equation might be written as;
VI N = h11 II N + h12 VO
IO = h21 II N + h22 VO
The quantities h11, h12 , h21 and h22 are called the hybrid parameters. The
hybrid parameters are defined as ;
a. Input resistance with output short circuited. The value expressed in ohms.
V IN
h11 = VO = 0 ................... 1
IIN
b. Fraction of output voltage at input with input open circuited.

V IN
h12 = IIN = 0 ................... 2
VO
c. Inverted current transfer ratio with output short circuited.
IO
h21 = VO = 0 ................... 3
IIN
d. Output conductance with input open circuited.
IO
h22 = IIN = 0 ................... 4
VO
The hybrid model of a transistor in common - emitter configuration, is shown in fig 1. Where
hie, is the input resistance, hre, is reverse - open - circuit voltage amplification, hfe, is the
short circuit current gain and hoe, is the output conductance.
The h - parameters are measured at a constant temperature, constant voltages, constant
currents and constant frequency. Generally mid frequency of 1 kc is used for these
neasurements. The collector and base are biased with very high impedance circuits.
h - parameter of transistor 2
In fig 2, the circuit used to measure h - parameters of a p n p (GE) transistor is shown. The
base is connected to bias supply through a high Q, L - C tank circuit which has its rejection
frequency close to 1 kc. This arrangement gives very high impedance for ac signal ( very
large when compared to input impedance ) but very low resistance to dc currents. At
output stage when S, is closed the 100 ohm resistance remain in circuit as the power
supply is bypassed with greater value capacitor. The value of 100 ohm is very much less
than the output impedance of the transistor. When S, is opened the ac signals can be fed
across the transformer which has ferrite core to avoid saturation . This arrangement iso-
late the ac source from the circuit.
Object : To measure h - parameters of given PNP transistor AC 125 or eq, in common -
emitter configuration at 1 kc sine.
Other apparatus required : ( If not provided in the board ), AC millivoltmeter and AF oscil-
lator 1 kc sine.
1. Keep both supply controls at minimum. Switch ON the power. Configure fig 2 circuit.
2. Adjust BIAS 0 -9V, power supply at 5~6V dc ( near center). Adjust BIAS 0 - 2V, supply
in such manner that collector current becomes nearly 5 to 6 mA.
3. Wait about 1 minute to thermally stablize the transistor. If collector current get in
creased bring it back to previous value by adjusting the BIAS 0 - 2V, supply.
4. Keep switch S, towards ON, to short circuit the outut. Adjust output of oscillator to about
100 mV at input (measured across socket 2 and gnd) .
5. Measure ac voltage across 10 k ohm resistor as VR ( between 2 and 3).
Between socket 3 and ground as VIN, across 7 and ground as VO.
6. Disconnect audio oscillator from the input . Connect audio oscillator across the pri -
mary of the transformer T. Keep switch S, towards OFF, circuit as fig 3.
7. Adjust 1kc sine wave amplitude to obtain 1V, output across socket 4 and ground.
8. Measure ac voltage across input and ground as V2 ( between 3 and ground ), across
the collector and ground ( 4 and ground ) Vo2, across 7 and ground as V3.
Tabulate the observations,
a.. When signal at input and S was ON so the output short circuited (fig 2).
Vin (3 - gnd) VR (2 - 3) Vo (7 - gnd)
....... mV ......... mV ............ mV
b.. When signal across T, and S was OFF so the input left open (fig 3).
Vo2 (4 - gnd) V2 (3 - gnd) V3 (7 - gnd)
............ V ........... mV ........... mV
Calculate
VIN x R1
hie11 = (typically between 4 - 10K)
VR
VO x R1
hfe21 = (typically between 75 - 200)
VR x R2
V2
hre12 = (typically between 2x10-4 ~ 4x10-3)
Vo2
V3
hoe22 = (typically between 10 - 25Siemen)
Vo2x R2
Where R1 is 10 k ohms and R2 is 100 ohm.
Ib hie CE IC C
B
vvv
hfeIb
vvv
hreV C v hoe
VI N VO
E
Fig 1. Transistor hybrid model as two port in common - emitter configuration.

AC
mV
HI LO
INPUT
1Kc
5 6
INPUT
R1
2 3
10K T
VVV 4 7
S
VVV
C1 L mA R3
1
C S=ON 100
B AC
VVV
R2 125
V
1Kc 1Kc
10K VCC
INPUT E
VBE C2 9V
+
+ 0-2V
Fig 2. Measurement of input, keeping output short.
AC
mV
HI LO
INPUT
1Kc
5 6
INPUT
R1
2 3
10K T
VVV 4 7
S
VVV
C1 L mA R3
1
C S=OFF 100
B AC
VVV
R2 125
V
1Kc 1Kc
10K VCC
INPUT E
VBE C2 9V
+
+ 0-2V
Fig 3. Measurement of output, keeping input open.

TRANSISTOR MULTIVIBRATORS
Transistor circuits can be designed to generate accurate and stable R - C defined periods,
for use as monostable and astable pulse generators. Lets one by operation described .
The astable operation : In fig 1, an astable multivibrator is shown. When power applied due to
some imbalance one transistor either Q1 or Q2 conducts more. Assume Q1 is hard conduct-
ing therefore its collector potential is quite low , and Q2 collector is near by +Vcc level. The
coupling capacitor C2 bring Q1 base - emitter potential to saturate Q1. At this time capaci-
tor C1, start charging, via Q1 (which is saturated) and R2, which brings Q2 base at negative
potential. As C1 gets charging, the base potential of Q2 start rising towards ground level, and
finally to the +ve value equal to Vbe (Q2). This time Q2 start conducting and its collector
potential drops to ground level. The C2 now discharge through Q1, Q2, hence Q1 base volt-
age dropped to negative potential and its collector voltage rise towards +Vcc. Now C2 start
charging via R1 and Q2, and this cycle repeats endless. Since the timing depends upon RC
(R1,R2 & C1,C2), the defined period obtained at any collector of Q1 or Q2 is, equal to T.
T = t1 + t2, and
t1 = 0.694 R1C2
t2 = 0.694 R2 C1
When R1 = R2 and C1 = C2, then
T = t1 + t2 = 2(0.694)RC = 1.39RC.
The monostable operation : In fig 2, a monostable multivibrator is shown. When power ap-
plied Q2 turns on (since there is no ground return resistance at bias) and its collector poten-
tial is low. The capacitor C, furthur pulls it to hard on (saturate). The low potential at its collec-
tor cut - off the Q1 bias and its collector voltage are ar near by +Vcc level.
As soon as a positve going trigger pulse applied at Q1 base, it conducts and its collector
voltage falls. Now capacitor C start charging via Q1 and R, hence base of Q2 is pulled to-
wards negative, which brings its collector at +Vcc level, which saturate Q1.
After elapse of time t1, Q2 base porential start rise to +ve and at Vbe = 0.6V, the Q2 is on,
Transistor multivibrator - 2.
and this cause to bring Vbe of Q1 low to cut - off it. Q1 is than again pulled to saturation by C.
The off state of Q2 is a function of R - C, and it period is defined as monotime T equals to,
T = 0.694RC
The bistable operation : In fig 3, a bistable multivibrator is shown. When power applied due to
some imbalance, either Q1 or Q2 turns on. Assume Q1 is on, and Q2 is off. The collector
potential of Q1 is low and Q2 is high. This brings Q1 hard on (saturate) and Q2 to cut - off.
The diode D1 is reverse - biased (in blocking state) and D2 is in forward - biased (conduct-
ing state). This is one stable state.
As soon as negative going trigger pulse received at trigger input, it appears at collector of
Q2, and at base of Q1 via RB // C2. This pulls base of Q1 at negative potential and Q1 is cut
- off. Thw rising potential at Q1 collector brings base of Q2 at +ve potential and turns Q2 on.
This time D2 is back - biased and D1 is forward - biased. This is another stable state.
Object :- Study of transistor multivibrators.
Other app req : Stop watch, CRO, func gen or square wave oscillator.
Astable multivibrator.
1. Observe the given circuit in fig 1. Connect CRO at the output (Q1 or Q2 collector ) &
ground. If dual trace is available connect 2nd channel with base of same transistor.
2. Observe the trace upon CRO and measure the time period T. Calculate theoratical value
and compare the result*.
3. Change either R or C and observe its effect upon T.
Conc : The astable multivibrators produce ractangular output with a period of T. the T is a
function of R and C.
Monostable multivibrator.
With F.G.
1. Observe the given circuit in fig 2. Connect CRO at the output (Q2 collector ) & ground.
Connect other channel with F.G. Select R any given value and C = .01 uF.
2. Feed square wave 5Vpp input at trigger ( between 200 - 500 Hz).Observe the trace upon
CRO and measure the time period T. Calculate theoratical value and compare the result*.
3. Change R and observe its effect upon T.
4. Vary the frequency of F.G and observe its effect upon T.
With stop watch. Select R = 100K and C = =100uF
1. Disconnect CRO from output and connect it with LED. Disconnect F.G and connect trigger
with pulser.
2. Observe the LED is off. Now push pulser key for brief period. The LED is on (glow).
Simultaneously start stop watch.
3. As soon as LED is off, stop the watch and note the time T. compare it with theoratical
result.
Conc : The monotime T is a function of R and C, and it does not vary with input trigger pulse
or frequency.
Bistable multivibrator.
With F.G.
1. Observe the given circuit in fig 3. Connect CRO at the output (Q2 collector ) & ground.
Connect other channel with F.G.
2. Feed square wave 5Vpp input at trigger ( between 200 - 500 Hz).Observe the trace upon
CRO and measure the time period T. Observe that T is twice of input time.
Conc : The bistable multivibrator acts a divide by two of input signal.
With LED.
1. Connect Q1 and Q2 collectors with given LED,s. Connect trigger input with given pulser
output.
2. Observe the either Q1 or Q2 is on (only one LED wii glow). This is a stable state.
3. Apply a brief push at pulser key.
4. Observe the LEd position is changed. This is other stable poistion.

+VCC 5V ASTABLE MULTIVIBRATOR
RC
VVV
VVV
VVV
VVV
RC R R
1.8K 1.8K
OUTPUT 2 C
W.R.T GND OUTPUT 1
W.R.T GND
C
C C
B B
Q1
V
V
E E
-VE
C C
B B
Q1 Q2
V
E E
FIG 1 : Astable multivibrator .
collector
t1 t2
0
0
base
Astable multivibrator waveform.

MONOSTABLE MULTIVIBRATOR
R2
VVV
VVV
VVV
R1 R
1.8K 1.8K
C
OUTPUT 1 W.R.T
GND
(see procedure)
VVV
R3
10K
D
C C
B B
Q1 Q2
V
V
E R5 VVV E
R4
VVV
10K TRIG
10K
C C
B B
Q1 Q2
V
E E
FIG 2 : Monostable multivibrator .
T
+
collector
0 F.G (trig input).
0
Base
t1
Monostable multivibrator waveform.

BISTABLE MULTIVIBRATOR
TRIG Trigger
D3 C (see procedure)
RC
VVV
VVV
RC
1.8K 1.8K
D1 D2
OUTPUT 2
W.R.T GND OUTPUT 1
W.R.T GND
VVV
VVV
C2 RB RB C3
1n 47K 47K 1n
C C
B B
Q1 Q2
V
V
E E
C C
B B
Q1 Q2
V
E E
FIG 3 : Bistable multivibrator .
collector
0 F.G.
Bistable multivibrator waveform.

OP AMP PARAMETERS & APPLICATION
Other app req : A CRO and AF signal source (audio osc or function gen).
1. Input offset voltage, Vio : -It is the differential input voltage that exsists between two input
terminals of an op - amp without any external input ( no signal applied). The output offset
voltage in either polarity is caused by this input voltage Vio. To measure it fig 1, is applied. In
fig 1, an op - amp with voltage gain of -1000, (Rf / R) is shown. The output voltage may be
either polarity is equal to,
Vo = 103 . Vio. as no signal applied to either input.
So Vio = Vo / 103, can be read directly as mV from a digital voltmeter.
Procedure : Connect the circuit as shown in fig 1. Switch on the power and note the voltage
at output . Read it in mV directly as Vo = Vio.1000. Rf = 100k, R = 100 ohm.
2. Input offset current, Iio, and input bias current Ib :- There is slightly difference in input
bias currents for both input terminals. The difference in both is called as input offset current. In
fig 2, when switch S1 is closed and S2 is opened a voltage devloped across the output is a
function of Ib1( R), where R = 10 megohm. the output voltage is equal to Vo /10 microamp.
When switch S1 is opened and S2 is closed the output voltage is a function of Ib2(RF). where
RF is 10 megohm. Capacitors are connected across R to prevent oscillations.
Vo1 = R. Ib1 as no external signal is applied and it is close loop gain = 1.
and Vo2 = RF. Ib2 as no external signal is applied. Ib1 or Ib2 = Vo / 10 amp.
The input bias current = Ib = Ib1 + Ib2 / 2.
The input offset current Iio = Ib1 - Ib2.
Procedure : Connect the circuit as fig 2, open (off) switch S2, to introduce the 10meg resist-
ance between ground and +in terminal. Read the output voltage directly and calculate,Ib1 as
Vo = Ib1. 10000000, e.g 0.5 volt = 0.05 microamp or 50 nanoamp.

OP AMP PARAMETERS
Other app req : A DMM,CRO and AF signal source (audio osc or function gen).
1. Input offset voltage, Vio : -It is the differential input voltage that exsists between two input
terminals of an op - amp without any external input ( no signal applied). The output offset
voltage in either polarity is caused by this input voltage Vio. To measure it fig 1, is applied. In
fig 1, an op - amp with voltage gain of -1000, (Rf / R) is shown. The output voltage may be
either polarity is equal to,
Vo = 103 . Vio. as no signal applied to either input.
So Vio = Vo / 103, can be read directly as mV from a digital voltmeter.
Procedure : Connect the circuit as shown in fig 1. Switch on the power and note the voltage
at output . Read it in mV directly as Vo = Vio.1000. Rf = 100k, R = 100 ohm.
2. Input offset current, Iio, and input bias current Ib :- There is slightly difference in input
bias currents for both input terminals. The difference in both is called as input offset current. In
fig 2, when switch S1 is closed and S2 is opened a voltage devloped across the output is a
function of Ib1( R), where R = 10 megohm. the output voltage is equal to Vo /10 microamp.
When switch S1 is opened and S2 is closed the output voltage is a function of Ib2(RF). where
RF is 10 megohm. Capacitors are connected across R to prevent oscillations.
Vo1 = R. Ib1 as no external signal is applied and it is close loop gain = 1.
and Vo2 = RF. Ib2 as no external signal is applied. Ib1 or Ib2 = Vo / 10 amp.
The input bias current = Ib = Ib1 + Ib2 / 2.
The input offset current Iio = Ib1 - Ib2.
Procedure : Connect the circuit as fig 2, open (off) switch S2, to introduce the 10meg resist-
ance between ground and +in terminal. Read the output voltage directly and calculate,Ib1 as
Vo = Ib1. 10000000, e.g 0.5 volt = 0.05 microamp or 50 nanoamp.

Op - amp parameter - 2.
3. Input resistance, Rid : -The differential input resistance is the input resistance seen from
the input port of an op - amp. To measure Rid. as shown in In fig 3, both inputs of op - amp is
wired through R = 100K, with DPDTswitche S3 across them. The input signal is applied at
the inverting input. When S3 is on the op - amp has very large gain and output voltage is V1.
When S3 are off the voltage gain changes only by its internal resistance, not by the feedback
and output voltage is = V2.
Output voltage at switch S3 on = V1
Output voltage at switch S3 off = V2
Now Ri1 = [{V2 /( V1 - V2)} (2R)]. where R = R = 100 Kohm each.
Procedure : Connect the circuit as shown in fig 3. Keep S3 on. Keep input signal 30 or40 Hz.
Switch on the power, and adjust input voltage to read 5Vac (approx) at DMM. Note this
voltage as V1. Now S3 is made off. Note the output voltage as V2. Calculate differential input
resistance as given before.
Note : During this experiment use short connecting leads between op - amp inputs and
socket 3 and 4. The op - amp is running at very high gain thus when 100K resistances are
introduced at opening S3 an unstable reading may appear. If necessary adjust oscillator
frequency to lower side very slowly to obtain stable output.
4. Common mode rejection ratio, CMRR : - The CMRR is given by the equation as,
CMRR = ADM / ACM,
where ADM is the differential mode gain and ACM is the common mode gain. Refer to fig 4,
an arrangement is shown to measure the CMRR. In first case the differential voltage gain is
measured at output and gain is find out as Vo / Vin = ADM. In second step the common mode
voltage gain is measured at the output as above and common mode rejection ratio is calcu-
lated.
Procedure : Connect the circuit as shown in fig 4. The amplifier has a voltage gain of 10.
Connect the inverting terminal with oscillator output as shown in fig 4. To measure ADM, put
switch S3 and S4 in off state . Apply an input signal at 100Hz of such amplitude that an
unclipped maximum output voltage obtained. Note the output voltage as Vopp. Note the
input voltage at input node as Vipp. Calculate the voltage gain as Vo / Vi = Calculate the
voltage gain in dB as ADM dB = 20 log10 Vo / Vi.
To measure ACM, keep S4 on. Note the input and output voltage in pp. Calculate the com-
mon mode voltage gain ACM as before. Calculate the common mode rejection ratio as CMRR
= ADM / ACM in dB.
b.Maximum voltage swing :- For this experiment one variable DC voltage source required.
Note the maximum voltage swing in ADM measure mode for AC signal with slightly clipped
pattern ( same as before exp 4 )
Disconnect function generator and connect the input with the dc source and connect voltme-
ter at output in reverse polarity on input voltage polarity. Increase the input voltage and note
the maximum dc voltage output in one direction. Revert the input dc and output meter polarity
and repeat the step for maximum voltage swing in other polarity. Plot it graphically and find
out the saturation region on both side as shown below.
+Vo
DC
AC
+Vin -Vin Max vo swing
-Vo
5. Slew Rate. SR : - The slew rate determines the maximum frequency of operation fmax for
a desired output voltage swing. To measure slew rate circuit shown in fig 5, is used.
Procedure : Other apparatus required , CRO.
Connect the circuit as shown in fig 5. Feed an ac 8Khz, sine wave signal to the input for
saturated output waveform. Trace it upon the paper with the position of the X - Y graticules.
Display the input waveform pattern and trace it upon the paper with X - Y graticules. Place
both waveforms one upon other and find out the period as shown in fig below. Calculate the
SR from the trace as SR = Vopp / T in volt per S,
+Vpp T,uS
inverted
Vopp t uS
-Vpp
6. Quicent current : - The quicent current is the ideal current drawn by op - amp under no
signal and output termination. Fig 6 show the connection where, a milliammeter inservted to
measure quicent current.
Procedure : Other apparatus required , digital mA meter.
Connect the circuit as shown in fig 6. Note the current as IQ1. Now break the loop by plug out
patch cord J. Note the current again as IQ2. The mean of it is the quicent current.
7. Summer : - In given circuit shown in fig 7, the feedback current IF is a function of sums of
input currents I1 + I2 + Ib, since Ib is very small for close loop operation thus the relation
becomes I1 + I2 = IF. The input currents are function of input voltage V1, V2, and resistance
R1, R2 since node ( - input ) exsists virtual zero. Thus the above relation should be written as
, - Vo / RF = V1 / R1 + V2 / R2,
the - sign ahead of Vo indicate inverting action. If the resistances Rf = R1 = R2 = R, than the
output will can be written as
- Vo = Va + Vb ( a summing relation ) .. 1
Procedure :
Connect the circuit as shown in fig 7. Feed The voltage Va and Vb and note output voltage
and its polarity as given in text.
8. Inverting amp : - In given circuit shown in fig 8, the voltage output of an inverting amplifier
is given by relation Vo = - (RF/R1), where RF is feedback resistor and R1 is the total input
resistor.
Procedure :
Connect the circuit as shown in fig 8. Feed The voltage +2V, and note output voltage and its
polarity as given in text. Here RF = 10K , R1 = 5K (since two 10K resistors are in parallel).
Break the jumper J and note the output decrease, here RF = 10K and R1 = 10K.
9. Buffer amp : - In given circuit shown in fig 9, the voltage output of non - inverting amplifier
is given by relation Vo = 1+ (RF/R1), where RF is feedback resistor and R1 is the total input
resistor. Now there is no R1 and RF, so output is 1 (unity) and due to 100% feedback the input
impedance = Rid.
Procedure :
Connect the circuit as shown in fig 9. Feed The voltage +2V, and note output voltage and its
polarity as given in text. Here it is unity gain non - inverting amplifier therefore output has
same polarity as input.

10K AC
VVV 10K mV
+2V +3V
VVV meter
S1
1M
10M
VVV VVV
100K 100K
C VVV
VVV
10K
VCC +12V
S3 VVV
VVV
-
VVV S4
100K 10K 741
VVV +
100 100
SIG VEE
VVV
VVV
VVV
VVV
VVV
IN S2 10M 50
-12V
100
FIG 1 : Measurement of Vio.
DVM
10K
VVV 10K
+2V +3V
VVV
S1
1M
VVV 10M
VVV
100K 100K
C VVV
VVV
10K
VCC +12V
S3 VVV
VVV
-
VVV S4
100K 10K 741
VVV +
100 100
SIG VEE
VVV
VVV
VVV
VVV
VVV
IN S2 10M 50
-12V
100
FIG 2 : Measurement of ib.

DVM
10K
VVV 10K
+2V +3V
VVV
S1
1M
10M
VVV VVV
100K 100K
C VVV
VVV
10K
VVV VCC +12V
S3
VVV
-
VVV S4
100K 10K 741
VVV +
100 100
SIG VEE
VVV
VVV
VVV
VVV
VVV
IN S2 10M 50
-12V
100
FIG 3 : Measurement of Rid.

30Hz sine
(F.G)
10K DVM
VVV 10K
+2V +3V
VVV
S1
1M
10M
VVV VVV
100K 100K
C VVV
VVV
10K
VVV VCC +12V
S3
VVV
-
VVV S4
100K 10K 741
VVV +
100 100
SIG VEE
VVV
VVV
VVV
VVV
VVV
IN S2 10M 50
-12V
100
FIG 4 : Measurement of CMRR.

30Hz sine
(F.G)
mA meter
10K
VVV 10K
+2V +3V
VVV
S1
1M
10M
VVV VVV
100K 100K
C VVV
VVV
10K
VCC +12V
S3 VVV
VVV
-
VVV S4
100K 10K 741
VVV +
100 100
SIG VEE
VVV
VVV
VVV
VVV
VVV
IN S2 10M 50
-12V
100
FIG 5 : Measurement of slew rate.
10K CRO
VVV 10K
+2V +3V
VVV
S1
1M
10M
VVV VVV
100K 100K
C VVV
VVV
10K
VVV VCC +12V
S3
VVV
- J
VVV S4
100K 10K 741
VVV +
100 100
SIG VEE
VVV
VVV
VVV
VVV
VVV
IN S2 10M 50
-12V
100
FIG 5 : Measurement of Q current.

8KHz sine
(F.G)
10K DVM
VVV 10K
+2V +3V
VVV
S1
1M
10M
VVV VVV
100K 100K
C VVV
VVV
10K
VVV VCC +12V
S3
VVV
-
VVV S4
100K 10K 741
VVV +
100 100
SIG VEE
VVV
VVV
VVV
VVV
VVV
IN S2 10M 50
-12V
100
FIG 7 : op - amp summer
10K DVM
VVV 10K
+2V +3V
VVV
S1
1M
10M
VVV VVV
J
100K 100K
C VVV
VVV
10K
VVV VCC +12V
S3
VVV
-
VVV S4
100K 10K 741
VVV +
100 100
SIG VEE
VVV
VVV
VVV
VVV
VVV
IN S2 10M 50
-12V
100
FIG 8 : op - amp inverting amp

10K DVM
VVV 10K
+2V +3V
VVV
S1
1M
10M
VVV VVV
100K 100K
C VVV
VVV
10K
VCC +12V
S3 VVV
VVV
-
VVV S4
100K 10K 741
VVV +
100 100
SIG VEE
VVV
VVV
VVV
VVV
VVV
IN S2 10M 50
-12V
100
FIG 9 : op - amp buffer

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M. Sc.

Physics Lab Manuals

Electronics Lab (PHY 505)

1. Diode Rectifier & Filters 1 (1-10)

This board is designed to study of diode as half wave/ full wave/bridge

inductor, two capacitors,RL and 2 meters 300Vdc and 100mAdc.

Half wave rectifier : A diode is device which conducts in one direction

unidirectional voltage ( signal ) achieved from an alternating voltage ( signal

rectified which devlope and denoyed alternately in each cycle. Thus an ac

voltage is imposed which is called as ripple voltage. In a half wave rectifier

its ratio is about 1.2, between ac voltage and dc voltage at output.

Fig 1. Half wave rectifier and its input / output waveforms.

output, which has magnitude equal to 0.48 approx, between ac and dc

which has magnitude equal to 0.48 approx, between ac and dc voltages at

shown below an electrolytic capacitor is connected across the output of

AB depends upon XC of C and value of RL.

shown in fig 4, an inductor is connected between the output of rectifier and

ac component. Since the RL is > than the dc resistance of L, a small loss of

dc voltage obtained across load. The inductive reactance (XL) of L increase

with the frequency better filteration obtained at higher harmonic frequency

( in half wave rectifer it is 50 Hz and in full wave it is 100 Hz ). The output

dc the dc resistance of L is low thus VL = Vdc ( RL / ( Rchoke + RL )). The

circuit. As shown in fig 5, an inductor is connected between the output of

ance offers a high reactance to the ripple current of ac component, while

resistance of L, a small loss of dc voltage obtained across load. As the

circuit is similar to series inductor filter with a difference is added C. The

ripple across the load is now Vr load = Vr L ( XC / XL ), where Vr L is the

ripple voltage as before in fig 4 circuit.

quency is low i.e. 50 Hz, rather then 100 Hz in full weave.

Fig 5. L - C filter and its input / output waveforms.

Rectifier with Pye filter : It is same as L - C filter, where another capacitor

ter filteration offered by it.

Fig 6. PYE (  ) filter and its input / output waveforms.

a. To study half wave rectifier circuit. ( AC meter is external).

1. Connect the circuit as shown in fig 7. It becomes a half wave rectifier

2. Switch on the power. Adjust RL for 50mA load current.

3. Measure AC across the transformer secondary. (connect external ac

voltmeter across -ve socket and socket at secondary S1).

Vdc = {VAC ( rms ) x 2 / }.

as Vr. Calculate ripple factor as,

Ripple factor r = Vr / Vdc.

7. Tabulate all observations.

Input ac Vdc Vrms at dc out r

... volt ... V ... V ....

b. To study full wave ( centre tapped ) rectifier circuit.

2. Remaining steps are same as before.

c. The full wave bridge rectifier circuit.

2. Remaining steps are same as before.

d. The shunt capacitor filter with full wave rectifier.

2. Note the introduction of C1 increase the dc voltage since capacitor is

goes to charge for Vm value.

3. Measure the Vdc and Vr across the RL.

2 and 3. Note the Vdc and Vr across RL.

5. Tabulate the result. Compare the reduction of Vr in full wave ( due to

e. The series inductor filter.

circuit, refer to fig 11.

2. Note Vdc and Vr voltage across the RL.

4. Tabulate the result.

1. Refer to fig 12.

2. The remaining process is same as before.

1. Connect the circuit as fig 13.

2. Remining procedure as before.

write the performance of each configuration.