Simulation Assignment

Of
VLSI
​(UE18EC254)
Name: Chandan Shankar M
SRN: PES1201801986
Section: D
Semester: 4

1) Realize the 1 bit FA using AOI, Mirror Circuit and TG concept and verify
the truth table and compare the results in terms of delay.
Aim:-
Realize the 1 bit FA using AOI, Mirror Circuit and TG concept and verify the
truth table and compare the results in terms of delay using cool spice tool.

Truth table:-
A B Cin Sum Cou
t

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1
 Conventional CMOS Circuit and its operation:-

Operation:-

We know that sum and carry out expression for full adder are

Cout = AB + ACin + BCin

= AB + Cin (A+B)

Sum = ABCin + AB`Cin` + A`B`Cin+ A`BCin`

 = ABCin + ( A+B+Cin).( A`Cin`+A`B`+A`Cin`)
= ABCin+ (A+B+Cin).(Cout`)
Hence,to realize cmos circuit we require Cout` and Sum` therefore,
Cout’ = [A.B + Cin.(A+B)]’
Sum’=[ ABCin+ (A+B+Cin).(Cout’) ]’
Now by realizing Nmos and Pmos circuits we can get the overall circuit
diagram

Example:- Let A=0 B=0 Cin=1,hence NFET’s with Cin as input is ON and
PFET’s with A and B as input are ON hence at above left corner we will get a
path for Cout` to be drive to Vdd hence Cout` is logic 1 hence Cout is logic 0
And Cout` is given to the sum circuit hence the nmos with Cout` as input
becomes ON and it is in parallel with nmos with input 1 hence it drives Sum`
to logic 0,hence Sum will become logic 1.
The worst case delay for the conventional cmos will be Full sum with 5
transistors.
Simulation waveform for conventional cmos circuit:-
From graph we can calculate delay for full adder using conventional cmos
circuit with input A and output Sum and Cout:-
A-Sum :- t(plh)=1.778us
A-Cout :- t(plh)=2.768us
Proposed circuits and it’s functioning:-

a) AOI concept:-

Circuit diagram:-
Functioning:-
In AOI circuit we are using and,or,not gates to come up with full adder hence
the sum and carry out expressions are modified into respectively as,
Cout = [A.B + Cin.(A+B)]
Sum=[ ABCin+ (A+B+Cin).(Cout’) ],
So that both Cout and Sum in SOP forM.Moreover sum uses cout’ so that we
can design an AOI gate for cout’ and use the output to feed another AOI gate
for sum,hence circuit diagram shows the construction of the two OAOI
networks.
Note,however that in equation for sum we’ll find 4 OR operations which
indicates that the bottom AOI gate will have 4 series connected PFET’s ,this
may induce an unacceptably long delay in adder,
Simulation waveform for Full adder using AOI concept:-
b)​ ​Mirror circuit concept:-
Circuit diagram:-

Functioning:-
The Pull down circuit is same as conventional cmos full adder and in mirror
the pull up and pull down are similar to each other to make layout simpler
hence the circuit is shown above.
Example:- Let A=0 B=0 Cin=1,hence NFET’s with Cin as input is ON and
PFET’s with A and B as input are ON hence at above left we will get a path
for Cout` to be drive to Vdd by A and B hence Cout` is logic 1 hence Cout is
logic 0 and Cout` is given to the sum circuit hence the nmos with Cout` as
input becomes ON and it is in parallel with nmos with input 1 hence it drives
Sum` to logic 0,hence Sum will become logic 1.
The worst case delay for the conventional cmos will be Full sum with 4
transistors one transistor less when compared to conventional circuit.

Simulation waveform for Full adder using Mirror circuit concept:-

From graph we can calculate delay for full adder using conventional cmos
circuit with input A and output Sum and Cout:-
A-Sum :- t(plh)=1.638us
A-Cout :- t(plh)=2.747us
d) ​Transmission Gate circuit:-
a) Schematic and Hierarchical symbols for Cmos inverter and
Transmission Gate:-
b) Circuit diagram using inverter and transmission gate:-
Functioning:-
Full adder is realized using inverter and Transmission gate as shown above,
Transmission gate is the parallel connection of nmos and pmos pass
transistors because nmos is good passer for logic 0 than logic 1 similarly pmos
is good passer for logic 1 than logic 0 hence to get clear output for both
combinations we make use of transmission gate.
We make use of transmission gate and realized full adder.

Simulation waveform for Full adder using Transmission gate concept:-

From graph we can calculate delay for full adder using conventional cmos
circuit with input A and output Sum and Cout:-
A-Sum :- t(plh)=2.069us
A-Cout :- t(plh)=3.042us

Result and it’s analysis:-

The AOI, Mirror circuit and Transmission gate concept of realizing full adder
are simulated using cool spice tool and the waveform is verified for required
truth table.
Comparison with conventional approach:-
a) AOI circuit requires just to give out sum it requires 4 OR operations
hence the dealay is much more than conventional.
b) Mirror circuit has same transistors as that of conventional approach and
hence the layout is simpler and the delay is less compared to
conventional as mentioned above by taking example as well as it is
verified in graph also.
c) Since transmission gate requires less transistors but it has to wait for
inverter output to come at each stage hence the delay increases for that
and it’s more than both approach.
Finally,comparing to dealy mirror has less delay then conventional and then
transmission gate as verified in graph.

Conclusion:-
We came up with different kinds of realization for full adder because to
reduce area,delay as well as power hence we showed four types of approach
including conventional,hence explained with delay and area of the layout.
2) Realize a 2 Input NAND and NOR gate using Clocked CMOS, Pseudo
NMOS and Dynamic logic

Aim:-
Realize a 2 Input NAND gate using Clocked CMOS, Pseudo NMOS and
Dynamic logic using cool spice tool.

Truth table:-
A B Y

0 0 1

0 1 1

1 0 1

1 1 0

Conventional CMOS Circuit and its operation:-

Operation:-

The above circuit shows the schematic for 2 input Nand gate using
Conventional CMOS logic,From the diagram we can see that the pull down
network is in series whereas pull up is in parallel.
Case 1:- when A=0 B=0 in which both the Pmos are on and whereas both
Nmos are off hence the output will drive Vdd(logic 1).
Case 2:- when A=1 B=0 in which input with A in Nmos is on and input with
B in Pmos is on, but Nmos is in series hence single Nmos which is on cannot
drive logic 0 but Pmos is in parallel hence single Pmos which is on is enough
to drive Vdd hence the output is logic 1.
Case 3:- when A=0 B=1 in which input with B in Nmos is on and input with
A in Pmos is on, but Nmos is in series hence single Nmos which is on cannot
drive logic 0 but Pmos is in parallel hence single Pmos which is on is enough
to drive Vdd hence the output is logic 1.
Case 4:- when A=1 B=1 in which both the Nmos are on and whereas both
Pmos are off hence the output will drive ground potential(logic 0).

Simulation waveform for conventional cmos circuit:-

Proposed circuits and it’s functioning:-
a)​ ​ Clocked CMOS logic:-
Circuit diagram:-

Functioning:-
Static Network at Pull Up and Pull Down is realized based on logical function
to be performed and are driven by the inputs.
But, Pull Up and Pull down network is connected to the output through the Tri
state Network.
Case (1) : Φ =1 , Φ’=0
The inputs with Φ and Φ` of nmos and pmos are ON , As a result the PMOS
Pull Up and NMOS Pull down network gets connected to Output and the
Circuit behaves similar to Conventional Static CMOS Circuit.
Based on Inputs either the output is Pulled UP to VDD or Pulled Down to
GND.
Case (2) : Φ =0 , Φ’=1
The inputs with Φ and Φ` of nmos and pmos are OFF , As a result the PMOS
Pull Up and NMOS Pull down network NOT connected to the Output.
As a result , The output is in High Impedance state.
Now, the Cout holds the previous Status ( either VDD / 0 Volts). The Cout
can not hold the charge for Longer time due to charge leakage .

Simulation waveform for clocked cmos circuit:-

Results and it’s analysis:-
The clocked cmos circuit is simulated using cool spice tool and the waveform
is verified.
From graph1 we can see that whenever Φ =1 the output is given w.r.t inputs
but when Φ =0 both pmos and nmos are OFF it has to attain previous status
but due to charge leakage it comes to 0 quickly.
From graph2 we can see clocked cmos 2 input Nand gate has more
discharging time it’s due to the presence of series connected clocking FET’s
automatically lengthens both rise and fall time but here fall time further
increases due to Nmos logic’s are in series.

Comparison of the results with Conventional approach:-

1. It is used to sequence the data from one circuit to other.
2. It requires 2N+2 transistors whereas conventional approach requires
only 2N transistors.
b)​ Pseudo NMOS logic:-
Circuit diagram:-

Functioning:-
Adding a single Pmos transistor to an otherwise Nmos-only circuit produces a
logic family that is called Pseudo-NMOS.
Pull-up device: Pmos is biased active since the grounded gate gives VSGp =
VDD
Pull-down device: Nmos logic array acts as a large switch between the output
f and ground
However, since the pFET is always biased on, VOL can never achieve the
ideal value of 0V.

Simulation waveform for pseudo nmos circuit:-

Results and it’s analysis:-

The pseudo nmos circuit is simulated using cool spice tool and the waveform
is verified.
From the graph we can see that it doesn’t give logic 0 value clearly, otherwise
it is similar to conventional cmos.
Comparison of the results with Conventional approach:-
1. Pseudo nmos requires only (N+1) FET’s whereas Conventional
approach requires 2N FET’s hence layout is simpler and interconnect is
much simpler.
2. It’s difficult to get logic 0 output in pseudo nmos due to pmos is always
biased on.

c) Dynamic logic:-
Circuit diagram:-
Functioning:-

A dynamic logic gate uses clocking and charge storage properties of

MOSFETs to implement logic operations.
The clock provides a synchronized data flow.
Logic is Implemented using an array of NMOS network placed between the
output node and drain of the Mn.
Case(1):- Φ = 0 ; Pre-charge Mode
Pmos is ON and single Nmos is OFF and this establishes a path between VDD
and output Therefore the Cout charges to VDD.
Case(2):- Φ = 1 ; Evaluation Mode
Pmos is OFF and single Nmos is ON and this establishes a path between
output and GND. Therefore the Cout may discharge if input provides NMOS
chain to GND else Output remains in precharged state, and becomes less
potential due to charge sharing.

Simulation waveform for dynamic logic circuit:-

Results and it’s analysis:-

The dynamic logic circuit for 2 input Nand gate is simulated using cool spice
tool and the waveform is verified.
From the graph it is verified when Φ = 1 the output comes when A=1 and B=1
as 0 then afterwards it gives previous state value because one of the or both
the Nmos transistors are OFF and when Φ = 0 the output is always 1 due to
the Pmos is ON always irrespective of input it gives logic 1.

Comparison of the results with Conventional approach:-

1. Dynamic logic circuit requires only (N+2) FET’s whereas

Conventional approach requires 2N FET’s hence layout is simpler and
interconnect is much simpler and may be faster than static cascades.
 2. We cannot cascade dynamic logic as that of conventional due to charge
sharing concept.

Conclusion:-

Conventional approach output of a static logic gate is valid so long as

the input value are valid and the circuit has stabilized,and it requires more
layout area there is no synchronization to overcome these two problems we
go for different schematics to overcome these effects.
In clocked cmos circuit there will be synchronization due to addition of clock
signal but due to that 2 transistors are added hence layout area increases.
In pseudo nmos logic since it requires less transistors and hence layout area
decreases but there is no synchronization due to lack of clock signal.
In dynamic logic circuit these two problem can be overcome due to there is
clock signal and less transistors but there is a drawback of charge leakage and
charge sharing.

Aim:-
Realize a 2 Input NOR gate using Clocked CMOS, Pseudo NMOS and
Dynamic logic using cool spice tool.

Truth table:-
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
Conventional CMOS Circuit and its operation:-
Circuit diagram:-

Operation:-
The above circuit shows the schematic for 2 input Nor gate using
Conventional CMOS logic,From the diagram we can see that the pull down
network is in parallel whereas pull up is in series.
Case 1:- when A=0 B=0 in which both the Pmos are on and whereas both
Nmos are off hence the output will drive Vdd(logic 1).
Case 2:- when A=1 B=0 in which input with A in Nmos is on and input with
B in Pmos is on, but Pmos is in series hence single Pmos which is on cannot
drive logic 1 but Nmos is in parallel hence single PNmos which is on is
enough to drive output to logic 0.
Case 3:- when A=0 B=1 in which input with B in Nmos is on and input with
A in Pmos is on, but Pmos is in series hence single Pmos which is on cannot
drive logic 1 but Nmos is in parallel hence single Nmos which is on is enough
to drive output is logic 0.
Case 4:- when A=1 B=1 in which both the Nmos are on and whereas both
Pmos are off hence the output will drive ground potential(logic 0).

Simulation waveform for conventional cmos circuit:-

Proposed circuits and it’s functioning:-
a) ​Clocked CMOS logic:​-
Circuit diagram:-
Functioning:-

Static Network at Pull Up and Pull Down is realized based on logical function
to be performed and are driven by the inputs.
But, Pull Up and Pull down network is connected to the output through the Tri
state Network.
Case (1) : Φ =1 , Φ’=0
The inputs with Φ and Φ` of nmos and pmos are ON , As a result the PMOS
Pull Up and NMOS Pull down network gets connected to Output and the
Circuit behaves similar to Conventional Static CMOS Circuit.
Based on Inputs either the output is Pulled UP to VDD or Pulled Down to
GND.
Case (2) : Φ =0 , Φ’=1
The inputs with Φ and Φ` of nmos and pmos are OFF , As a result the PMOS
Pull Up and NMOS Pull down network NOT connected to the Output.
As a result , The output is in High Impedance state.
Now, the Cout holds the previous Status ( either VDD / 0 Volts). The Cout
can not hold the charge for Longer time due to charge leakage .

Simulation waveform for conventional cmos circuit:-

Results and it’s analysis:-

The clocked cmos circuit is simulated using cool spice tool and the waveform
is verified.
From graph1 we can see that whenever Φ =1 the output is given w.r.t inputs
but when Φ =0 both pmos and nmos are OFF it has to attain previous status
but due to charge leakage it comes to 0 quickly.
Due to the presence of series connected clocking FET’s automatically
lengthens both rise and fall time but here rise time further increases due to
Pmos logic’s are in series.
Comparison of the results with Conventional approach:-
1. It is used to sequence the data from one circuit to other.
2. It requires 2N+2 transistors whereas conventional approach requires
only 2N transistors.

b) ​Pseudo NMOS logic:-

Circuit diagram:-

Functioning:-
Adding a single Pmos transistor to an otherwise Nmos-only circuit produces a
logic family that is called Pseudo-NMOS.
Pull-up device: Pmos is biased active since the grounded gate gives VSGp =
VDD
Pull-down device: Nmos logic array acts as a large switch between the output
f and ground
However, since the pFET is always biased on, VOL can never achieve the
ideal value of 0V.

Simulation waveform for pseudo nmos circuit:-

Results and it’s analysis:-

The pseudo nmos circuit is simulated using cool spice tool and the waveform
is verified.
From the graph we can see that it doesn’t give logic 0 value clearly and when
it’s input (0,1) or (1,0) it gives a hike but does not goes to 1 because Nmos is
in parallel and at a time Pmos is driving to Vdd and Nmos is driving to zero
hence it gives value around 4.4V otherwise it is similar to conventional cmos.

Comparison of the results with Conventional approach:-

1. Pseudo nmos requires only (N+1) FET’s whereas Conventional

approach requires 2N FET’s hence layout is simpler and interconnect is
much simpler.
2. It’s difficult to get logic 0 output in pseudo nmos due to pmos is always
biased on.
c)​ ​Dynamic logic:-
Circuit diagram:-

Functioning:-
A dynamic logic gate uses clocking and charge storage properties of
MOSFETs to implement logic operations.
The clock provides a synchronized data flow.
Logic is Implemented using an array of NMOS network placed between the
output node and drain of the Mn.
Case(1):- Φ = 0 ; Pre-charge Mode
Pmos is ON and single Nmos is OFF and this establishes a path between VDD
and output Therefore the Cout charges to VDD.
Case(2):- Φ = 1 ; Evaluation Mode
Pmos is OFF and single Nmos is ON and this establishes a path between
output and GND. Therefore the Cout may discharge if input provides NMOS
chain to GND else Output remains in precharged state, and becomes less
potential due to charge sharing.

Simulation waveform for dynamic logic circuit:-

Results and it’s analysis:-

The dynamic logic circuit for 2 input Nor gate is simulated using cool spice
tool and the waveform is verified.
From the graph it is verified when Φ = 1 the output comes whenever one of
the input is 1 as 0 and it gives previous state value for (0,0) because since
Pmos is OFF for Φ = 1 and when Φ = 0 the output is always 1 due to the Pmos
is ON always irrespective of input it gives logic 1.
Comparison of the results with Conventional approach:-
1. Dynamic logic circuit requires only (N+2) FET’s whereas
Conventional approach requires 2N FET’s hence layout is simpler and
interconnect is much simpler and may be faster than static cascades.
2. We cannot cascade dynamic logic as that of conventional due to charge
sharing concept.

Conclusion:-
Conventional approach output of a static logic gate is valid so long as
the input value are valid and the circuit has stabilized,and it requires more
layout area there is no synchronization to overcome these two problems we
go for different schematics to overcome these effects.
In clocked cmos circuit there will be synchronization due to addition of clock
signal but due to that 2 transistors are added hence layout area increases.
In pseudo nmos logic since it requires less transistors and hence layout area
decreases but there is no synchronization due to lack of clock signal.
In dynamic logic circuit these two problem can be overcome due to there is
clock signal and less transistors but there is a drawback of charge leakage and
charge sharing.