Professional Documents
Culture Documents
Laboratory
Experiment – 1
Group No. :- 28
Part – 1 :
All the gates given to us were 14 pin ICs.
VCC is connected to a 5V DC supply and GND is maintained at 0 V.
As mentioned in the lab sheet,
C: CMOS
HC: High speed CMOS
S: Schottky (high-speed)
LS: Low power Schottky,
F: Fast
The Truth tables of different type of gates are:
NOT GATE:
Truth Table:
AND GATE:
OR GATE:
XOR GATE:
NAND GATE:
NOR GATE:
Part - 2:
The given function is Y = A.B + B. ~C + C. ~A
To realise this function 3 AND gates and 2 OR gates have been used.
The Circuit Diagram is given below:
At 7, the connection has become A.B
At 8, the connection has become B.~C
At 9, the connection has become C.~A
Part - 3 :
Aim: To build a XOR gate using NAND gate.
The Truth Table for the Circuit is given below:
Part – 4:
The given Truth table is :
Using ‘Build Circuit’ option in logisim, the following two circuits can be built:
CASE – 1:
Here a, b are the inputs analogous to A and B. x in the circuit diagram indicates S (sum) and y
indicates the Cout(carry over).
In the above given circuits, NAND gates were not used. Hence the NOT, AND and OR gates
have been used in the above given case.
CASE – 2:
In this case, the Truth Table was realised using NAND gates only.
Here a, b are the inputs analogous to A and B. x in the circuit diagram indicates S (sum) and y
indicates the Cout(carry over).
The above two results are from the simulator. The connections given by us in the lab using the
available ICs are as per the diagram below:
A
S
C_out
B
PART – 5 :
Simulation and Implementation of Full Adder.
The pictures given below provides explanation for the required proofs.
Statement -1:
S = A ⊕B ⊕ CIN
Proof:
Statement-2:
COUT = A.B + B.CIN + CIN.A
Proof:
In the above pictures, CIN is referred to as C.
The Circuit Diagram is given below: