Electronic Design Automation

Assignment-1

Name: Chandan Shankar M

SRN: PES1201801986
Date: 27-08-2020
Question:
1) Design a 32-bit adder using basic gates and map them onto standard cells and
LUTs, such that transistor area is minimal. The total area is measured in terms
of transistors in all cases. Total delay is measure in terms of number of
transistor-levels
Here I will compare 32-bit Ripple Carry Adder in terms of area and delay in terms
of transistors for both standard cells and FPGA.
Standard Cells implementation: -
1-bit RCA Implementation

1(a)
32-bit RCA

1(b)

The above diagram 1(a) shows the circuit for 1-bit FA and 1(b) refers to 32-bit RCA using 1-bit
FA blocks.
From fig 1(a) we know that for a 1-bit adder we need
2 XOR, 2 AND, 1 OR gates to implement
Hence for 32-bit adder total number of gates are
XOR – 64
AND – 64
OR – 32

Total number of basic gates = 160 Gates

Area
From the CMOS technology we know the transistor level circuit of the basic gates are as follows
for respective gates used: -

From above we will get to know the number of transistors for AND and XOR gate for OR gate it
is similar to AND gate only Nmos becomes parallel and Pmos becomes series.
AND Gate: - 4T + 2T = 6T
OR Gate: - 4T +2T = 6T
XOR Gate: - 2T + 2T + 2T = 6T

Hence the Total number of Transistors for a 32-bit FA will be 64*6 + 64*6 + 32*6 = 960
Transistors
Delay/Critical path
Worst case delay linear with the number of bits
Td = (N-1) t carry + t sum
Let’s consider B[0] to sum[31] has maximum delay (consider for logic1 just for easy
calculation) in terms of number of Transistors
Therefore, t carry = (3+3+2) =8 for first FA
t carry = (3+3)=6 for remaining FA
t sum = 3+3 = 6
Td = 8+30*6 + 6
Td = 194 Transistors

Qflow implementation to check the result got manually

Verilog code(structural)
module full_adder(A, B, CIN, S, COUT);

input A;input B;input CIN;output S;output COUT;

assign S = A ^ B ^ CIN;

assign COUT = (A & B) | (CIN & (A ^ B));

endmodule

module bit_adder(A, B, C0, S, C32);

input [31:0] A;input [31:0] B;input C0; output [31:0] S;output C32;

wire C1; wire C2; wire C3; wire C4; wire C5; wire C6; wire C7; wire C8; wire C9; wire C10; wire C11;

wire C12; wire C13; wire C14; wire C15; wire C16; wire C17; wire C18; wire C19; wire C20; wire C21;

wire C22; wire C23; wire C24; wire C25; wire C26; wire C27; wire C28; wire C29; wire C30; wire C31;

full_adder fu0 (A[0], B[0], C0, S[0], C1);full_adder fu1 (A[1], B[1], C1, S[1], C2);full_adder fu2 (A[2], B[2], C2, S[2], C3);

full_adder fu3 (A[3], B[3], C3, S[3], C4);full_adder fu4 (A[4], B[4], C4, S[4], C5);full_adder fu5 (A[5], B[5], C5, S[5], C6);

full_adder fu6 (A[6], B[6], C6, S[6], C7);full_adder fu7 (A[7], B[7], C7, S[7], C8);full_adder fu8 (A[8], B[8], C8, S[8], C9);

full_adder fu9 (A[9], B[9], C9, S[9], C10);full_adder fu10 (A[10], B[10], C10, S[10], C11);full_adder fu11 (A[11], B[11], C11, S[11],
C12);

full_adder fu12 (A[12], B[12], C12, S[12], C13);full_adder fu13 (A[13], B[13], C13, S[13], C14);full_adder fu14 (A[14], B[14], C14,
S[14], C15);

full_adder fu15 (A[15], B[15], C15, S[15], C16);full_adder fu16 (A[16], B[16], C16, S[16], C17);full_adder fu17 (A[17], B[17], C17,
S[17], C18);

full_adder fu18 (A[18], B[18], C18, S[18], C19);full_adder fu19 (A[19], B[19], C19, S[19], C20);full_adder fu20 (A[20], B[20], C20,
S[20], C21);

full_adder fu21 (A[21], B[21], C21, S[21], C22);full_adder fu22 (A[22], B[22], C22, S[22], C23);full_adder fu23 (A[23], B[23], C23,
S[23], C24);

full_adder fu24 (A[24], B[24], C24, S[24], C25);full_adder fu25 (A[25], B[25], C25, S[25], C26);full_adder fu26 (A[26], B[26], C26,
S[26], C27);

full_adder fu27 (A[27], B[27], C27, S[27], C28);full_adder fu28 (A[28], B[28], C28, S[28], C29);full_adder fu29 (A[29], B[29], C29,
S[29], C30);

full_adder fu30 (A[30], B[30], C30, S[30], C31);full_adder fu31 (A[31], B[31], C31, S[31], C32);

endmodule
Number of Gates/Cells = 160
NAND = 32*4 = 128
NOT = 32*2 = 64
OAI33 = 32*12 = 384
XNOR = 32*6 = 192
XOR = 32*6 = 192

Total number of Transistors = 960 (same as manual calculation)

Inbuilt Qflow has standard cell library it reduces and make it to 321 Standard Cells.

Area = 3.49 *108 um2 = 3.49 * 10-4 m

Delay = 9863.22 ps = 9.86 ns
Layout Diagram of FA using Standard cells

FPGA: -
1-bit adder can be implemented by 2 LUT with three input’s making 1LUT for sum and 1LUT
for carry implementation as shows.

Similarly this will be implemented for the 32-bit FA

AREA
LUT3 in terms of transistors by taking multiplexer in terms of Transmission Gates.
LUT3 = (48+ 34) = 82
For 32-bit we require 64 LUT3, therefore
Total number of Transistors = 64*82 = 5248
DELAY/Critical Path
Td = (N-1) t carry + t sum
t carry = 3
t sum = 3
Td = 31*3+3
Td = 96 Transistors (by taking only mux into consideration)

Let’s 4:1 mux has this type of pass transistor logic then analyzing same for 8:1 mux the number
of transistors will be

AREA
LUT3 in terms of transistors by taking multiplexer in terms of Pass Transistors.
LUT3 = (48+ 22) = 70
For 32-bit we require 64 LUT3, therefore
Total number of Transistors = 64*70 = 4480

DELAY
Td = (N-1) t carry + t sum

t carry = 3, t sum = 3
Td = 31*3+3
Td = 96 Transistors (by taking only mux into consideration)
Let’s 4:1 mux has this type of pass transistor logic then analyzing same for 8:1 mux the number
of transistors will be

AREA
LUT3 in terms of transistors by taking multiplexer in terms of Pass Transistors.
LUT3 = (48+ 20) = 68
For 32-bit we require 64 LUT3, therefore

Total number of Transistors = 64*68 = 4352

DELAY
Td = (N-1) t carry + t sum

t carry = 3
t sum = 3
Td = 31*3+3

Td = 96 Transistors (by taking only mux into consideration)

FPGA Implementation using Xilinx Vivado:-

Verilog code:-
module full_adder(A, B, CIN, S, COUT);

input A;input B; input CIN;

output S;output COUT;

assign S = A ^ B ^ CIN;

assign COUT = (B & A) | (A & CIN) | (CIN & B);

endmodule
module bit_adder(A, B, C0, S, C32);

input [31:0] A,B;input C0;

output [31:0] S;output C32;

wire C1; wire C2;wire C3;wire C4; wire C5;wire C6; wire C7;wire C8; wire C9; wire C10;wire C11;

wire C12;wire C13;wire C14;wire C15;wire C16;wire C17;wire C18;wire C19;wire C20;wire C21;

wire C22;wire C23;wire C24;wire C25;wire C26;wire C27;wire C28;wire C29;wire C30;wire C31;

full_adder fu0 (A[0], B[0], C0, S[0],C1); full_adder fu1 (A[1], B[1], C1, S[1],C2);

full_adder fu2 (A[2], B[2], C2, S[2],C3);full_adder fu3 (A[3], B[3], C3, S[3],C4);

full_adder fu4 (A[4], B[4], C4, S[4],C5);full_adder fu5 (A[5], B[5], C5, S[5],C6);

full_adder fu6 (A[6], B[6], C6, S[6],C7); full_adder fu7 (A[7], B[7], C7, S[7], C8);

full_adder fu8 (A[8], B[8], C8, S[8], C9);full_adder fu9 (A[9], B[9], C9, S[9], C10);

full_adder fu10 (A[10], B[10], C10, S[10], C11);full_adder fu11 (A[11], B[11], C11, S[11], C12);

full_adder fu12 (A[12], B[12], C12, S[12], C13);full_adder fu13 (A[13], B[13], C13, S[13], C14);

full_adder fu14 (A[14], B[14], C14, S[14], C15);full_adder fu15 (A[15], B[15], C15, S[15], C16);

full_adder fu16 (A[16], B[16], C16, S[16], C17);full_adder fu17 (A[17], B[17], C17, S[17], C18);

full_adder fu18 (A[18], B[18], C18, S[18], C19);full_adder fu19 (A[19], B[19], C19, S[19], C20);

full_adder fu20 (A[20], B[20], C20, S[20], C21);full_adder fu21 (A[21], B[21], C21, S[21], C22);

full_adder fu22 (A[22], B[22], C22, S[22], C23); full_adder fu23 (A[23], B[23], C23, S[23], C24);

full_adder fu24 (A[24], B[24], C24, S[24], C25);full_adder fu25 (A[25], B[25], C25, S[25], C26);

full_adder fu26 (A[26], B[26], C26, S[26], C27);full_adder fu27 (A[27], B[27], C27, S[27], C28);

full_adder fu28 (A[28], B[28], C28, S[28], C29);full_adder fu29 (A[29], B[29], C29, S[29], C30);

full_adder fu30 (A[30], B[30], C30, S[30], C31);full_adder fu31 (A[31], B[31], C31, S[31], C32);

endmodule
Schematic: -

1(a)

1(b)

Figure 1(a) shows the schematic for the 1-bit FA using basic gates and 1(b) is 32-bit
implementation using the same
32-BIT FULL ADDER SCHEMATIC USING LOOKUP TABLE

Total Number of Look up tables given by vivado in report as

Where K is number of input’s to LUT
Transistor count by LUT’s of CMOS Logic (MUX will be taken in terms of transmission gates)
LUT2 = (24+16) = 40
LUT3 = (48+34) = 82
LUT4 = (96+66) = 162
LUT5 = (192+134) = 326
LUT6 = (384+264) = 648
But in this case
LUT3 = 16* 82 = 1312
LUT5 = 32* 326 = 10432
Total of 11744 Transistors are required.
Worst case delay in Transistor count for an LUT based full adder will be 208. (by taking only
mux into consideration)
Using tool why it’s gave more transistor and delay because whatever the code I written will take
only consider on output rather than wire which gives carryout’s and because of that make’s more
LUT’s to make the combination and it optimizes in terms of all combination to give output.