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  • Code FSM Lockup

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    Veadesh
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    This document defines a testbench module (tb) that instantiates a finite state machine module (fsm). The tb module generates a clock signal and resets the fsm. It also dumps the simulation results of the fsm instance to a file. The fsm module contains an always block that updates the current state (State) on each clock edge based on the next state (NextState) value. It defines 4 states - IDLE, LOAD, STORE, WAIT and the next state logic to transition between these states in sequence.

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    Code_FSM_Lockup.txt

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    This document defines a testbench module (tb) that instantiates a finite state machine module (fsm). The tb module generates a clock signal and resets the fsm. It also dumps the simulation results of the fsm instance to a file. The fsm module contains an always block that updates the current state (State) on each clock edge based on the next state (NextState) value. It defines 4 states - IDLE, LOAD, STORE, WAIT and the next state logic to transition between these states in sequence.

    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    7 views1 page

    Code FSM Lockup

    Uploaded by

    Veadesh
    This document defines a testbench module (tb) that instantiates a finite state machine module (fsm). The tb module generates a clock signal and resets the fsm. It also dumps the simulation results of the fsm instance to a file. The fsm module contains an always block that updates the current state (State) on each clock edge based on the next state (NextState) value. It defines 4 states - IDLE, LOAD, STORE, WAIT and the next state logic to transition between these states in sequence.

    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 1

    module tb;

    reg clk,resetN;

    fsm fsm_inst(clk,resetN);

    initial begin
    clk=0;resetN=1;
    #1 resetN=0;
    #3 resetN=1;
    #50 $finish;
    end

    always #5 clk = !clk;

    initial begin
    $dumpfile("dump.vcd");
    $dumpvars(0,tb.fsm_inst);
    end

    endmodule

    module fsm (clock,resetN);


    input clock;

    input resetN;

    enum {IDLE,LOAD,STORE,WAIT} State, NextState;

    always @(posedge clock, negedge resetN)


    if (!resetN)
    State <= IDLE;
    else
    State <= NextState;

    always_comb begin
    // always@(State) begin
    case (State)
    IDLE: NextState = LOAD;
    LOAD: NextState = STORE;
    STORE: NextState = WAIT;
    endcase

    end

    endmodule

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