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Problem:4 (CLO4)
(a) Given the system shown in the Fig:4a, design
a PID controller to satisfy the following
specifications:
(i) settling time Ts2 sec;
(ii) OS 20% overshoot; Fig: 4a
(iii) ess=0 steady-state error for a step input.
[Hints: Desired closed-loop poles are found to be s= -2.3 ±j4.49].
4:(b) Given the system Bode diagrams in Fig:4b. Determine the phase and gain margin and stable or stability
of the system?
[Note: On answer sheet sketch the given bode plot and mark the limits of PH & GM]
Fig: 4b
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