A B C D E

1 1

Compal Confidential
2 2

JAL90 M/B Schematics Document

Intel Penryn Processor with Cantiga + DDRII + ICH9M

3 2008-07-04 3

REV:1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401551 I
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 21, 2008 Sheet 1 of 50
A B C D E
 A B C D E

Compal Confidential
Intel Penryn Processor Thermal Sensor Clock Generator
Fan Control
Model Name : JAL90 page 36
EMC1402-1-ACZL ICS9LPRS387
uPGA-478 Package page 4 page 16
File Name : LA-4201P
(Socket P) page 4,5,6
1 1
FSB
H_A#(3..35) 667/800/1066MHz H_D#(0..63)

HDMI Conn. LCD Conn. CRT Conn.

page 20 page 18 page 19
Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2
Intel Cantiga
LVDS Dual Channel BANK 0, 1, 2, 3 page 14,15

1.8V DDRII 533/667

TMDS LVDS uFCBGA-1329
PCI-Express page 7,8,9,10,11,12,13
Card Reader LS-4201P
16X
JMB385 MXM II VGA/B USB conn x2 Bluetooth CMOS Finger Print
page 26 DMI C-Link
page 17
USB port 0, 2 Conn Camera AES1610
page 30 page 30 page 18 page 30

PCI-Express
2
Intel ICH9-M 3.3V 48MHz USB
2

3.3V 24.576MHz/48Mhz HD Audio

S-ATA
BGA-676
New Card MINI Card x2 LAN(GbE) page 21,22,23,24
Socket WLAN, Robson2 Realtek RTL8111C port 0 port 1
page 30 page 29 page 27 GMCH HDA MDC 1.5 HDA Codec MXM HDA
Conn ALC888S-VC
page 08 page 33 page 34 page 17
SATA HDD CDROM
Conn.
page 25
Conn.
page 25
DOCKING RJ45
page 28
(DVI/LAN/ Audio AMP
CRT/USB/AUDIO) LS-4208P LPC BUS page 35
page 38
3
Media/B Conn. 3
page 32
ENE KB926 Phone Jack x3
RTC CKT. LS-4202P page 35
page 31
page 22 BTN/B Conn.
page 32

LS-4204P
Power On/Off CKT. Touch Pad Int.KBD
PWR/B Conn. page 32 page 32
page 33
page 32

EC I/O Buffer BIOS

DC/DC Interface CKT. LS-4205P page 32 page 32
USB/B Conn.
page 37 USB port 4
page 29
CIR
Power Circuit DC/DC LS-4206P page 33
page 39,40,41,42
4
43,44,45,46
UMA HDMI/B 4

LS-4205P
Security Classification Compal Secret Data Compal Electronics, Inc.
COVER LIGHT Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

Conn THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
page 36 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 2 of 50
A B C D E
 A B C D E

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF
+1.25VS 1.25V switched power rail ON OFF OFF
+1.5V 1.5V power rail for HDA ON ON OFF Board ID / SKU ID Table for AD channel
+1.5VS 1.5V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+1.8V 1.8V power rail for DDR ON ON OFF Ra/Rc/Re 100K +/- 5%
+1.8VS 1.8V switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+2.5VS 2.5V switched power rail ON OFF OFF 0 0 0 V 0 V 0.155 V
+3VALW 3.3V always on power rail ON ON ON* 1 8.2K +/- 5% 0.168 V 0.250 V 0.362 V
+3V 3.3V power rail for SB ON ON X 2 18K +/- 5% 0.375 V 0.503 V 0.621 V
+3V_LAN 3.3V power rail for LAN ON ON X 3 33K +/- 5% 0.634 V 0.819 V 0.945 V
+3VS 3.3V switched power rail ON OFF OFF 4 56K +/- 5% 0.958 V 1.185 V 1.359 V
+5VALW 5V always on power rail ON ON ON* 5 100K +/- 5% 1.372 V 1.650 V 1.838 V
+5VS 5V switched power rail ON OFF OFF 6 200K +/- 5% 1.851 V 2.200 V 2.420 V
+VSB VSB always on power rail ON ON ON* 7 NC 2.433 V 3.300 V 3.300 V
2 2
+RTCVCC RTC power ON ON ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BOARD ID Table BTO Option Table
External PCI Devices Board ID PCB Revision BTO Item BOM Structure
Device IDSEL# REQ#/GNT# Interrupts
0 0.1 JAL90 JAL90@
1 0.2 JAW50/KAW00 JAW50@
2 0.3 UMA GM@
3 1.0 JAL90-UMA JAL90GM@
4 1A JAW50/KAW00
GLPM@
5 Discrete
6 Discrete PM@
7 ALC888VC 888VC@
ALC888VB 888VB@
8111C 8111C@
EC SM Bus1 address EC SM Bus2 address 8102E 8102E@
3
Device Address Device Address
ALC268 268@ 3

Smart Battery 0001 011X b ADI ADT7421 1001 100X b

JAL90/JAW50 ABO@
EEPROM(24C16/02) 1010 000X b
KAW00 EM@
GMT G781-1 1001 101X b
JAL90/JAW50
JAL9050@
KAW00
JAL90-DIS JAL90PM@
JAW50-DIS JAW50PM@
JAW50-UMA JAW50GL@
ICH9M SM Bus address
Device Address BOM Configuration Table
Clock Generator 1101 001Xb Project BOM Configuration
(ICS9LPRS387, SLG8SP556V)
DDR DIMM0 1001 000Xb
JAL90-UMA 431551BOL01:JAL90GM@/JAL9050@/JAL90@/GM@/888VC@/8111C@/ABO@
DDR DIMM2 1001 010Xb
JAL90-Dis 431551BOL02:PM@/JAL90PM@/JAL9050@/JAL90@/GLPM@/888VC@/8111C@/ABO@
JAW50-UMA 431551BOL11:JAW50@/JAW50GL@/JAL9050@/GM@/GLPM@/8111C@/268@/ABO@
JAW50-DIS 431551BOL12:PM@/JAW50@/JAW50PM@/JAL9050@/GLPM@/8111C@/268@/ABO@
4 KAW00 431551BOL31:JAW50@/JAW50GL@/JAL9050@/GM@/GLPM@/8111C@/268@/EM@ 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 3 of 50
A B C D E
 5 4 3 2 1

H_A#[3..35]
7 H_A#[3..35]
H_REQ#[0..4]
7 H_REQ#[0..4]
H_RS#[0..2]
7 H_RS#[0..2]
JCPU1A
H_A#3 J4 H1 H_ADS# 7
A[3]# ADS#

ADDR GROUP_0
H_A#4 L5 E2 H_BNR# 7
H_A#5 A[4]# BNR#
D L4 A[5]# BPRI# G5 H_BPRI# 7 D
H_A#6 K5
H_A#7 A[6]#
M3 A[7]# DEFER# H5 H_DEFER# 7
H_A#8 N2 F21
A[8]# DRDY# H_DRDY# 7
H_A#9 J1 E1
A[9]# DBSY# H_DBSY# 7
H_A#10 N3
H_A#11 A[10]#
P5 A[11]# BR0# F1 H_BR0# 7
H_A#12 P2 A[12]#

CONTROL
H_A#13 L2 D20 H_IERR#
H_A#14 A[13]# IERR#
P4 A[14]# INIT# B3 H_INIT# 22
H_A#15 P1
H_A#16 A[15]#
R1 A[16]# LOCK# H4 H_LOCK# 7
7 H_ADSTB#0 M1 ADSTB[0]#
C1 H_RESET# H_RESET# 7
H_REQ#0 RESET# H_RS#0
K3 REQ[0]# RS[0]# F3
H_REQ#1 H2 F4 H_RS#1
H_REQ#2 REQ[1]# RS[1]# H_RS#2
K2 REQ[2]# RS[2]# G3
H_REQ#3 J3 G2 H_TRDY# 7
H_REQ#4 REQ[3]# TRDY#
L1 REQ[4]#
HIT# G6 H_HIT# 7
H_A#17 Y2 E4
A[17]# HITM# H_HITM# 7
H_A#18 U5
H_A#19 A[18]#
R3 A[19]# BPM[0]# AD4

ADDR GROUP_1
H_A#20 W6 AD3
H_A#21 A[20]# BPM[1]#
U4 A[21]# BPM[2]# AD1
H_A#22 Y5 AC4
A[22]# BPM[3]#
XDP/ITP SIGNALS
H_A#23 U1 AC2
H_A#24 A[23]# PRDY# XDP_BPM#5
R4 A[24]# PREQ# AC1
H_A#25 T5 AC5 XDP_TCK
C H_A#26 A[25]# TCK XDP_TDI C
T3 A[26]# TDI AA6
H_A#27 W2 AB3
H_A#28 A[27]# TDO XDP_TMS
W5 A[28]# TMS AB5
H_A#29 Y4 AB6 XDP_TRST#
H_A#30 A[29]# TRST# XDP_DBRESET#
U2 A[30]# DBR# C20 XDP_DBRESET# 23
H_A#31 V4
H_A#32 A[31]# +1.05VS
W3 A[32]#
H_A#33 AA4 THERMAL
H_A#34 A[33]#
AB2 A[34]#
H_A#35 AA3 D21 H_PROCHOT#
A[35]# PROCHOT# H_THERMDA
7 H_ADSTB#1 V1 ADSTB[1]# THERMDA A24
B25 H_THERMDC XDP_TDI R17 1 2 54.9_0402_1%
THERMDC
22 H_A20M# A6 A20M#
ICH

22 H_FERR# A5 FERR# THERMTRIP# C7 H_THERMTRIP# 8,22 left NC if no ITP

22 H_IGNNE# C4 IGNNE# XDP_TMS R16 1 2 54.9_0402_1% 39Ohm
22 H_STPCLK# D5 STPCLK#
C6 H CLK XDP_BPM#5 R8 1 2 54.9_0402_1%
22 H_INTR LINT0
B4 A22 @
22 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 16
22 H_SMI# A3 SMI# BCLK[1] A21 CLK_CPU_BCLK# 16
M4 H_PROCHOT# R32 2 1 56_0402_5%
RSVD[01]
N5 RSVD[02]
T2 H_IERR# R31 2 1 56_0402_5%
RSVD[03]
V3 RSVD[04]
RESERVED

B2 RSVD[05] Layout Note:

D2 RSVD[06]
D22 H_THERMDA&H_THERMDC Trace / Space = 10 / 10 mil
RSVD[07]
D3 RSVD[08]
B XDP_TRST# R13 54.9_0402_1% B
F6 RSVD[09] 2 1

XDP_TCK R7 1 2 54.9_0402_1%

Penryn
CONN@

+3VS
C95
0.1U_0402_16V4Z
1 2

+1.05VS U8
BSEL2 BSEL1 BSEL0 BCLK H_THERMDA

0 0 0 266 1 VDD SMCLK 8 EC_SMB_CK2 31,32

1

1
R39 C94 2 7
DP SMDATA EC_SMB_DA2 31,32
0 1 0 200 56_0402_5%
2200P_0402_50V7K
@ 3 DN ALERT# 6 1 2 +3VS
2 R541
2

0 1 1 166 4 5 10K_0402_5%
H_THERMDC THERM# GND
2
B
E

H_PROCHOT# 3 1 OCP# 23 EMC1402-1-ACZL-TR_MSOP8

A A
C

Q2
MMBT3904_SOT23-3
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 4 of 50
5 4 3 2 1
 5 4 3 2 1

H_D#[0..63] JCPU1C
H_D#[0..63] 7
+CPU_CORE A7 VCC[001] VCC[068] AB20 +CPU_CORE
JCPU1B A9 AB7
H_D#0 H_D#32 VCC[002] VCC[069]
E22 D[0]# D[32]# Y22 A10 VCC[003] VCC[070] AC7
D H_D#1 F24 AB24 H_D#33 A12 AC9 D
H_D#2 D[1]# D[33]# H_D#34 VCC[004] VCC[071]
E26 D[2]# D[34]# V24 A13 VCC[005] VCC[072] AC12

DATA GRP 0
H_D#3 G22 V26 H_D#35 A15 AC13

DATA GRP 2
H_D#4 D[3]# D[35]# H_D#36 VCC[006] VCC[073]
F23 D[4]# D[36]# V23 A17 VCC[007] VCC[074] AC15
H_D#5 G25 T22 H_D#37 A18 AC17
H_D#6 D[5]# D[37]# H_D#38 VCC[008] VCC[075]
E25 D[6]# D[38]# U25 A20 VCC[009] VCC[076] AC18
H_D#7 E23 U23 H_D#39 B7 AD7
H_D#8 D[7]# D[39]# H_D#40 VCC[010] VCC[077]
K24 D[8]# D[40]# Y25 B9 VCC[011] VCC[078] AD9
H_D#9 G24 W22 H_D#41 B10 AD10
H_D#10 D[9]# D[41]# H_D#42 VCC[012] VCC[079]
J24 D[10]# D[42]# Y23 B12 VCC[013] VCC[080] AD12
H_D#11 J23 W24 H_D#43 B14 AD14
H_D#12 D[11]# D[43]# H_D#44 VCC[014] VCC[081]
H22 D[12]# D[44]# W25 B15 VCC[015] VCC[082] AD15
H_D#13 F26 AA23 H_D#45 B17 AD17
H_D#14 D[13]# D[45]# H_D#46 VCC[016] VCC[083]
K22 D[14]# D[46]# AA24 B18 VCC[017] VCC[084] AD18
H_D#15 H23 AB25 H_D#47 B20 AE9
D[15]# D[47]# VCC[018] VCC[085]
7 H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 7 C9 VCC[019] VCC[086] AE10
7 H_DSTBP#0 H26 DSTBP[0]# DSTBP[2]# AA26 H_DSTBP#2 7 C10 VCC[020] VCC[087] AE12
7 H_DINV#0 H25 DINV[0]# DINV[2]# U22 H_DINV#2 7 C12 VCC[021] VCC[088] AE13
C13 VCC[022] VCC[089] AE15
C15 VCC[023] VCC[090] AE17
H_D#16 N22 AE24 H_D#48 C17 AE18
H_D#17 D[16]# D[48]# H_D#49 VCC[024] VCC[091]
K25 D[17]# D[49]# AD24 C18 VCC[025] VCC[092] AE20
H_D#18 P26 AA21 H_D#50 D9 AF9
H_D#19 D[18]# D[50]# H_D#51 VCC[026] VCC[093]
R23 D[19]# D[51]# AB22 D10 VCC[027] VCC[094] AF10
H_D#20 L23 AB21 H_D#52 D12 AF12
D[20]# D[52]# VCC[028] VCC[095]

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D14 AF14

DATA GRP 3
H_D#22 D[21]# D[53]# H_D#54 VCC[029] VCC[096]
L22 D[22]# D[54]# AD20 D15 VCC[030] VCC[097] AF15
H_D#23 M23 AE22 H_D#55 D17 AF17
H_D#24 D[23]# D[55]# H_D#56 VCC[031] VCC[098]
P25 D[24]# D[56]# AF23 D18 VCC[032] VCC[099] AF18
C H_D#25 P23 AC25 H_D#57 E7 AF20 C
+1.05VS H_D#26 D[25]# D[57]# H_D#58 VCC[033] VCC[100]
P22 D[26]# D[58]# AE21 E9 VCC[034]
H_D#27 T24 AD21 H_D#59 E10 G21 +1.05VS
H_D#28 D[27]# D[59]# H_D#60 VCC[035] VCCP[01]
R24 D[28]# D[60]# AC22 E12 VCC[036] VCCP[02] V6
H_D#29 L25 AD23 H_D#61 E13 J6
D[29]# D[61]# VCC[037] VCCP[03]
2

H_D#30 T25 AF22 H_D#62 E15 K6

R287 H_D#31 D[30]# D[62]# H_D#63 VCC[038] VCCP[04]
N25 D[31]# D[63]# AC23 E17 VCC[039] VCCP[05] M6
1K_0402_1% 7 H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 7 E18 VCC[040] VCCP[06] J21
7 H_DSTBP#1 M26 DSTBP[1]# DSTBP[3]# AF24 H_DSTBP#3 7 E20 VCC[041] VCCP[07] K21
7 H_DINV#1 N24 AC20 H_DINV#3 7 F7 M21
1

DINV[1]# DINV[3]# VCC[042] VCCP[08]

Trace Close CPU < 0.5' GTL_REF0 COMP0 R295 27.4_0402_1%
F9 VCC[043] VCCP[09] N21
AD26 GTLREF COMP[0] R26 1 2 F10 VCC[044] VCCP[10] N6
Width=4 mil , R317 2 1 @ 1K_0402_5% TEST1 C23 MISC U26 COMP1 R291 1 2 54.9_0402_1% F12 R21
R316 TEST1 COMP[1] VCC[045] VCCP[11]
2 1 @ 1K_0402_5% TEST2 D25 AA1 COMP2 R10 1 2 27.4_0402_1% F14 R6
Spacing: 15mil TEST2 COMP[2] VCC[046] VCCP[12]
2

T4 PAD @ TEST3 C24 TEST3 COMP[3] Y1 COMP3 R12 1 2 54.9_0402_1% F15 VCC[047] VCCP[13] T21
(55Ohm) R289 C381 1 2 @ 0.1U_0402_16V4Z TEST4 AF26 F17 T6
TEST4 VCC[048] VCCP[14]
2K_0402_1% T2 PAD @ TEST5 AF1 TEST5 DPRSTP# E5 H_DPRSTP# 8,22,46 F18 VCC[049] VCCP[15] V21
@ TEST6 A26 B5 F20 W21
T13 PAD TEST6 DPSLP# H_DPSLP# 22 VCC[050] VCCP[16]
C3 D24 H_DPWR# 7 AA7 20mils
1

TEST7 DPWR# H_PWRGOOD VCC[051]

16 CPU_BSEL0 B22 BSEL[0] PWRGOOD D6 H_PWRGOOD 22 AA9 VCC[052] VCCA[01] B26 +1.5VS
16 CPU_BSEL1 B23 D7 H_CPUSLP# AA10 C26
BSEL[1] SLP# H_CPUSLP# 7 VCC[053] VCCA[02]
16 CPU_BSEL2 C21 BSEL[2] PSI# AE6 PSI# 46 AA12 VCC[054] 1 1
AA13 AD6 CPU_VID0 46 C85 C93
Penryn VCC[055] VID[0]
AA15 VCC[056] VID[1] AF5 CPU_VID1 46
CONN@ AA17 AE5 CPU_VID2 46 0.01U_0402_16V7K
VCC[057] VID[2] 2 2
TRACE CLOSELY CPU < 0.5' AA18 VCC[058] VID[3] AF4 CPU_VID3 46
AA20 VCC[059] VID[4] AE3 CPU_VID4 46
COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) AB9 AF3 CPU_VID5 46 10U_0805_10V4Z
VCC[060] VID[5]
COMP1, COMP3 layout : Width 4mils and Space 25mils (55Ohms) AC10 VCC[061] VID[6] AE2 CPU_VID6 46
B B
AB10 VCC[062] 1 2 +CPU_CORE
AB12 R286 100_0402_1%
VCC[063] VCCSENSE
AB14 VCC[064] VCCSENSE AF7 VCCSENSE 46
AB15 VCC[065]
AB17 VCC[066]
AB18 AE7 VSSSENSE VSSSENSE 46
VCC[067] VSSSENSE
Penryn 1 2
CONN@ . R285 100_0402_1%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 5 of 50
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE +CPU_CORE
2 x 330uF(6mOhm/2) 2 x 330uF(6mOhm/2)
JCPU1D 1 1 1 1
A4 VSS[001] VSS[082] P6
A8 P21 C378 + C377 + C98 + C7 +
VSS[002] VSS[083] @
A11 VSS[003] VSS[084] P24
A14 R2 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9
VSS[004] VSS[085] 2 2 2 2
A16 VSS[005] VSS[086] R5
A19 VSS[006] VSS[087] R22
D A23 VSS[007] VSS[088] R25 D
AF2 VSS[008] VSS[089] T1 South Side Secondary North Side Secondary
B6 VSS[009] VSS[090] T4
B8 VSS[010] VSS[091] T23
B11 T26 +CPU_CORE
VSS[011] VSS[092]
B13 VSS[012] VSS[093] U3
B16 VSS[013] VSS[094] U6
B19 VSS[014] VSS[095] U21
B21 VSS[015] VSS[096] U24 1 1 1 1 1 1 1 1
B24 V2 C409 C413 C390 C68 C70 C64 C60 C402
VSS[016] VSS[097]
C5 VSS[017] VSS[098] V5
C8 V22 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[018] VSS[099] 2 2 2 2 2 2 2 2
C11 VSS[019] VSS[100] V25
C14 W1 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[020] VSS[101]
C16 VSS[021] VSS[102] W4
C19 VSS[022] VSS[103] W23 (Place these capacitors on South side,Secondary Layer)
C2 VSS[023] VSS[104] W26
C22 VSS[024] VSS[105] Y3
C25 Y6 +CPU_CORE
VSS[025] VSS[106]
D1 VSS[026] VSS[107] Y21
D4 VSS[027] VSS[108] Y24
D8 VSS[028] VSS[109] AA2
D11 VSS[029] VSS[110] AA5 1 1 1 1 1 1 1 1
D13 AA8 C21 C20 C19 C18 C17 C394 C403 C69
VSS[030] VSS[111]
D16 VSS[031] VSS[112] AA11
D19 AA14 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[032] VSS[113] 2 2 2 2 2 2 2 2
D23 VSS[033] VSS[114] AA16
D26 AA19 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[034] VSS[115]
E3 VSS[035] VSS[116] AA22
C E6 AA25 (Place these capacitors on North side,Secondary Layer) C
VSS[036] VSS[117]
E8 VSS[037] VSS[118] AB1
E11 VSS[038] VSS[119] AB4
E14 AB8 +CPU_CORE
VSS[039] VSS[120]
E16 VSS[040] VSS[121] AB11
E19 VSS[041] VSS[122] AB13
E21 VSS[042] VSS[123] AB16
E24 VSS[043] VSS[124] AB19 1 1 1 1 1 1 1 1
F5 AB23 C78 C77 C76 C75 C386 C382 C65 C59
VSS[044] VSS[125]
F8 VSS[045] VSS[126] AB26
F11 AC3 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[046] VSS[127] 2 2 2 2 2 2 2 2
F13 VSS[047] VSS[128] AC6
F16 AC8 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[048] VSS[129]
F19 VSS[049] VSS[130] AC11
F2 VSS[050] VSS[131] AC14 (Place these capacitors on South side,Primary Layer)
F22 VSS[051] VSS[132] AC16
F25 VSS[052] VSS[133] AC19
G4 AC21 +CPU_CORE
VSS[053] VSS[134]
G1 VSS[054] VSS[135] AC24
G23 VSS[055] VSS[136] AD2
G26 VSS[056] VSS[137] AD5
H3 VSS[057] VSS[138] AD8 1 1 1 1 1 1 1 1
H6 AD11 C395 C391 C384 C385 C410 C383 C411 C412
VSS[058] VSS[139]
H21 VSS[059] VSS[140] AD13
H24 AD16 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[060] VSS[141] 2 2 2 2 2 2 2 2
J2 VSS[061] VSS[142] AD19
J5 AD22 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[062] VSS[143]
J22 VSS[063] VSS[144] AD25
B
J25 VSS[064] VSS[145] AE1 (Place these capacitors on North side,Primary Layer) B
K1 VSS[065] VSS[146] AE4
K4 VSS[066] VSS[147] AE8
K23 VSS[067] VSS[148] AE11
K26 VSS[068] VSS[149] AE14 +CPU-CORE C,uF ESR, mohm ESL,nH
L3 AE16
L6
VSS[069] VSS[150]
AE19 Decoupling
VSS[070] VSS[151]
L21 VSS[071] VSS[152] AE23 SPCAP,Polymer 4X330uF 6m ohm/4 1.8nH/6
L24 VSS[072] VSS[153] AE26
M2 VSS[073] VSS[154] A2 32X22uF 3m ohm/32 0.6nH/32
M5 VSS[074] VSS[155] AF6 MLCC 0805 X5R
M22 VSS[075] VSS[156] AF8 32X10uF 3m ohm/32 0.6nH/32
M25 VSS[076] VSS[157] AF11
N1 VSS[077] VSS[158] AF13
N4 VSS[078] VSS[159] AF16
N23 VSS[079] VSS[160] AF19
N26 VSS[080] VSS[161] AF21
P3 A25 +1.05VS
VSS[081] VSS[162]
VSS[163] AF25
Penryn 1
CONN@ . 1 1 1 1 1 1
+ C73 C30 C16 C13 C31 C29 C61

330U_D2E_2.5VM_R15 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

2 2 2 2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 6 of 50
5 4 3 2 1
 5 4 3 2 1

H_A#[3..35] 4
5 H_D#[0..63] U31A
A14 H_A#3
H_D#0 H_A#_3 H_A#4
F2 H_D#_0 H_A#_4 C15
H_D#1 G8 F16 H_A#5
H_D#2 H_D#_1 H_A#_5 H_A#6
F8 H_D#_2 H_A#_6 H13
H_D#3 E6 C18 H_A#7
H_D#4 H_D#_3 H_A#_7 H_A#8
G2 H_D#_4 H_A#_8 M16
D H_D#5 H6 J13 H_A#9 D
H_D#6 H_D#_5 H_A#_9 H_A#10
H2 H_D#_6 H_A#_10 P16
H_D#7 F6 R16 H_A#11
H_D#8 H_D#_7 H_A#_11 H_A#12
D4 H_D#_8 H_A#_12 N17
H_D#9 H3 M13 H_A#13
H_D#10 H_D#_9 H_A#_13 H_A#14
M9 H_D#_10 H_A#_14 E17
H_D#11 M11 P17 H_A#15
H_D#12 H_D#_11 H_A#_15 H_A#16
J1 H_D#_12 H_A#_16 F17
H_D#13 J2 G20 H_A#17
H_D#14 H_D#_13 H_A#_17 H_A#18
N12 H_D#_14 H_A#_18 B19
H_D#15 J6 J16 H_A#19
H_D#16 H_D#_15 H_A#_19 H_A#20
P2 H_D#_16 H_A#_20 E20
H_D#17 L2 H16 H_A#21
H_D#18 H_D#_17 H_A#_21 H_A#22
R2 H_D#_18 H_A#_22 J20
H_D#19 N9 L17 H_A#23
H_D#20 H_D#_19 H_A#_23 H_A#24
L6 H_D#_20 H_A#_24 A17
H_D#21 M5 B17 H_A#25
+1.05VS H_D#22 H_D#_21 H_A#_25 H_A#26
J3 H_D#_22 H_A#_26 L16
H_D#23 N2 C21 H_A#27
H_D#24 H_D#_23 H_A#_27 H_A#28
R1 H_D#_24 H_A#_28 J17
1

H_D#25 N5 H20 H_A#29

R69 H_D#26 H_D#_25 H_A#_29 H_A#30
N6 H_D#_26 H_A#_30 B18
H_D#27 P13 K17 H_A#31
221_0402_1% H_D#28 H_D#_27 H_A#_31 H_A#32
N8 H_D#_28 H_A#_32 B20
H_D#29 L7 F21 H_A#33
2

H_SWING H_D#30 H_D#_29 H_A#_33 H_A#34

N10 H_D#_30 H_A#_34 K21
H_D#31 M3 L20 H_A#35
H_D#32 H_D#_31 H_A#_35
width=10mil Y3 H_D#_32
2

1 H_D#33 AD14 H12 H_ADS#

H_D#_33 H_ADS# H_ADS# 4
C R68 C155 H_D#34 Y6 B16 H_ADSTB#0 C
H_D#_34 H_ADSTB#_0 H_ADSTB#0 4
H_D#35 Y10 G17 H_ADSTB#1
H_D#_35 H_ADSTB#_1 H_ADSTB#1 4
100_0402_1% 0.1U_0402_16V4Z H_D#36 Y12 A9 H_BNR#
2 H_D#_36 H_BNR# H_BNR# 4

HOST
H_D#37 Y14 F11 H_BPRI#
H_BPRI# 4
1

H_D#38 H_D#_37 H_BPRI# H_BR0#

Y7 H_D#_38 H_BREQ# G12 H_BR0# 4
H_D#39 W2 E9 H_DEFER#
H_D#_39 H_DEFER# H_DEFER# 4
H_D#40 AA8 B10 H_DBSY#
H_D#_40 H_DBSY# H_DBSY# 4
H_D#41 Y9 AH7 CLK_MCH_BCLK
H_D#_41 HPLL_CLK CLK_MCH_BCLK 16
H_RCOMP H_D#42 AA13 AH6 CLK_MCH_BCLK#
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# 16
H_D#43 AA9 J11 H_DPWR#
H_D#_43 H_DPWR# H_DPWR# 5
width=10mil H_D#44 AA11 F9 H_DRDY#
H_D#_44 H_DRDY# H_DRDY# 4
1

H_D#45 AD11 H9 H_HIT#

H_D#_45 H_HIT# H_HIT# 4
R334 H_D#46 AD10 E12 H_HITM#
H_D#_46 H_HITM# H_HITM# 4
H_D#47 AD13 H11 H_LOCK#
H_D#_47 H_LOCK# H_LOCK# 4
24.9_0402_1% H_D#48 AE12 C9 H_TRDY#
H_D#_48 H_TRDY# H_TRDY# 4
H_D#49 AE9
2

H_D#50 H_D#_49
AA2 H_D#_50
H_D#51 AD8
H_D#52 H_D#_51
AA3 H_D#_52
H_D#53 AD3 J8 H_DINV#0
H_D#54 H_D#_53 H_DINV#_0 H_DINV#1 H_DINV#0 5
AD7 H_D#_54 H_DINV#_1 L3 H_DINV#1 5
H_D#55 AE14 Y13 H_DINV#2
H_D#56 H_D#_55 H_DINV#_2 H_DINV#3 H_DINV#2 5
AF3 H_D#_56 H_DINV#_3 Y1 H_DINV#3 5
H_D#57 AC1
H_D#58 H_D#_57 H_DSTBN#0
AE3 H_D#_58 H_DSTBN#_0 L10 H_DSTBN#0 5
H_D#59 AC3 M7 H_DSTBN#1
H_D#60 H_D#_59 H_DSTBN#_1 H_DSTBN#2 H_DSTBN#1 5
AE11 H_D#_60 H_DSTBN#_2 AA5 H_DSTBN#2 5
H_D#61 AE8 AE6 H_DSTBN#3
H_D#62 H_D#_61 H_DSTBN#_3 H_DSTBN#3 5
AG2 H_D#_62
B H_D#63 H_DSTBP#0 B
AD6 H_D#_63 H_DSTBP#_0 L9 H_DSTBP#0 5
M8 H_DSTBP#1
H_DSTBP#_1 H_DSTBP#2 H_DSTBP#1 5
H_DSTBP#_2 AA6 H_DSTBP#2 5
H_SWING C5 AE5 H_DSTBP#3
H_RCOMP H_SWING H_DSTBP#_3 H_DSTBP#3 5
E3 H_RCOMP H_REQ#[0..4] 4
+1.05VS B15 H_REQ#0
H_REQ#_0 H_REQ#1
H_REQ#_1 K13
F13 H_REQ#2
H_REQ#_2
2

B13 H_REQ#3
R77 H_RESET# H_REQ#_3 H_REQ#4
4 H_RESET# C12 H_CPURST# H_REQ#_4 B14
H_CPUSLP# E11
5 H_CPUSLP# H_CPUSLP# H_RS#[0..2] 4
1K_0402_1% B6 H_RS#0
H_RS#_0 H_RS#1
F12
1

H_AVREF H_RS#_1 H_RS#2

width:spacing=10mil:20mil (<0.5") A11 H_AVREF H_RS#_2 C8
B11 H_DVREF
1

1
R74 C161 CANTIGA ES_FCBGA1329
@ JAL90GM@
2K_0402_1% 0.1U_0402_16V4Z
2
2

within 100mil to Ball A9,B9

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 7 of 50
5 4 3 2 1
 5 4 3 2 1

U31B +1.8V

M36 RSVD1 SA_CK_0 AP24 DDRA_CLK0 14

1
N36 RSVD2 SA_CK_1 AT21 DDRA_CLK1 14
R33 AV24 R392
RSVD3 SB_CK_0 DDRB_CLK0 15
T33 AU20

COMPENSATION
RSVD4 SB_CK_1 DDRB_CLK1 15
AH9 1K_0402_1%
RSVD5
AH10 AR24 DDRA_CLK0# 14

2
RSVD6 SA_CK#_0 SM_RCOMP_VOH
AH12 RSVD7 SA_CK#_1 AR21 DDRA_CLK1# 14
AH13 RSVD8 SB_CK#_0 AU24 DDRB_CLK0# 15
K12 RSVD9 SB_CK#_1 AV20 DDRB_CLK1# 15 1 1

1
AL34 C491 C492
RSVD10 R390
AK34 RSVD11 SA_CKE_0 BC28 DDRA_CKE0 14
AN35 AY28 2.2U_0603_6.3V6K 0.01U_0402_16V7K
D RSVD12 SA_CKE_1 DDRA_CKE1 14 2 2 D
AM35 AY36 SM_DRAMRST# would be 3.01K_0402_1%
RSVD13 SB_CKE_0 DDRB_CKE0 15
T24 BB36 DDRB_CKE1 15 needed for DDR3 only

2
RSVD14 SB_CKE_1
All RSVD balls on GMCH should be left No
Connect. SA_CS#_0 BA17 DDRA_SCS0# 14
AY16 SM_RCOMP_VOL
SA_CS#_1 DDRA_SCS1# 14
B31 RSVD15 SB_CS#_0 AV16 DDRB_SCS0# 15 For Cantiga 80 Ohm

1
B2 RSVD16 SB_CS#_1 AR13 DDRB_SCS1# 15 1 1

DDR CLK/ CONTROL/

M1 R389 C483 C482
RSVD17

RSVD
SA_ODT_0 BD17 DDRA_ODT0 14
AY17 1K_0402_1% 2.2U_0603_6.3V6K 0.01U_0402_16V7K
SA_ODT_1 DDRA_ODT1 14 2 2
AY21 BF15 DDRB_ODT0 15

2
RSVD20 SB_ODT_O +1.8V +1.8V
SB_ODT_1 AY13 DDRB_ODT1 15
BG22 SMRCOMP R386 1 2 80.6_0402_1%
SM_RCOMP

2
BG23 BH21 SMRCOMP# R383 1 2 80.6_0402_1%
RSVD22 SM_RCOMP# R146
BF23 RSVD23
BH18 BF28 SM_RCOMP_VOH 1K_0402_1%
RSVD24 SM_RCOMP_VOH SM_RCOMP_VOL
BF18 RSVD25 SM_RCOMP_VOL BH28 @
20mil CLK_DREF_96M R483 1 2PM@ 0_0402_5%

1
AV42 SM_VREF 1 2 +DIMM_VREF CLK_DREF_96M# R482 1 2PM@ 0_0402_5%
SM_VREF SM_PWROK R125 1
SM_PWROK AR36 2 0_0402_5% R147

2
BF17 SM_REXT R375 1 2 499_0402_1% 1 0_0402_5%
SM_REXT C212 R145 CLK_DREF_SSC R481 1
SM_DRAMRST# BC36 2PM@ 0_0402_5%
1K_0402_1% CLK_DREF_SSC# R480 1 2PM@ 0_0402_5%
0.1U_0402_16V4Z @
CLK_DREF_96M 2
B38 CLK_DREF_96M 16

1
DPLL_REF_CLK CLK_DREF_96M#
DPLL_REF_CLK# A38 CLK_DREF_96M# 16
CLK_DREF_SSC
DPLL_REF_SSCLK E41
F41 CLK_DREF_SSC#
CLK_DREF_SSC 16 as close as possible to the related balls
DPLL_REF_SSCLK# CLK_DREF_SSC# 16

CLK
F43 CLK_MCH_3GPLL
PEG_CLK CLK_MCH_3GPLL 16
E43 CLK_MCH_3GPLL#
C PEG_CLK# CLK_MCH_3GPLL# 16
Strap Pin Table C

011 = FSB667
AE41 DMI_ITX_MRX_N0 CFG[2:0] 010 = FSB800
DMI_RXN_0 DMI_ITX_MRX_N0 23
AE37 DMI_ITX_MRX_N1 000 = FSB1067
DMI_RXN_1 DMI_ITX_MRX_N1 23
AE47 DMI_ITX_MRX_N2
DMI_RXN_2 DMI_ITX_MRX_N2 23
AH39 DMI_ITX_MRX_N3 0 = DMI x 2
DMI_RXN_3 DMI_ITX_MRX_N3 23
DMI_ITX_MRX_P0
CFG5 1 = DMI x 4 * (Default)
DMI_RXP_0 AE40 DMI_ITX_MRX_P0 23
MCH_CLKSEL0 T25 AE38 DMI_ITX_MRX_P1 0 = iTPM Host Interface is enabled
16 MCH_CLKSEL0 CFG_0 DMI_RXP_1 DMI_ITX_MRX_P1 23
MCH_CLKSEL1 DMI_ITX_MRX_P2 CFG6
16 MCH_CLKSEL1
MCH_CLKSEL2
R25
P25
CFG_1 DMI_RXP_2 AE48
AH40 DMI_ITX_MRX_P3
DMI_ITX_MRX_P2 23 1 = iTPM Host Interface is Disabled *(Default)
16 MCH_CLKSEL2 CFG_2 DMI_RXP_3 DMI_ITX_MRX_P3 23
P20 CFG_3 DMI_MTX_IRX_N0
0 = Lane Reversal Enable
P24 CFG_4 DMI_TXN_0 AE35 DMI_MTX_IRX_N0 23 CFG9 1 = Normal Operation * (Default)
2 PM_EXTTS#0 MCH_CFG_5 DMI_MTX_IRX_N1

DMI
+3VS 1 C25 CFG_5 DMI_TXN_1 AE43 DMI_MTX_IRX_N1 23
R118 10K_0402_5% MCH_CFG_6 N24 AE46 DMI_MTX_IRX_N2 0 = PCIe Loopback Enable
CFG_6 DMI_TXN_2 DMI_MTX_IRX_N2 23
1 2 PM_EXTTS#1 MCH_CFG_7 M24 CFG_7 CFG DMI_TXN_3 AH42 DMI_MTX_IRX_N3
DMI_MTX_IRX_N3 23 CFG10 1 = Disable * (Default)
R121 10K_0402_5% E21 CFG_8
1 2 MCH_CLKREQ# MCH_CFG_9 C23 CFG_9 DMI_TXP_0 AD35 DMI_MTX_IRX_P0
DMI_MTX_IRX_P0 23 00 = Reserved
R126 10K_0402_5% MCH_CFG_10 C24 AE44 DMI_MTX_IRX_P1 CFG[13:12] 01 = XOR Mode Enabled
CFG_10 DMI_TXP_1 DMI_MTX_IRX_P1 23
N21 AF46 DMI_MTX_IRX_P2 10 = All Z Mode Enabled
CFG_11 DMI_TXP_2 DMI_MTX_IRX_P2 23
Use VGATE for GMCH_PWROK MCH_CFG_12 P21 AH43 DMI_MTX_IRX_P3 11 = Normal Operation * (Default)
CFG_12 DMI_TXP_3 DMI_MTX_IRX_P3 23
MCH_CFG_13 T21
VGATE GMCH_PWROK CFG_13
16,23,46 VGATE 1
R143
2
@ 0_0402_5%
R20 CFG_14 0 = Dynamic ODT Disabled
ICH_PWROK 1 MCH_CFG_16
M20 CFG_15 CFG16 1 = Dynamic ODT Enabled * (Default)
23 ICH_PWROK 2 L21 CFG_16
R144 0_0402_5% 0 = Normal Operation
H21 CFG_17 *(Default)
P29 CFG19 1 = DMI Lane Reversal Enable
GRAPHICS VID

MCH_CFG_19 CFG_18
R28 CFG_19
MCH_CFG_20 T28 B33 0 = Only PCIE or SDVO is operational.
CFG_20 GFX_VID_0
GFX_VID_1 B32 CFG20 * (Default)
G33
B GFX_VID_2
F33 (PCIE/SDVO select) 1 = PCIE/SDVO are operating simu. B
R82 PM_SYNC#_R GFX_VID_3
23 PM_SYNC# 1 2 0_0402_5% R29 PM_SYNC# GFX_VID_4 E33
R73 2 0_0402_5% PM_DPRSTP#_R 0 = No SDVO Card Present
5,22,46 H_DPRSTP# 1
PM_EXTTS#0
B7 PM_DPRSTP# * (Default)
14 PM_EXTTS#0 N33 PM_EXT_TS#_0 SDVO_CTRLDATA 1 = SDVO Card Present
PM

15 PM_EXTTS#1 PM_EXTTS#1 P32

GMCH_PWROK PM_EXT_TS#_1
AT40 PWROK GFX_VR_EN C34 0 = LFP Disable * (Default)
21,23,26,27,31 PLT_RST# R75 1 2 100_0402_5% MCH_RSTIN# AT11 RSTIN# L_DDC_DATA 1 = LFP Card Present; PCIE disable
R85 1 2 0_0402_5% THERMTRIP#_R T20 +1.05VS
4,22 H_THERMTRIP# THERMTRIP#
R80 0_0402_5% DPRSLPVR_R 0 = Digital DisplayPort Disable
23,46 PM_DPRSLPVR 1 2 R32 DPRSLPVR * (Default)
1 = Digital DisplayPort Device Present
DDPC_CTRLDATA

2
BG48 AH37 R128
NC_1 CL_CLK CL_CLK0 23
BF48 AH36 1K_0402_1%
NC_2 CL_DATA CL_DATA0 23
ME

BD48 AN36 ICH_PWROK

NC_3 CL_PWROK MCH_CFG_5
BC48 AJ35 CL_RST#0 23 2 1

1
NC_4 CL_RST# CL_VREF R110 @ 2.21K_0402_1%
BH47 NC_5 CL_VREF AH34
BG47 MCH_CFG_6 2 1
NC_6

2
BE47 R86 @ 4.02K_0402_1%
NC_7 C198 1 R129 MCH_CFG_7
BH46 NC_8 DDPC_CTRLCLK N28 2 1
NC

BF46 M28 511_0402_1% R92 @ 2.21K_0402_1%

NC_9 DDPC_CTRLDATA SDVO_SCLK MCH_CFG_9
BG45 NC_10 SDVO_CTRLCLK G36 SDVO_SCLK 17 2 1
+3VS BH44 E36 SDVO_SDATA 0.1U_0402_16V4Z R103 @ 2.21K_0402_1%
SDVO_SDATA 17

1
NC_11 SDVO_CTRLDATA MCH_CLKREQ# 2 MCH_CFG_10
BH43 NC_12 CLKREQ# K36 MCH_CLKREQ# 16 2 1
MISC

BH6 H36 MCH_ICH_SYNC# 23 R98 @ 2.21K_0402_1%

NC_13 ICH_SYNC#
1

+3VS BH5 MCH_CFG_12 2 1

R210 NC_14 R89 @ 2.21K_0402_1%
BG4 NC_15
1K_0402_5% BH3 B12 MCH_TSATN# MCH_CFG_13 2 1
NC_16 TSATN#
1

+1.05VS BF3 R90 @ 2.21K_0402_1%

R202 NC_17 MCH_CFG_16
BH2 2 1
2

1K_0402_5% NC_18 R88 @ 2.21K_0402_1%

MCH_TSATN_EC# 31 BG2 NC_19
1

BE2 B28 HDA_BITCLK_MCH HDA_BITCLK_MCH 22

NC_20 HDA_BCLK
1

R371 C BG1 B30 HDA_RST_MCH# HDA_RST_MCH# 22

2

A 54.9_0402_1% Q21 NC_21 HDA_RST# HDA_SDIN2_MCH A

2 BF1 NC_22 HDA_SDI B29 1 2 HDA_SDIN2 22
B HDA_SDOUT_MCH MCH_CFG_19
R366 MMBT3904_SOT23-3 BD1 NC_23 HDA_SDO C29 HDA_SDOUT_MCH 22 R102 33_0402_5% 2 1 +3VS
1

C E BC1 A28 HDA_SYNC_MCH JAL90GM@ R96 @ 4.02K_0402_1%

HDA

HDA_SYNC_MCH 22
2

MCH_TSATN# Q18 NC_24 HDA_SYNC MCH_CFG_20

1 2 2 F1 NC_25 2 1
B MMBT3904_SOT23-3 A47 Notice: Please check HDA power rail to select HDA controller. R95 @ 4.02K_0402_1%
330_0402_5% E NC_26
3

CANTIGA ES_FCBGA1329
JAL90GM@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401551 I
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 21, 2008 Sheet 8 of 50
5 4 3 2 1
 5 4 3 2 1

DDRA_SDQ[0..63] DDRB_SDQ[0..63]
14 DDRA_SDQ[0..63] 15 DDRB_SDQ[0..63]
DDRA_SDM[0..7] DDRB_SDM[0..7]
14 DDRA_SDM[0..7] 15 DDRB_SDM[0..7]

D DDRA_SMA[0..14] DDRB_SMA[0..14] D
14 DDRA_SMA[0..14] 15 DDRB_SMA[0..14]

U31D U31E
DDRA_SDQ0 AJ38 BD21 DDRB_SDQ0 AK47 BC16
SA_DQ_0 SA_BS_0 DDRA_SBS0# 14 SB_DQ_0 SB_BS_0 DDRB_SBS0# 15
DDRA_SDQ1 AJ41 BG18 DDRB_SDQ1 AH46 BB17
SA_DQ_1 SA_BS_1 DDRA_SBS1# 14 SB_DQ_1 SB_BS_1 DDRB_SBS1# 15
DDRA_SDQ2 AN38 AT25 DDRB_SDQ2 AP47 BB33
SA_DQ_2 SA_BS_2 DDRA_SBS2# 14 SB_DQ_2 SB_BS_2 DDRB_SBS2# 15
DDRA_SDQ3 AM38 DDRB_SDQ3 AP46
DDRA_SDQ4 SA_DQ_3 DDRB_SDQ4 SB_DQ_3
AJ36 SA_DQ_4 SA_RAS# BB20 DDRA_SRAS# 14 AJ46 SB_DQ_4
DDRA_SDQ5 AJ40 BD20 DDRB_SDQ5 AJ48 AU17
SA_DQ_5 SA_CAS# DDRA_SCAS# 14 SB_DQ_5 SB_RAS# DDRB_SRAS# 15
DDRA_SDQ6 AM44 AY20 DDRB_SDQ6 AM48 BG16
SA_DQ_6 SA_WE# DDRA_SWE# 14 SB_DQ_6 SB_CAS# DDRB_SCAS# 15
DDRA_SDQ7 AM42 DDRB_SDQ7 AP48 BF14
SA_DQ_7 SB_DQ_7 SB_WE# DDRB_SWE# 15
DDRA_SDQ8 AN43 DDRB_SDQ8 AU47
DDRA_SDQ9 SA_DQ_8 DDRB_SDQ9 SB_DQ_8
AN44 SA_DQ_9 AU46 SB_DQ_9
DDRA_SDQ10 AU40 DDRB_SDQ10 BA48
DDRA_SDQ11 SA_DQ_10 DDRB_SDQ11 SB_DQ_10
AT38 SA_DQ_11 AY48 SB_DQ_11
DDRA_SDQ12 AN41 DDRB_SDQ12 AT47
DDRA_SDQ13 SA_DQ_12 DDRA_SDM0 DDRB_SDQ13 SB_DQ_12
AN39 SA_DQ_13 SA_DM_0 AM37 AR47 SB_DQ_13
DDRA_SDQ14 AU44 AT41 DDRA_SDM1 DDRB_SDQ14 BA47
DDRA_SDQ15 SA_DQ_14 SA_DM_1 DDRA_SDM2 DDRB_SDQ15 SB_DQ_14 DDRB_SDM0
AU42 SA_DQ_15 SA_DM_2 AY41 BC47 SB_DQ_15 SB_DM_0 AM47
DDRA_SDQ16 AV39 AU39 DDRA_SDM3 DDRB_SDQ16 BC46 AY47 DDRB_SDM1
DDRA_SDQ17 SA_DQ_16 SA_DM_3 DDRA_SDM4 DDRB_SDQ17 SB_DQ_16 SB_DM_1 DDRB_SDM2
AY44 SA_DQ_17 SA_DM_4 BB12 BC44 SB_DQ_17 SB_DM_2 BD40
DDRA_SDQ18 BA40 AY6 DDRA_SDM5 DDRB_SDQ18 BG43 BF35 DDRB_SDM3
C DDRA_SDQ19 SA_DQ_18 SA_DM_5 DDRA_SDM6 DDRB_SDQ19 SB_DQ_18 SB_DM_3 DDRB_SDM4 C
BD43 SA_DQ_19 SA_DM_6 AT7 BF43 SB_DQ_19 SB_DM_4 BG11
DDRA_SDQ20 AV41 AJ5 DDRA_SDM7 DDRB_SDQ20 BE45 BA3 DDRB_SDM5
DDRA_SDQ21 SA_DQ_20 SA_DM_7 DDRB_SDQ21 SB_DQ_20 SB_DM_5 DDRB_SDM6
AY43 BC41 AP1

B
SA_DQ_21 SB_DQ_21 SB_DM_6
A

DDRA_SDQ22 BB41 DDRB_SDQ22 BF40 AK2 DDRB_SDM7

DDRA_SDQ23 SA_DQ_22 DDRA_SDQS0 DDRB_SDQ23 SB_DQ_22 SB_DM_7
BC40 SA_DQ_23 SA_DQS_0 AJ44 DDRA_SDQS0 14 BF41 SB_DQ_23
DDRA_SDQ24 AY37 AT44 DDRA_SDQS1 DDRB_SDQ24 BG38
SA_DQ_24 SA_DQS_1 DDRA_SDQS1 14 SB_DQ_24
DDRA_SDQ25 BD38 BA43 DDRA_SDQS2 DDRB_SDQ25 BF38 AL47 DDRB_SDQS0
SA_DQ_25 SA_DQS_2 DDRA_SDQS2 14 SB_DQ_25 SB_DQS_0 DDRB_SDQS0 15

MEMORY
DDRA_SDQ26 DDRA_SDQS3 DDRB_SDQ26 DDRB_SDQS1
MEMORY

AV37 SA_DQ_26 SA_DQS_3 BC37 DDRA_SDQS3 14 BH35 SB_DQ_26 SB_DQS_1 AV48 DDRB_SDQS1 15
DDRA_SDQ27 AT36 AW12 DDRA_SDQS4 DDRB_SDQ27 BG35 BG41 DDRB_SDQS2
SA_DQ_27 SA_DQS_4 DDRA_SDQS4 14 SB_DQ_27 SB_DQS_2 DDRB_SDQS2 15
DDRA_SDQ28 AY38 BC8 DDRA_SDQS5 DDRB_SDQ28 BH40 BG37 DDRB_SDQS3
SA_DQ_28 SA_DQS_5 DDRA_SDQS5 14 SB_DQ_28 SB_DQS_3 DDRB_SDQS3 15
DDRA_SDQ29 BB38 AU8 DDRA_SDQS6 DDRB_SDQ29 BG39 BH9 DDRB_SDQS4
SA_DQ_29 SA_DQS_6 DDRA_SDQS6 14 SB_DQ_29 SB_DQS_4 DDRB_SDQS4 15
DDRA_SDQ30 AV36 AM7 DDRA_SDQS7 DDRB_SDQ30 BG34 BB2 DDRB_SDQS5
SA_DQ_30 SA_DQS_7 DDRA_SDQS7 14 SB_DQ_30 SB_DQS_5 DDRB_SDQS5 15
DDRA_SDQ31 AW36 DDRB_SDQ31 BH34 AU1 DDRB_SDQS6
SA_DQ_31 SB_DQ_31 SB_DQS_6 DDRB_SDQS6 15
DDRA_SDQ32 BD13 DDRB_SDQ32 BH14 AN6 DDRB_SDQS7
SA_DQ_32 SB_DQ_32 SB_DQS_7 DDRB_SDQS7 15
DDRA_SDQ33 AU11 AJ43 DDRA_SDQS0# DDRB_SDQ33 BG12
SA_DQ_33 SA_DQS#_0 DDRA_SDQS0# 14 SB_DQ_33
DDRA_SDQ34 BC11 AT43 DDRA_SDQS1# DDRB_SDQ34 BH11
SA_DQ_34 SA_DQS#_1 DDRA_SDQS1# 14 SB_DQ_34
DDRA_SDQ35 BA12 BA44 DDRA_SDQS2# DDRB_SDQ35 BG8 AL46 DDRB_SDQS0#
SA_DQ_35 SA_DQS#_2 DDRA_SDQS2# 14 SB_DQ_35 SB_DQS#_0 DDRB_SDQS0# 15

SYSTEM
DDRA_SDQ36
SYSTEM

AU13 BD37 DDRA_SDQS3# DDRB_SDQ36 BH12 AV47 DDRB_SDQS1#

SA_DQ_36 SA_DQS#_3 DDRA_SDQS3# 14 SB_DQ_36 SB_DQS#_1 DDRB_SDQS1# 15
DDRA_SDQ37 AV13 AY12 DDRA_SDQS4# DDRB_SDQ37 BF11 BH41 DDRB_SDQS2#
SA_DQ_37 SA_DQS#_4 DDRA_SDQS4# 14 SB_DQ_37 SB_DQS#_2 DDRB_SDQS2# 15
DDRA_SDQ38 BD12 BD8 DDRA_SDQS5# DDRB_SDQ38 BF8 BH37 DDRB_SDQS3#
SA_DQ_38 SA_DQS#_5 DDRA_SDQS5# 14 SB_DQ_38 SB_DQS#_3 DDRB_SDQS3# 15
DDRA_SDQ39 BC12 AU9 DDRA_SDQS6# DDRB_SDQ39 BG7 BG9 DDRB_SDQS4#
SA_DQ_39 SA_DQS#_6 DDRA_SDQS6# 14 SB_DQ_39 SB_DQS#_4 DDRB_SDQS4# 15
DDRA_SDQ40 BB9 AM8 DDRA_SDQS7# DDRB_SDQ40 BC5 BC2 DDRB_SDQS5#
SA_DQ_40 SA_DQS#_7 DDRA_SDQS7# 14 SB_DQ_40 SB_DQS#_5 DDRB_SDQS5# 15
DDRA_SDQ41 BA9 DDRB_SDQ41 BC6 AT2 DDRB_SDQS6#
SA_DQ_41 SB_DQ_41 SB_DQS#_6 DDRB_SDQS6# 15
DDRA_SDQ42 AU10 DDRB_SDQ42 AY3 AN5 DDRB_SDQS7#
SA_DQ_42 SB_DQ_42 SB_DQS#_7 DDRB_SDQS7# 15
DDRA_SDQ43 AV9 DDRB_SDQ43 AY1
DDRA_SDQ44 SA_DQ_43 DDRA_SMA0 DDRB_SDQ44 SB_DQ_43
BA11 SA_DQ_44 SA_MA_0 BA21 BF6 SB_DQ_44
DDRA_SDQ45 BD9 BC24 DDRA_SMA1 DDRB_SDQ45 BF5 AV17 DDRB_SMA0

DDR
SA_DQ_45 SA_MA_1 SB_DQ_45 SB_MA_0
DDR

DDRA_SDQ46 AY8 BG24 DDRA_SMA2 DDRB_SDQ46 BA1 BA25 DDRB_SMA1

DDRA_SDQ47 SA_DQ_46 SA_MA_2 DDRA_SMA3 DDRB_SDQ47 SB_DQ_46 SB_MA_1 DDRB_SMA2
BA6 SA_DQ_47 SA_MA_3 BH24 BD3 SB_DQ_47 SB_MA_2 BC25
B DDRA_SDQ48 DDRA_SMA4 DDRB_SDQ48 DDRB_SMA3 B
AV5 SA_DQ_48 SA_MA_4 BG25 AV2 SB_DQ_48 SB_MA_3 AU25
DDRA_SDQ49 AV7 BA24 DDRA_SMA5 DDRB_SDQ49 AU3 AW25 DDRB_SMA4
DDRA_SDQ50 SA_DQ_49 SA_MA_5 DDRA_SMA6 DDRB_SDQ50 SB_DQ_49 SB_MA_4 DDRB_SMA5
AT9 SA_DQ_50 SA_MA_6 BD24 AR3 SB_DQ_50 SB_MA_5 BB28
DDRA_SDQ51 AN8 BG27 DDRA_SMA7 DDRB_SDQ51 AN2 AU28 DDRB_SMA6
DDRA_SDQ52 SA_DQ_51 SA_MA_7 DDRA_SMA8 DDRB_SDQ52 SB_DQ_51 SB_MA_6 DDRB_SMA7
AU5 SA_DQ_52 SA_MA_8 BF25 AY2 SB_DQ_52 SB_MA_7 AW28
DDRA_SDQ53 AU6 AW24 DDRA_SMA9 DDRB_SDQ53 AV1 AT33 DDRB_SMA8
DDRA_SDQ54 SA_DQ_53 SA_MA_9 DDRA_SMA10 DDRB_SDQ54 SB_DQ_53 SB_MA_8 DDRB_SMA9
AT5 SA_DQ_54 SA_MA_10 BC21 AP3 SB_DQ_54 SB_MA_9 BD33
DDRA_SDQ55 AN10 BG26 DDRA_SMA11 DDRB_SDQ55 AR1 BB16 DDRB_SMA10
DDRA_SDQ56 SA_DQ_55 SA_MA_11 DDRA_SMA12 DDRB_SDQ56 SB_DQ_55 SB_MA_10 DDRB_SMA11
AM11 SA_DQ_56 SA_MA_12 BH26 AL1 SB_DQ_56 SB_MA_11 AW33
DDRA_SDQ57 AM5 BH17 DDRA_SMA13 DDRB_SDQ57 AL2 AY33 DDRB_SMA12
DDRA_SDQ58 SA_DQ_57 SA_MA_13 DDRA_SMA14 DDRB_SDQ58 SB_DQ_57 SB_MA_12 DDRB_SMA13
AJ9 SA_DQ_58 SA_MA_14 AY25 AJ1 SB_DQ_58 SB_MA_13 BH15
DDRA_SDQ59 AJ8 DDRB_SDQ59 AH1 AU33 DDRB_SMA14
DDRA_SDQ60 SA_DQ_59 DDRB_SDQ60 SB_DQ_59 SB_MA_14
AN12 SA_DQ_60 AM2 SB_DQ_60
DDRA_SDQ61 AM13 DDRB_SDQ61 AM3
DDRA_SDQ62 SA_DQ_61 DDRB_SDQ62 SB_DQ_61
AJ11 SA_DQ_62 AH3 SB_DQ_62
DDRA_SDQ63 AJ12 DDRB_SDQ63 AJ3
SA_DQ_63 SB_DQ_63
CANTIGA ES_FCBGA1329 CANTIGA ES_FCBGA1329
JAL90GM@ JAL90GM@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 9 of 50
5 4 3 2 1
 5 4 3 2 1

U31C

18 DPST_PWM L32 L_BKLT_CTRL

17,31 ENBKL 1 2 LBKLT_EN G32 T37 PEG_COMP 1 2 +1.05VS
R117 GM@ 0_0402_5% LCTLA_CLK L_BKLT_EN PEG_COMPI R130 49.9_0402_1%
LCTLB_DATA
M32 L_CTRL_CLK PEG_COMPO T36 10mils
M33 L_CTRL_DATA
18 GMCH_LCD_CLK GMCH_LCD_CLK K33
GMCH_LCD_DATA L_DDC_CLK PCIE_GTX_C_MRX_N0 PCIE_MTX_C_GRX_N[0..15]
D 18 GMCH_LCD_DATA J33 L_DDC_DATA PEG_RX#_0 H44 PCIE_MTX_C_GRX_N[0..15] 17 D
M29 J46 PCIE_GTX_C_MRX_N1
18 GMCH_ENVDD L_VDD_EN PEG_RX#_1 PCIE_MTX_C_GRX_P[0..15]
L44 PCIE_GTX_C_MRX_N2
PEG_RX#_2 PCIE_MTX_C_GRX_P[0..15] 17
1 2 LVDS_IBG C44 L40 PCIE_GTX_C_MRX_N3
R402 GM@ 2.37K_0402_1% LVDS_IBG PEG_RX#_3 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_N[0..15]
B43 LVDS_VBG PEG_RX#_4 N41 PCIE_GTX_C_MRX_N[0..15] 17
2 1 E37 P48 PCIE_GTX_C_MRX_N5
R517 GM@ LVDS_VREFH PEG_RX#_5 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_P[0..15]
E38 LVDS_VREFL PEG_RX#_6 N44 PCIE_GTX_C_MRX_P[0..15] 17
0_0402_5% T43 PCIE_GTX_C_MRX_N7
GMCH_TXCLK- PEG_RX#_7 PCIE_GTX_C_MRX_N8
18 GMCH_TXCLK- C41 LVDSA_CLK# PEG_RX#_8 U43
GMCH_TXCLK+ C40 Y43 PCIE_GTX_C_MRX_N9
18 GMCH_TXCLK+ LVDSA_CLK PEG_RX#_9
GMCH_TZCLK- B37 Y48 PCIE_GTX_C_MRX_N10
18 GMCH_TZCLK- LVDSB_CLK# PEG_RX#_10
GMCH_TZCLK+ A37 Y36 PCIE_GTX_C_MRX_N11
18 GMCH_TZCLK+ LVDSB_CLK PEG_RX#_11

LVDS
AA43 PCIE_GTX_C_MRX_N12
GMCH_TXOUT0- PEG_RX#_12 PCIE_GTX_C_MRX_N13
18 GMCH_TXOUT0- H47 LVDSA_DATA#_0 PEG_RX#_13 AD37
GMCH_TXOUT1- E46 AC47 PCIE_GTX_C_MRX_N14
18 GMCH_TXOUT1- LVDSA_DATA#_1 PEG_RX#_14
GMCH_TXOUT2- G40 AD39 PCIE_GTX_C_MRX_N15
18 GMCH_TXOUT2- LVDSA_DATA#_2 PEG_RX#_15
A40 LVDSA_DATA#_3
H43 PCIE_GTX_C_MRX_P0
GMCH_TXOUT0+ PEG_RX_0 PCIE_GTX_C_MRX_P1
18 GMCH_TXOUT0+ H48 LVDSA_DATA_0 PEG_RX_1 J44
GMCH_TXOUT1+ D45 L43 PCIE_GTX_C_MRX_P2
18 GMCH_TXOUT1+ LVDSA_DATA_1 PEG_RX_2

GRAPHICS
GMCH_TXOUT2+ F40 L41 PCIE_GTX_C_MRX_P3
18 GMCH_TXOUT2+ LVDSA_DATA_2 PEG_RX_3
B40 N40 PCIE_GTX_C_MRX_P4
LVDSA_DATA_3 PEG_RX_4 PCIE_GTX_C_MRX_P5
PEG_RX_5 P47
GMCH_TZOUT0- A41 N43 PCIE_GTX_C_MRX_P6
18 GMCH_TZOUT0- LVDSB_DATA#_0 PEG_RX_6
GMCH_TZOUT1- H38 T42 PCIE_GTX_C_MRX_P7
18 GMCH_TZOUT1- LVDSB_DATA#_1 PEG_RX_7
GMCH_TZOUT2- G37 U42 PCIE_GTX_C_MRX_P8
18 GMCH_TZOUT2- LVDSB_DATA#_2 PEG_RX_8
J37 Y42 PCIE_GTX_C_MRX_P9
LVDSB_DATA#_3 PEG_RX_9 PCIE_GTX_C_MRX_P10
PEG_RX_10 W47
GMCH_TZOUT0+ B42 Y37 PCIE_GTX_C_MRX_P11
18 GMCH_TZOUT0+ LVDSB_DATA_0 PEG_RX_11
C GMCH_TZOUT1+ G38 AA42 PCIE_GTX_C_MRX_P12 C
18 GMCH_TZOUT1+ LVDSB_DATA_1 PEG_RX_12
GMCH_TZOUT2+ F37 AD36 PCIE_GTX_C_MRX_P13
18 GMCH_TZOUT2+ LVDSB_DATA_2 PEG_RX_13
K37 AC48 PCIE_GTX_C_MRX_P14
LVDSB_DATA_3 PEG_RX_14

PCI-EXPRESS
AD40 PCIE_GTX_C_MRX_P15
PEG_RX_15
J41 PCIE_MTX_GRX_N0 C210 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0
PEG_TX#_0 PCIE_MTX_GRX_N1 C218 1
PEG_TX#_1 M46 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N1
GMCH_TV_COMPS F25 M47 PCIE_MTX_GRX_N2 C222 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2
GMCH_TV_LUMA TVA_DAC PEG_TX#_2 PCIE_MTX_GRX_N3 C228 1
H25 TVB_DAC PEG_TX#_3 M40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N3
GMCH_TV_CRMA K25 M42 PCIE_MTX_GRX_N4 C231 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4
TVC_DAC PEG_TX#_4 PCIE_MTX_GRX_N5 C234 1
PEG_TX#_5 R48 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N5
2

TV
H24 N38 PCIE_MTX_GRX_N6 C237 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6
R104 R105 R93 TV_RTN PEG_TX#_6 PCIE_MTX_GRX_N7 C242 1
PEG_TX#_7 T40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N7
U37 PCIE_MTX_GRX_N8 C243 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8
GM@ GM@ GM@ PEG_TX#_8 PCIE_MTX_GRX_N9 C251 1
PEG_TX#_9 U40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N9
75_0402_1% TV_DCONSEL_0 C31 Y40 PCIE_MTX_GRX_N10 C250 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10
1

75_0402_1% TV_DCONSEL_1 TV_DCONSEL_0 PEG_TX#_10 PCIE_MTX_GRX_N11 C257 1

E32 TV_DCONSEL_1 PEG_TX#_11 AA46 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N11
75_0402_1% AA37 PCIE_MTX_GRX_N12 C249 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12
PEG_TX#_12 PCIE_MTX_GRX_N13 C244 1
PEG_TX#_13 AA40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N13
AD43 PCIE_MTX_GRX_N14 C256 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14
PEG_TX#_14 PCIE_MTX_GRX_N15 C252 1
PEG_TX#_15 AC46 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N15
Change to 0Ohm when use PM chip PCIE_MTX_GRX_P0 C208
19 GMCH_CRT_B E28 CRT_BLUE PEG_TX_0 J42 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
2 1 L46 PCIE_MTX_GRX_P1 C215 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P1
R114 GM@ 150_0402_1% PEG_TX_1 PCIE_MTX_GRX_P2 C220
19 GMCH_CRT_G G28 CRT_GREEN PEG_TX_2 M48 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2
2 1 M39 PCIE_MTX_GRX_P3 C223 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P3
PEG_TX_3

VGA
R115 GM@ 150_0402_1% J28 M43 PCIE_MTX_GRX_P4 C229 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
19 GMCH_CRT_R CRT_RED PEG_TX_4
2 1 R47 PCIE_MTX_GRX_P5 C232 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P5
R116 GM@ 150_0402_1% PEG_TX_5 PCIE_MTX_GRX_P6 C235
G29 CRT_IRTN PEG_TX_6 N37 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
B PCIE_MTX_GRX_P7 C238 1 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P7 B
PEG_TX_7 T39 2
GMCH_CRT_CLK H32 U36 PCIE_MTX_GRX_P8 C239 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
19 GMCH_CRT_CLK CRT_DDC_CLK PEG_TX_8
GMCH_CRT_DATA J32 U39 PCIE_MTX_GRX_P9 C246 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P9
19 GMCH_CRT_DATA CRT_DDC_DATA PEG_TX_9
J29 Y39 PCIE_MTX_GRX_P10 C245 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10
19 GMCH_CRT_HSYNC CRT_HSYNC PEG_TX_10
2 1 CRT_IREF E29 Y46 PCIE_MTX_GRX_P11 C253 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P11
R107 PM@ 0_0402_5% CRT_TVO_IREF PEG_TX_11 PCIE_MTX_GRX_P12 C247
PEG_TX_12 AA36 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12
AA39 PCIE_MTX_GRX_P13 C241 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P13
PEG_TX_13 PCIE_MTX_GRX_P14 C255 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14
19 GMCH_CRT_VSYNC L29 CRT_VSYNC PEG_TX_14 AD42 1 2
2 1 AD46 PCIE_MTX_GRX_P15 C248 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P15
+3VS R101 PM@ 0_0402_5% PEG_TX_15
2

R119 CANTIGA ES_FCBGA1329

R123 1 GM@ 2 2.2K_0402_5% GMCH_LCD_CLK 1.02K_0402_1% JAL90GM@
GM@
R122 1 GM@ 2 2.2K_0402_5% GMCH_LCD_DATA
1

R127 1 GM@ 2 10K_0402_5% LCTLB_DATA

R120 1 GM@ 2 10K_0402_5% LCTLA_CLK

R108 1 GM@ 2 2.2K_0402_5% GMCH_CRT_CLK

R100 1 GM@ 2 2.2K_0402_5% GMCH_CRT_DATA

A A

R124 GM@ 0_0402_5% TV_DCONSEL_0

R109 GM@ 0_0402_5% TV_DCONSEL_1

R112 1 2 100K_0402_5% LBKLT_EN Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 10 of 50
5 4 3 2 1
 5 4 3 2 1

U31F
+VGFX_CORE
+1.8V

2600mA VCC_AXG_NTCF_1 W28

AP33 VCC_SM_1 VCC_AXG_NCTF_2 V28
AN33 VCC_SM_2 VCC_AXG_NCTF_3 W26 Place close to the GMCH
BH32 VCC_SM_3 VCC_AXG_NCTF_4 V26
D
BG32 VCC_SM_4 VCC_AXG_NCTF_5 W25
+1.05VS VCC: 1930.4mA (GMCH), 1210.34mA (MCH) D
BF32 V25
BD32
VCC_SM_5 VCC_AXG_NCTF_6
W24 (270UF*1, 22UF*1, 0.22UF*2, 0.1UF*1)
VCC_SM_6 VCC_AXG_NCTF_7
BC32 VCC_SM_7 VCC_AXG_NCTF_8 V24
BB32 W23 +1.05VS
VCC_SM_8 VCC_AXG_NCTF_9 1

VCC
BA32 V23 1 1 U31G
VCC_SM_9 VCC_AXG_NCTF_10 + C122 C193 C194 C195 C192
AY32 VCC_SM_10 VCC_AXG_NCTF_11 AM21
AW32 VCC_SM_11 VCC_AXG_NCTF_12 AL21 AG34 VCC_1
AV32 AK21 220U_D2_4VM_R15 0.22U_0402_6.3V6K 0.1U_0402_16V4Z AC34
VCC_SM_12 VCC_AXG_NCTF_13 2 2 2 VCC_2
AU32 VCC_SM_13 VCC_AXG_NCTF_14 W21 AB34 VCC_3
AT32 V21 10U_0805_10V4Z 0.22U_0402_6.3V6K AA34

SM
VCC_SM_14 VCC_AXG_NCTF_15 VCC_4
AR32 VCC_SM_15 VCC_AXG_NCTF_16 U21 Y34 VCC_5
AP32 AM20 Cavity Capacitors V34

VCC CORE
VCC_SM_16 VCC_AXG_NCTF_17 VCC_6
AN32 VCC_SM_17 VCC_AXG_NCTF_18 AK20 U34 VCC_7
BH31 VCC_SM_18 VCC_AXG_NCTF_19 W20 AM33 VCC_8
BG31 VCC_SM_19 VCC_AXG_NCTF_20 U20 AK33 VCC_9
BF31 VCC_SM_20 VCC_AXG_NCTF_21 AM19 AJ33 VCC_10
BG30 VCC_SM_21 VCC_AXG_NCTF_22 AL19 AG33 VCC_11
BH29 VCC_SM_22 VCC_AXG_NCTF_23 AK19 AF33 VCC_12
BG29 VCC_SM_23 VCC_AXG_NCTF_24 AJ19
BF29 AH19 J1 VCC_AXG: 6326.84mA
VCC_SM_24 VCC_AXG_NCTF_25 JUMP_43X79 +VGFX_CORE
BD29 AG19
BC29
VCC_SM_25 VCC_AXG_NCTF_26
AF19 @ (330UF*2, 22UF*1, 10UF*1, 1U*1, 0.47U*1, 0.1UF*2) AE33
VCC_SM_26 VCC_AXG_NCTF_27 VCC_13
BB29 VCC_SM_27 VCC_AXG_NCTF_28 AE19 +1.05VS 1 1 2 2 AC33 VCC_14
Reference PILLAR_ROCK CRB Rev1.0 BA29 VCC_SM_28 VCC_AXG_NCTF_29 AB19 AA33 VCC_15
AY29 AA19 1 2 C180 C181 C172 1 C174 1 C171 1 C178 1 Y33
VCC_SM_29 VCC_AXG_NCTF_30 VCC_16
GFX NCTF
AW29 Y19 R111 GM@ 0_0805_5% W33
VCC_SM_30 VCC_AXG_NCTF_31 GM@ VCC_17
Pins BA36, BB24, BD16,

POWER
AV29 VCC_SM_31 VCC_AXG_NCTF_32 W19 1 1 2 2 V33 VCC_18
BB21, AW16, AW13, AT13 AU29 V19 0.47U_0603_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z U33
VCC_SM_32 VCC_AXG_NCTF_33 J2 GM@ GM@ 2 2 GM@ 2 2 VCC_19
AT29 U19 AH28
could be left NC for DDR2 AR29
VCC_SM_33 VCC_AXG_NCTF_34
AM17 JUMP_43X79 R84 1U_0402_6.3V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z AF28
VCC_20
board. VCC_SM_34 VCC_AXG_NCTF_35 @ 0_0402_5% GM@ GM@ VCC_21
AP29 VCC_SM_35 VCC_AXG_NCTF_36 AK17 AC28 VCC_22
AH17 PM@ Cavity Capacitors AA28
C VCC_AXG_NCTF_37 VCC_23 C
VCC_AXG_NCTF_38 AG17 AJ26 VCC_24
VCC_AXG_NCTF_39 AF17 AG26 VCC_25
VCC_SM_BA36 BA36 AE17 AE26
VCC_SM_BB24 VCC_SM_36/NC VCC_AXG_NCTF_40 VCC_26
BB24 VCC_SM_37/NC VCC_AXG_NCTF_41 AC17 AC26 VCC_27 +1.05VS
VCC

VCC_SM_BD16 BD16 AB17 AH25

VCC_SM_38/NC VCC_AXG_NCTF_42 VCC_28
BB21 VCC_SM_39/NC VCC_AXG_NCTF_43 Y17 AG25 VCC_29
VCC_SM_AW16 AW16 W17 1 AF25
VCC_SM_40/NC VCC_AXG_NCTF_44 C118 VCC_30
AW13 VCC_SM_41/NC VCC_AXG_NCTF_45 V17 AG24 VCC_31 VCC_NCTF_1 AM32
VCC_SM_AT13 AT13 AM16 + AJ23 AL32
VCC_SM_42/NC VCC_AXG_NCTF_46 VCC_32 VCC_NCTF_2
VCC_AXG_NCTF_47 AL16 AH23 VCC_33 VCC_NCTF_3 AK32
AK16 330U_D2E_2.5VM_R15 AF23 AJ32
POWER

VCC_AXG_NCTF_48 GM@ 2 VCC_34 VCC_NCTF_4

VCC_AXG_NCTF_49 AJ16 T32 VCC_35 VCC_NCTF_5 AH32
+VGFX_CORE AH16 AG32
VCC_AXG_NCTF_50 VCC_NCTF_6
VCC_AXG_NCTF_51 AG16 VCC_NCTF_7 AE32
VCC_AXG_NCTF_52 AF16 Place close to the GMCH VCC_NCTF_8 AC32
Y26 VCC_AXG_1 VCC_AXG_NCTF_53 AE16 VCC_NCTF_9 AA32
AE25 VCC_AXG_2 VCC_AXG_NCTF_54 AC16 VCC_NCTF_10 Y32
AB25 VCC_AXG_3 VCC_AXG_NCTF_55 AB16 VCC_NCTF_11 W32
AA25 VCC_AXG_4 VCC_AXG_NCTF_56 AA16 VCC_NCTF_12 U32
AE24 VCC_AXG_5 VCC_AXG_NCTF_57 Y16 VCC_NCTF_13 AM30
AC24 VCC_AXG_6 VCC_AXG_NCTF_58 W16 VCC_SM: 2600mA VCC_NCTF_14 AL30
AA24 V16 AK30
Y24
VCC_AXG_7 VCC_AXG_NCTF_59
U16 +1.8V (330UF*1, 22UF*2, 0.1UF*1) VCC_NCTF_15
AH30
VCC_AXG_8 VCC_AXG_NCTF_60 VCC_NCTF_16
AE23 VCC_AXG_9 VCC_NCTF_17 AG30
AC23 VCC_AXG_10 VCC_NCTF_18 AF30
AB23 VCC_AXG_11 1 VCC_NCTF_19 AE30
AA23 C205 1 1 1 AC30

NCTF
VCC_AXG_12 + C190 C191 C196 VCC_NCTF_20
AJ21 VCC_AXG_13 VCC_NCTF_21 AB30
AG21 VCC_AXG_14 VCC_NCTF_22 AA30
AE21 330U_D2E_2.5VM_R15 10U_0805_10V4Z Y30
VCC_AXG_15 2 2 2 2 VCC_NCTF_23
AC21 VCC_AXG_16 VCC_NCTF_24 W30
AA21 10U_0805_10V4Z 0.1U_0402_16V4Z V30
B VCC_AXG_17 VCC_NCTF_25 B
Y21 VCC_AXG_18 VCC_NCTF_26 U30
VCC

VCC
AH20 VCC_AXG_19 Place on the edge VCC_NCTF_27 AL29
AF20 VCC_AXG_20 VCC_NCTF_28 AK29
AE20 VCC_AXG_21 VCC_NCTF_29 AJ29
AC20 VCC_AXG_22 Reference PILLAR_ROCK CRB Rev1.0 VCC_NCTF_30 AH29
AB20 VCC_AXG_23 VCC_NCTF_31 AG29
AA20 AE29
GFX

VCC_AXG_24 VCC_SM_BA36 VCC_NCTF_32

T17 VCC_AXG_25 VCC_NCTF_33 AC29
T16 VCC_SM_BB24 AA29
VCC_AXG_26 VCC_SM_BD16 VCC_NCTF_34
AM15 VCC_AXG_27 VCC_NCTF_35 Y29
AL15 VCC_SM_AW16 W29
VCC_AXG_28 VCC_SM_AT13 VCC_NCTF_36
AE15 VCC_AXG_29 VCC_NCTF_37 V29
AJ15 VCC_AXG_30 VCC_NCTF_38 AL28
AH15 VCC_AXG_31 1 1 1 1 1 VCC_NCTF_39 AK28
AG15 C164 C170 C169 C185 C200 AL26
VCC_AXG_32 @ @ @ @ @ VCC_NCTF_40
AF15 VCC_AXG_33 VCC_NCTF_41 AK26
AB15 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K AK25
VCC_AXG_34 2 2 2 2 2 VCC_NCTF_42
AA15 VCC_AXG_35 VCC_NCTF_43 AK24
Y15 0.1U_0402_16V7K 0.1U_0402_16V7K AK23
VCC_AXG_36 VCC_NCTF_44
V15 VCC_AXG_37
U15 VCC_AXG_38
AN14 VCC_AXG_39
AM14 VCC_AXG_40
U14 AV44 VCCSM_LF1
VCC SM LF

VCC_AXG_41 VCC_SM_LF1 VCCSM_LF2

T14 VCC_AXG_42 VCC_SM_LF2 BA37
AM40 VCCSM_LF3
VCC_SM_LF3 VCCSM_LF4
VCC_SM_LF4 AV21
AY5 VCCSM_LF5
@ VCC_AXG_SENSE VCC_SM_LF5 VCCSM_LF6 CANTIGA ES_FCBGA1329
T10 PAD AJ14 VCC_AXG_SENSE VCC_SM_LF6 AM10
PAD @ VSS_AXG_SENSE AH14 BB13 VCCSM_LF7 JAL90GM@
T9 VSS_AXG_SENSE VCC_SM_LF7
1 1 1 1 1 1 1
C165 C159 C158 C177 C202 C199 C211
A A
0.1U_0402_16V7K 0.22U_0402_6.3V6K 0.47U_0603_16V4Z 1U_0402_6.3V4Z
2 2 2 2 2 2 2
0.1U_0402_16V7K 0.22U_0402_6.3V6K 1U_0402_6.3V4Z
CANTIGA ES_FCBGA1329
JAL90GM@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 11 of 50
5 4 3 2 1
 5 4 3 2 1

+1.05VS_HPLL
+1.05VS_DPLLA
+1.05VS L23 1 2
MBK1608121YZF_0603 1 1 +1.05VS 1 2

1
VCCA_HPLL: 24mA C434 C441 L32 1 1 U31H VTT: 852mA
0_1210_5% C513 R536 +1.05VS
(4.7UF*1, 0.1UF*1) 4.7U_0805_10V4Z GM@ C505 + GM@ 0_0402_5% (270UF*1, 4.7UF*2, 2.2UF*1, 0.47UF*1)
2 2 852mA
Please check Power GM@ PM@ 73mA U13
0.1U_0402_16V4Z 220U_D2_4VM_R15 2 VTT_1
source if want VCCA_DPLLA +3VS_CRTDAC B27 T13 1

2
2 0.1U_0402_16V4Z VCCA_CRT_DAC_1 VTT_2
Please check Power VCCA_DPLLB: 64.8mA A26 VCCA_CRT_DAC_2 VTT_3 U12 1 1 1 1
support IAMT T12 C104 + C127 C116 C100 C108
+1.05VS_MPLL source if want (220UF*1, 0.1UF*1) VTT_4
VTT_5 U11
120Ohm@100MHz support IAMT 2.69mA T11 220U_D2_4VM_R15 4.7U_0805_10V4Z 0.47U_0603_16V4Z
+1.05VS_DPLLB VTT_6 2 2 2 2 2

CRT
D L5 1 D
2 +3VS_DACBG A25 VCCA_DAC_BG VTT_7 U10
MBK1608121YZF_0603 1 T10 4.7U_0805_10V4Z 2.2U_0603_6.3V6K
VTT_8

1
VCCA_MPLL: 139.2mA C149 1 2 B25 U9
VSSA_DAC_BG VTT_9

1
R335 L10 1 1 T9
(22UF*1, 0.1UF*1) 0.5_0603_1% 0_1210_5% C214 R537 VTT_10
U8
2 GM@ GM@ 0_0402_5% VTT_11
64.8mA VTT_12 T8

VTT
0.1U_0402_16V4Z C263 PM@ +1.05VS_DPLLA F47 U7

2
2
10U_0805_10V4Z 2 VCCA_DPLLA VTT_13
1 T7

2
GM@ 0.1U_0402_16V4Z VTT_14
+1.05VS_DPLLB L48 VCCA_DPLLB VTT_15 U6
C437 T6
24mA VTT_16

PLL
22U_0805_6.3V6M +1.05VS_HPLL AD1 VCCA_HPLL VTT_17 U5
2 R141 +1.8V_TX_LVDS VTT_18 T5
@ 0_0402_5% 1 AE1 139.2mA V3
+1.05VS_MPLL VCCA_MPLL VTT_19
+3VS 1 2 C213 U3
GM@ VTT_20
+VCCA_PEG_BG
VCCA_LVDS: 13.2mA 13.2mA VTT_21 V2

A PEG A LVDS
R140 1000P_0402_50V7K J48 U2
0_0402_5% 2 (1000PF*1) VCCA_LVDS VTT_22
T2
VTT_23
+1.5VS 1 2 J47 VSSA_LVDS VTT_24 V1
VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1) +3VS_CRTDAC U1
1 VTT_25
Please check Power C216 VCCA_PEG_BG: 0.414mA 0.414mA Please check Power
+3VS 1 2 source if want (0.1UF*1) AD48 VCCA_PEG_BG source if want
L31 GM@ 0.1U_0402_16V4Z VCC_AXF: 321.35mA
1

MBK1608301YZF_0603 1 1
support IAMT 2 +1.05VS_AXF support IAMT
C495 C494 R393 (10UF*1, 1UF*1)
1 50mA
GM@ GM@ 0_0402_5% No CIS Symbol AA48 1 2 +1.05VS
C606 + 0.1U_0402_16V4Z PM@ L8 1 +1.05VS_PEGPLL VCCA_PEG_PLL R376
+1.05VS 2
GM@ 2 2 MBK1608221YZF_0603 0_0603_5%
1 VCCA_PEG_PLL: 50mA 1 1
2

220U_D2_4VM_R15 0.01U_0402_16V7K 2 1 1 2 C519 C471 C470

2 C233 R142 (0.1UF*1) @
Close to Ball A26, B27 10U_0805_6.3V6M 1_0402_1% 0.1U_0402_16V4Z 480mA 10U_0805_6.3V6M
2
AR20 VCCA_SM_1
POWER 2 2
+1.05VS_A_SM AP20 1U_0402_6.3V4Z
C VCCA_SM_2 C
VCCA_SM: AN20 VCCA_SM_3
+1.05VS 1 2 (22UF*2, 4.7UF*1, 1UF*1) AR17 VCCA_SM_4 +1.8V_SM_CK
VCC_SM_CK: 119.85mA

A SM
1 R97 1 1 1 AP17
0_0805_5% C173 C168 C176 AN17
VCCA_SM_5
B22
(10UF*1, 0.1UF*1) 1uH 30%
VCCA_SM_6 VCC_AXF_1

AXF
Please check Power C435 + AT16 B21 1 2
VCCA_SM_7 VCC_AXF_2 +1.8V
@ 4.7U_0805_10V4Z AR16 A21 L28
source if want 220U_D2_4VM_R15 2 2 2 VCCA_SM_8 VCC_AXF_3 MBK1608121YZF_0603
AP16 VCCA_SM_9 1
support IAMT 2 22U_0805_6.3V6M 1U_0402_6.3V4Z C466
1 2 1 2
Please check Power 0.1U_0402_16V4Z R377 C167
2 1_0402_1% 10U_0805_6.3V6M
source if want VCC_SM_CK_1 BF21

SM CK
VCCA_DAC_BG: 2.6833333mA support IAMT +1.05VS_A_SM_CK VCC_SM_CK_2 BH20
(0.1UF*1, 0.01UF*1) +3VS_DACBG
VCCA_SM_CK: 24mA VCC_SM_CK_3 BG20
(22UF*1, 2.2UF*1, 0.1UF*1) 24mA VCC_SM_CK_4 BF20
+1.8V_TX_LVDS
+1.05VS 1 2 AP28 VCCA_SM_CK_1 +1.8V_TX_LVDS: 118.8mA
1 2 R106 1 1 1 AN28 0.1uH 20%
+3VS
L30 GM@ 0_0603_5% C182 C189 C186 AP25
VCCA_SM_CK_2 (22UF*1, 1000PF*1) 1 2
VCCA_SM_CK_3 +1.8V
1

MBK1608221YZF_0603 1 1 1 @ AN25 118.8mA 1 1 R178

VCCA_SM_CK_4

1
C489 C488 C486 R391 2.2U_0603_6.3V6K 0.1U_0402_16V4Z AN24 K47 C261 C265 0_0603_5%
2 2 2 VCCA_SM_CK_5 VCC_TX_LVDS

A CK
GM@ GM@ @ 0_0402_5% AM28 R175 GM@ GM@ GM@
0.1U_0402_16V4Z 10U_0805_6.3V6M PM@ 22U_0805_6.3V6M VCCA_SM_CK_NCTF_1 PM@ 1000P_0402_50V7K
AM26 VCCA_SM_CK_NCTF_2
2 2 2 0_0402_5% 2 2 10U_0805_10V4Z
AM25 105.3mA VCC_HV: 105.3mA
2

0.01U_0402_16V7K VCCA_SM_CK_NCTF_3
NO_STUFF AL25 C35 +3VS

2
VCCA_SM_CK_NCTF_4 VCC_HV_1
AM24 VCCA_SM_CK_NCTF_5 VCC_HV_2 B35 1

HV
Close to Ball A25 AL24 A35 C197
VCCA_SM_CK_NCTF_6 VCC_HV_3
AM23 VCCA_SM_CK_NCTF_7 Please check Power
AL23 0.1U_0402_16V4Z
VCCA_SM_CK_NCTF_8 2 source if want
1782mA support IAMT
VCC_PEG_1 V48 +1.05VS_PEG: 1782mA +1.05VS_PEG
VCC_PEG_2 U48 (220UF*1, 22UF*1, 4.7UF*1)

PEG
VCCA_TV_DAC: 40mA (0.1UF*1, VCC_PEG_3 V47 1 2 +1.05VS
87.79mA U47 1 R174
B 0.01UF*1 for each DAC) B24
VCC_PEG_4
U46 0_0805_5% B
+3VS_TVDAC VCCA_TV_DAC_1 VCC_PEG_5 1
+3VS_TVDAC A24 C236 + C258
VCCA_TV_DAC_2

TV
+3VS L29 1 2 VCCD_HDA: 50mA 10U_0805_10V4Z 220U_D2_4VM_R15
MBK1608221YZF_0603 2 2
(0.1UF*1) 50mA 456mA
1

180Ohm@100MHz GM@ 1 2 +1.5VS_HDA A32 AH48 +1.05VS

1 1 +1.5VS VCC_HDA VCC_DMI_1

HDA
C478 C477 R387 R396 1 AF48
VCC_DMI_2
1

DMI
GM@ GM@ 0_0402_5% 0_0402_5% C498 Close to A32 AH47
0.1U_0402_16V4Z PM@ JAL90GM@ R395 VCC_DMI_3 +1.05VS_DMI
VCC_DMI_4 AG47 1 2
2 2 0_0402_5% 0.1U_0402_16V4Z R163
58.696mA
2

0.01U_0402_16V7K GLPM@ 2
JAL90GM@ 0_0805_5%
+1.5VS_TVDAC M25 VCCD_TVDAC VCC_DMI: 456mA 1

D TV/CRT
C219
(0.1UF*1)
2

L28 48.363mA
+1.5VS_QDAC VCCD_QDAC 0.1U_0402_16V4Z
2
VCCD_HPLL: 157.2mA (0.1UF*1) 157.2mA
+1.05VS_HPLL AF1 VCCD_HPLL
A8 VTTLF_CAP1
+1.05VS_PEGPLL 50mA VTTLF1 VTTLF_CAP2
Please check Power AA47 VCCD_PEG_PLL VTTLF2 L1

VTTLF
VCCD_TVDAC: 58.696mA source if want VTTLF3 AB2 VTTLF_CAP3
+1.5VS_TVDAC 60.31mA
(0.1UF*1, 0.01UF*1) support IAMT M38 VCCD_LVDS_1 1 1 1
LVDS

+1.5VS 1 2 L37 C142 C438 C452

L6 VCCD_LVDS_2
1 1
MBK1608221YZF_0603 C183 C184 Also power for internal VCCD_PEG_PLL: 50mA 0.47U_0603_16V4Z 0.47U_0603_16V4Z
2 2 2
0.1U_0402_16V4Z
Thermal Sensor (0.1UF*1) CANTIGA ES_FCBGA1329 0.47U_0603_16V4Z
2 2 +1.8V_LVDS JAL90GM@
+1.8V 1 2
0.022U_0402_16V7K R132
1

0_0603_5% 1 1
GM@ C201 C203 R131
GM@ GM@ 0_0402_5%
10U_0805_6.3V6M PM@
A 2 2 A
VCCD_QDAC: 48.363mA +1.5VS_QDAC R172
2

1U_0402_6.3V4Z D10
(0.1UF*1, 0.01UF*1) 2 1 1 2
+1.05VS +3VS
+1.5VS 1 2 VCCD_LVDS: 60.311111mA
R83 1 1 10_0603_5%
(1UF*1)
1

100_0603_1% C179 C188 CH751H-40PT_SOD323-2

180Ohm@100MHz R91
0.1U_0402_16V4Z 0_0402_5%
2 2 @ Security Classification Compal Secret Data Compal Electronics, Inc.
0.01U_0402_16V7K 2007/09/20 2008/09/20 Title
Issued Date Deciphered Date
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 12 of 50
5 4 3 2 1
 5 4 3 2 1

U31I U31J

AU48 VSS_1 VSS_100 AM36 BG21 VSS_199 VSS_297 AH8

AR48 VSS_2 VSS_101 AE36 L12 VSS_200 VSS_298 Y8
AL48 VSS_3 VSS_102 P36 AW21 VSS_201 VSS_299 L8
BB47 VSS_4 VSS_103 L36 AU21 VSS_202 VSS_300 E8
AW47 VSS_5 VSS_104 J36 AP21 VSS_203 VSS_301 B8
AN47 VSS_6 VSS_105 F36 AN21 VSS_204 VSS_302 AY7
AJ47 VSS_7 VSS_106 B36 AH21 VSS_205 VSS_303 AU7
AF47 VSS_8 VSS_107 AH35 AF21 VSS_206 VSS_304 AN7
AD47 VSS_9 VSS_108 AA35 AB21 VSS_207 VSS_305 AJ7
AB47 VSS_10 VSS_109 Y35 R21 VSS_208 VSS_306 AE7
Y47 VSS_11 VSS_110 U35 M21 VSS_209 VSS_307 AA7
T47 VSS_12 VSS_111 T35 J21 VSS_210 VSS_308 N7
D D
N47 VSS_13 VSS_112 BF34 G21 VSS_211 VSS_309 J7
L47 VSS_14 VSS_113 AM34 BC20 VSS_212 VSS_310 BG6
G47 VSS_15 VSS_114 AJ34 BA20 VSS_213 VSS_311 BD6
BD46 VSS_16 VSS_115 AF34 AW20 VSS_214 VSS_312 AV6
BA46 VSS_17 VSS_116 AE34 AT20 VSS_215 VSS_313 AT6
AY46 VSS_18 VSS_117 W34 AJ20 VSS_216 VSS_314 AM6
AV46 VSS_19 VSS_118 B34 AG20 VSS_217 VSS_315 M6
AR46 VSS_20 VSS_119 A34 Y20 VSS_218 VSS_316 C6
AM46 VSS_21 VSS_120 BG33 N20 VSS_219 VSS_317 BA5
V46 VSS_22 VSS_121 BC33 K20 VSS_220 VSS_318 AH5
R46 VSS_23 VSS_122 BA33 F20 VSS_221 VSS_319 AD5
P46 VSS_24 VSS_123 AV33 C20 VSS_222 VSS_320 Y5
H46 VSS_25 VSS_124 AR33 A20 VSS_223 VSS_321 L5
F46 VSS_26 VSS_125 AL33 BG19 VSS_224 VSS_322 J5
BF44 VSS_27 VSS_126 AH33 A18 VSS_225 VSS_323 H5
AH44 VSS_28 VSS_127 AB33 BG17 VSS_226 VSS_324 F5
AD44 VSS_29 VSS_128 P33 BC17 VSS_227 VSS_325 BE4
AA44 VSS_30 VSS_129 L33 AW17 VSS_228
Y44 VSS_31 VSS_130 H33 AT17 VSS_229 VSS_327 BC3
U44 VSS_32 VSS_131 N32 R17 VSS_230 VSS_328 AV3
T44 VSS_33 VSS_132 K32 M17 VSS_231 VSS_329 AL3
M44 VSS_34 VSS_133 F32 H17 VSS_232 VSS_330 R3
F44
BC43
VSS_35
VSS_36
VSS_134
VSS_135
C32
A31
C17 VSS_233 VSS VSS_331
VSS_332
P3
F3
AV43 VSS_37 VSS_136 AN29 BA16 VSS_235 VSS_333 BA2
AU43 VSS_38 VSS_137 T29 VSS_334 AW2
AM43 VSS_39 VSS_138 N29 AU16 VSS_237 VSS_335 AU2
J43 VSS_40 VSS_139 K29 AN16 VSS_238 VSS_336 AR2
C43 VSS_41 VSS_140 H29 N16 VSS_239 VSS_337 AP2
BG42
AY42
VSS_42
VSS_43
VSS VSS_141
VSS_142
F29
A29
K16
G16
VSS_240
VSS_241
VSS_338
VSS_339
AJ2
AH2
AT42 VSS_44 VSS_143 BG28 E16 VSS_242 VSS_340 AF2
C C
AN42 VSS_45 VSS_144 BD28 BG15 VSS_243 VSS_341 AE2
AJ42 VSS_46 VSS_145 BA28 AC15 VSS_244 VSS_342 AD2
AE42 VSS_47 VSS_146 AV28 W15 VSS_245 VSS_343 AC2
N42 VSS_48 VSS_147 AT28 A15 VSS_246 VSS_344 Y2
L42 VSS_49 VSS_148 AR28 BG14 VSS_247 VSS_345 M2
BD41 VSS_50 VSS_149 AJ28 AA14 VSS_248 VSS_346 K2
AU41 VSS_51 VSS_150 AG28 C14 VSS_249 VSS_347 AM1
AM41 VSS_52 VSS_151 AE28 BG13 VSS_250 VSS_348 AA1
AH41 VSS_53 VSS_152 AB28 BC13 VSS_251 VSS_349 P1
AD41 VSS_54 VSS_153 Y28 BA13 VSS_252 VSS_350 H1
AA41 VSS_55 VSS_154 P28
Y41 VSS_56 VSS_155 K28 VSS_351 U24
U41 VSS_57 VSS_156 H28 AN13 VSS_255 VSS_352 U28
T41 VSS_58 VSS_157 F28 AJ13 VSS_256 VSS_353 U25
M41 VSS_59 VSS_158 C28 AE13 VSS_257 VSS_354 U29
G41 VSS_60 VSS_159 BF26 N13 VSS_258
B41 VSS_61 VSS_160 AH26 L13 VSS_259 VSS_NCTF_1 AF32
BG40 VSS_62 VSS_161 AF26 G13 VSS_260 VSS_NCTF_2 AB32
BB40 VSS_63 VSS_162 AB26 E13 VSS_261 VSS_NCTF_3 V32
AV40 VSS_64 VSS_163 AA26 BF12 VSS_262 VSS_NCTF_4 AJ30
AN40 VSS_65 VSS_164 C26 AV12 VSS_263 VSS_NCTF_5 AM29
H40 VSS_66 VSS_165 B26 AT12 VSS_264 VSS_NCTF_6 AF29
E40 VSS_67 VSS_166 BH25 AM12 VSS_265 VSS_NCTF_7 AB29
AT39 BD25 AA12 U26

VSS NCTF
VSS_68 VSS_167 VSS_266 VSS_NCTF_8
AM39 VSS_69 VSS_168 BB25 J12 VSS_267 VSS_NCTF_9 U23
AJ39 VSS_70 VSS_169 AV25 A12 VSS_268 VSS_NCTF_10 AL20
AE39 VSS_71 VSS_170 AR25 BD11 VSS_269 VSS_NCTF_11 V20
N39 VSS_72 VSS_171 AJ25 BB11 VSS_270 VSS_NCTF_12 AC19
L39 VSS_73 VSS_172 AC25 AY11 VSS_271 VSS_NCTF_13 AL17
B39 VSS_74 VSS_173 Y25 AN11 VSS_272 VSS_NCTF_14 AJ17
BH38 VSS_75 VSS_174 N25 AH11 VSS_273 VSS_NCTF_15 AA17
BC38 VSS_76 VSS_175 L25 VSS_NCTF_16 U17
B B
BA38 VSS_77 VSS_176 J25 Y11 VSS_275
AU38 VSS_78 VSS_177 G25 N11 VSS_276
AH38 VSS_79 VSS_178 E25 G11 VSS_277 VSS_SCB_1 BH48
AD38 VSS_80 VSS_179 BF24 C11 VSS_278 VSS_SCB_2 BH1
AA38 VSS_81 VSS_180 AD12 BG10 VSS_279 VSS_SCB_3 A48
Y38 AY24 AV10 C1
VSS SCB

VSS_82 VSS_181 VSS_280 VSS_SCB_4

U38 VSS_83 VSS_182 AT24 AT10 VSS_281 VSS_SCB_5 A3
T38 VSS_84 VSS_183 AJ24 AJ10 VSS_282
J38 VSS_85 VSS_184 AH24 AE10 VSS_283
F38 VSS_86 VSS_185 AF24 AA10 VSS_284
C38 VSS_87 VSS_186 AB24 M10 VSS_285
BF37 VSS_88 VSS_187 R24 BF9 VSS_286 NC_26 E1
BB37 VSS_89 VSS_188 L24 BC9 VSS_287 NC_27 D2
AW37 VSS_90 VSS_189 K24 AN9 VSS_288 NC_28 C3
AT37 VSS_91 VSS_190 J24 AM9 VSS_289 NC_29 B4
AN37 VSS_92 VSS_191 G24 AD9 VSS_290 NC_30 A5
AJ37 VSS_93 VSS_192 F24 G9 VSS_291 NC_31 A6
H37 VSS_94 VSS_193 E24 B9 VSS_292 NC_32 A43
C37 VSS_95 VSS_194 BH23 BH8 VSS_293 NC_33 A44
BG36 VSS_96 VSS_195 AG23 BB8 VSS_294 NC_34 B45
BD36 Y23 AV8 C46
NC

VSS_97 VSS_196 VSS_295 NC_35

AK15 VSS_98 VSS_197 B23 AT8 VSS_296 NC_36 D47
AU36 VSS_99 VSS_198 A23 NC_37 B47
VSS_199 AJ6 NC_38 A46
NC_39 F48
CANTIGA ES_FCBGA1329 E48
JAL90GM@ NC_40
NC_41 C48
NC_42 B48

CANTIGA ES_FCBGA1329
JAL90GM@
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 13 of 50
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V

JDIMM2 +1.8V
+DIMM_VREF 1 VREF VSS 2
3 4 DDRA_SDQ4 +DIMM_VREF
VSS DQ4

1
DDRA_SDQ0 5 6 DDRA_SDQ5 20mils
DDRA_SDQ1 DQ0 DQ5 R138
7 DQ1 VSS 8
9 10 DDRA_SDM0
DDRA_SDQS0# VSS DM0 1K_0402_1%
9 DDRA_SDQS0# DDRA_SDQS0
11 DQS0# VSS 12
DDRA_SDQ6
1
C206
20mils
13 14 To SODIMM and GMCH

2
9 DDRA_SDQS0 DQS0 DQ6 DDRA_SDQ7
15 VSS DQ7 16 +DIMM_VREF
DDRA_SDQ2 17 18 0.1U_0402_16V4Z
DQ2 VSS

1
DDRA_SDQ3 DDRA_SDQ12 2
19 DQ3 DQ12 20
D DDRA_SDQ13 R136 D
21 VSS DQ13 22
DDRA_SDQ8 23 24
DDRA_SDQ9 DQ8 VSS DDRA_SDM1 1K_0402_1%
25 DQ9 DM1 26
27 28

2
DDRA_SDQS1# VSS VSS
9 DDRA_SDQS1# 29 DQS1# CK0 30 DDRA_CLK0 8
DDRA_SDQS1 31 32
9 DDRA_SDQS1 DQS1 CK0# DDRA_CLK0# 8
33 VSS VSS 34
DDRA_SDQ10 35 36 DDRA_SDQ14
DDRA_SDQ11 DQ10 DQ14 DDRA_SDQ15
37 DQ11 DQ15 38
39 40 DDRA_SMA[0..14]
VSS VSS 9 DDRA_SMA[0..14]
DDRA_SDQ[0..63]
9 DDRA_SDQ[0..63]
41 VSS VSS 42
DDRA_SDQ16 43 44 DDRA_SDQ20 DDRA_SDM[0..7]
DQ16 DQ20 9 DDRA_SDM[0..7] +1.8V
DDRA_SDQ17 45 46 DDRA_SDQ21
DQ17 DQ21
47 VSS VSS 48
DDRA_SDQS2# 49 50
9 DDRA_SDQS2# DQS2# NC PM_EXTTS#0 8
DDRA_SDQS2 51 52 DDRA_SDM2
9 DDRA_SDQS2 DQS2 DM2
53 VSS VSS 54 1 1 1 1 1
DDRA_SDQ18 55 56 DDRA_SDQ22 C150 C123 C136 C102 C113
DDRA_SDQ19 DQ18 DQ22 DDRA_SDQ23
57 DQ19 DQ23 58
59 60 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K
DDRA_SDQ24 VSS VSS DDRA_SDQ28 2 2 2 2 2
61 DQ24 DQ28 62
DDRA_SDQ25 63 64 DDRA_SDQ29 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K
DQ25 DQ29
65 VSS VSS 66
DDRA_SDM3 67 68 DDRA_SDQS3#
DM3 DQS3# DDRA_SDQS3 DDRA_SDQS3# 9
69 NC DQS3 70 DDRA_SDQS3 9
71 VSS VSS 72
DDRA_SDQ26 73 74 DDRA_SDQ30 +1.8V
DDRA_SDQ27 DQ26 DQ30 DDRA_SDQ31 +0.9VS
75 DQ27 DQ31 76
77 VSS VSS 78
DDRA_CKE0 79 80 DDRA_CKE1 DDRA_CKE0 1 4
C 8 DDRA_CKE0 CKE0 NC/CKE1 DDRA_CKE1 8 C
81 82 DDRA_SBS2# 2 3 1 1 1 1
VDD VDD RP45 56_0404_4P2R_5% C436 C433 C442 C447
83 NC NC/A15 84
DDRA_SBS2# 85 86 DDRA_SMA14
9 DDRA_SBS2# BA2 NC/A14
87 88 DDRA_SMA12 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SMA12 VDD VDD DDRA_SMA11 DDRA_SMA9 2 2 2 2
89 A12 A11 90 2 3
DDRA_SMA9 91 92 DDRA_SMA7 RP40 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SMA8 A9 A7 DDRA_SMA6
93 A8 A6 94
95 96 DDRA_SMA8 1 4
DDRA_SMA5 VDD VDD DDRA_SMA4 DDRA_SMA5
97 A5 A4 98 2 3
DDRA_SMA3 99 100 DDRA_SMA2 RP35 56_0404_4P2R_5%
DDRA_SMA1 A3 A2 DDRA_SMA0
101 A1 A0 102
103 104 DDRA_SMA3 1 4
DDRA_SMA10 VDD VDD DDRA_SBS1# DDRA_SMA1 +0.9VS
105 A10/AP BA1 106 DDRA_SBS1# 9 2 3
DDRA_SBS0# 107 108 DDRA_SRAS# RP31 56_0404_4P2R_5%
9 DDRA_SBS0# BA0 RAS# DDRA_SRAS# 9
DDRA_SWE# 109 110 DDRA_SCS0#
9 DDRA_SWE# WE# S0# DDRA_SCS0# 8
111 112 DDRA_SMA10 1 4
DDRA_SCAS# VDD VDD DDRA_ODT0 DDRA_SBS0#
9 DDRA_SCAS# 113 CAS# ODT0 114 DDRA_ODT0 8 2 3 1 1 1 1 1
DDRA_SCS1# 115 116 DDRA_SMA13 RP27 56_0404_4P2R_5% C101 C103 C110 C119 C128
8 DDRA_SCS1# NC/S1# NC/A13
117 VDD VDD 118
DDRA_ODT1 119 120 DDRA_SWE# 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
8 DDRA_ODT1 NC/ODT1 NC 2 2 2 2 2
121 122 DDRA_SCAS# 2 3
DDRA_SDQ32 VSS VSS DDRA_SDQ36 RP23 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
123 DQ32 DQ36 124
DDRA_SDQ33 125 126 DDRA_SDQ37
DQ33 DQ37 DDRA_SCS1#
127 VSS VSS 128 1 4
DDRA_SDQS4# 129 130 DDRA_SDM4 DDRA_ODT1 2 3
9 DDRA_SDQS4# DDRA_SDQS4 DQS4# DM4 RP19 56_0404_4P2R_5% +0.9VS
9 DDRA_SDQS4 131 DQS4 VSS 132
133 134 DDRA_SDQ38
DDRA_SDQ34 VSS DQ38 DDRA_SDQ39
135 DQ34 DQ39 136
DDRA_SDQ35 137 138
DQ35 VSS DDRA_SDQ44 DDRA_SMA11
139 VSS DQ44 140 1 4 1 1 1 1 1
DDRA_SDQ40 141 142 DDRA_SDQ45 DDRA_SMA14 2 3 C109 C115 C124 C153 C143
DDRA_SDQ41 DQ40 DQ45 RP41 56_0404_4P2R_5%
143 DQ41 VSS 144
B DDRA_SDQS5# 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z B
145 VSS DQS5# 146 DDRA_SDQS5# 9
DDRA_SDM5 DDRA_SDQS5 DDRA_SMA6 2 2 2 2 2
147 DM5 DQS5 148 DDRA_SDQS5 9 1 4
149 150 DDRA_SMA7 2 3 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SDQ42 VSS VSS DDRA_SDQ46 RP37 56_0404_4P2R_5%
151 DQ42 DQ46 152
DDRA_SDQ43 153 154 DDRA_SDQ47
DQ43 DQ47 DDRA_SMA2
155 VSS VSS 156 1 4
DDRA_SDQ48 157 158 DDRA_SDQ52 DDRA_SMA4 2 3 +0.9VS
DDRA_SDQ49 DQ48 DQ52 DDRA_SDQ53 RP32 56_0404_4P2R_5%
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 DDRA_SBS1# 1 4
NC,TEST CK1 DDRA_CLK1 8
165 166 DDRA_SMA0 2 3 1 1 1
VSS CK1# DDRA_CLK1# 8
DDRA_SDQS6# 167 168 RP28 56_0404_4P2R_5% C141 C133 C151
9 DDRA_SDQS6# DDRA_SDQS6 DQS6# VSS DDRA_SDM6
9 DDRA_SDQS6 169 DQS6 DM6 170
171 172 DDRA_SCS0# 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SDQ50 VSS VSS DDRA_SDQ54 DDRA_SRAS# 2 2 2
173 DQ50 DQ54 174 2 3
DDRA_SDQ51 175 176 DDRA_SDQ55 RP24 56_0404_4P2R_5% 0.1U_0402_16V4Z
DQ51 DQ55
177 VSS VSS 178
DDRA_SDQ56 179 180 DDRA_SDQ60 DDRA_SMA13 1 4
DDRA_SDQ57 DQ56 DQ60 DDRA_SDQ61 DDRA_ODT0
181 DQ57 DQ61 182 2 3
183 184 RP20 56_0404_4P2R_5%
DDRA_SDM7 VSS VSS DDRA_SDQS7#
185 DM7 DQS7# 186 DDRA_SDQS7# 9
187 188 DDRA_SDQS7 DDRA_CKE1 1 2
DDRA_SDQ58 VSS DQS7 DDRA_SDQS7 9 R71 56_0402_5%
189 DQ58 VSS 190
DDRA_SDQ59 191 192 DDRA_SDQ62
DQ59 DQ62 DDRA_SDQ63
193 VSS DQ63 194
D_CK_SDATA 195 196
15,16,20 D_CK_SDATA SDA VSS
D_CK_SCLK 197 198 R25 1 2 10K_0402_5%
15,16,20 D_CK_SCLK SCL SAO
+3VS 199 200 R21 1 2 10K_0402_5%
VDDSPD SA1
203 GND GND 204

FOX_AS0A426-N2RN-7F
CONN@
A +3VS A

1 1
DIMM0 REV H:5.2mm (BOT)
C32 C57

0.1U_0402_16V4Z
2
2.2U_0603_6.3V6K 2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 14 of 50
5 4 3 2 1
 A B C D E

+DIMM_VREF +1.8V

+1.8V +1.8V
1 1
1 1
JDIMM1 C209 C207 + C160 + C230
+DIMM_VREF 1 2 @
VREF VSS DDRB_SDQ4 2.2U_0603_6.3V6K
3 VSS DQ4 4
DDRB_SDQ0 DDRB_SDQ1 2 2
0.1U_0402_16V4Z 2 2
5 DQ0 DQ5 6
DDRB_SDQ5 7 8 330U_D2E_2.5VM_R15
DQ1 VSS DDRB_SDM0 330U_D2E_2.5VM_R15
9 VSS DM0 10
DDRB_SDQS0# 11 12
1 9 DDRB_SDQS0# DDRB_SDQS0 DQS0# VSS DDRB_SDQ6 1
9 DDRB_SDQS0 13 DQS0 DQ6 14
15 16 DDRB_SDQ7
DDRB_SDQ2 VSS DQ7
17 DQ2 VSS 18
DDRB_SDQ3 19 20 DDRB_SDQ12
DQ3 DQ12 DDRB_SDQ13
21 VSS DQ13 22
DDRB_SDQ8 23 24
DDRB_SDQ9 DQ8 VSS DDRB_SDM1
25 DQ9 DM1 26
27 VSS VSS 28
DDRB_SDQS1# 29 30
9 DDRB_SDQS1# DQS1# CK0 DDRB_CLK0 8
DDRB_SDQS1 31 32
9 DDRB_SDQS1 DQS1 CK0# DDRB_CLK0# 8
33 VSS VSS 34
DDRB_SDQ10 35 36 DDRB_SDQ14 DDRB_SMA[0..14]
DQ10 DQ14 9 DDRB_SMA[0..14]
DDRB_SDQ11 37 38 DDRB_SDQ15
DQ11 DQ15 DDRB_SDQ[0..63]
39 VSS VSS 40 9 DDRB_SDQ[0..63]
DDRB_SDM[0..7]
9 DDRB_SDM[0..7]
41 VSS VSS 42
DDRB_SDQ16 43 44 DDRB_SDQ20
DDRB_SDQ17 DQ16 DQ20 DDRB_SDQ21
45 DQ17 DQ21 46
47 VSS VSS 48
DDRB_SDQS2# 49 50
9 DDRB_SDQS2# DQS2# NC PM_EXTTS#1 8
DDRB_SDQS2 51 52 DDRB_SDM2
9 DDRB_SDQS2 DQS2 DM2
53 VSS VSS 54
DDRB_SDQ18 55 56 DDRB_SDQ22
DDRB_SDQ19 DQ18 DQ22 DDRB_SDQ23
57 DQ19 DQ23 58
59 VSS VSS 60
DDRB_SDQ24 61 62 DDRB_SDQ28
DDRB_SDQ25 DQ24 DQ28 DDRB_SDQ29
63 DQ25 DQ29 64
65 VSS VSS 66
DDRB_SDM3 67 68 DDRB_SDQS3# +1.8V
DM3 DQS3# DDRB_SDQS3 DDRB_SDQS3# 9 +0.9VS
69 NC DQS3 70 DDRB_SDQS3 9
71 VSS VSS 72
2 DDRB_SDQ26 DDRB_SDQ30 2
73 DQ26 DQ30 74
DDRB_SDQ27 75 76 DDRB_SDQ31 DDRB_CKE0 1 4 1 1 1 1 1
DQ27 DQ31 DDRB_SBS2# C152 C140 C120 C99 C112
77 VSS VSS 78 2 3
DDRB_CKE0 79 80 DDRB_CKE1 RP44 56_0404_4P2R_5%
8 DDRB_CKE0 CKE0 NC/CKE1 DDRB_CKE1 8
81 82 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K
VDD VDD DDRB_SMA12 2 2
2.2U_0603_6.3V6K 2 2
2.2U_0603_6.3V6K 2
83 NC NC/A15 84 1 4
DDRB_SBS2# 85 86 DDRB_SMA14 DDRB_SMA9 2 3
9 DDRB_SBS2# BA2 NC/A14
87 88 RP39 56_0404_4P2R_5%
DDRB_SMA12 VDD VDD DDRB_SMA11
89 A12 A11 90
DDRB_SMA9 91 92 DDRB_SMA7 DDRB_SMA8 1 4
DDRB_SMA8 A9 A7 DDRB_SMA6 DDRB_SMA5 +1.8V
93 A8 A6 94 2 3
95 96 RP34 56_0404_4P2R_5%
DDRB_SMA5 VDD VDD DDRB_SMA4
97 A5 A4 98
DDRB_SMA3 99 100 DDRB_SMA2 DDRB_SMA3 1 4
DDRB_SMA1 A3 A2 DDRB_SMA0 DDRB_SMA1
101 A1 A0 102 2 3 1 1 1 1
103 104 RP30 56_0404_4P2R_5% C106 C96 C156 C129
DDRB_SMA10 VDD VDD DDRB_SBS1#
105 A10/AP BA1 106 DDRB_SBS1# 9
DDRB_SBS0# 107 108 DDRB_SRAS# DDRB_SMA10 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z
9 DDRB_SBS0# BA0 RAS# DDRB_SRAS# 9 2 2 2 2
DDRB_SWE# 109 110 DDRB_SCS0# DDRB_SBS0# 2 3 0.1U_0402_16V4Z 0.1U_0402_16V4Z
9 DDRB_SWE# WE# S0# DDRB_SCS0# 8
111 112 RP26 56_0404_4P2R_5%
DDRB_SCAS# VDD VDD DDRB_ODT0
9 DDRB_SCAS# 113 CAS# ODT0 114 DDRB_ODT0 8
DDRB_SCS1# 115 116 DDRB_SMA13 DDRB_SWE# 1 4
8 DDRB_SCS1# NC/S1# NC/A13
117 118 DDRB_SCAS# 2 3
DDRB_ODT1 VDD VDD RP22 56_0404_4P2R_5%
8 DDRB_ODT1 119 NC/ODT1 NC 120
121 VSS VSS 122
DDRB_SDQ32 123 124 DDRB_SDQ36 DDRB_SCS1# 1 4
DDRB_SDQ33 DQ32 DQ36 DDRB_SDQ37 DDRB_ODT1 +0.9VS
125 DQ33 DQ37 126 2 3
127 128 RP18 56_0404_4P2R_5%
DDRB_SDQS4# VSS VSS DDRB_SDM4
9 DDRB_SDQS4# 129 DQS4# DM4 130
DDRB_SDQS4 131 132
9 DDRB_SDQS4 DQS4 VSS DDRB_SDQ38
133 VSS DQ38 134 1 1 1 1 1
DDRB_SDQ34 135 136 DDRB_SDQ39 DDRB_SMA11 1 4 C111 C117 C114 C107 C132
3 DDRB_SDQ35 DQ34 DQ39 DDRB_SMA14 3
137 DQ35 VSS 138 2 3
139 140 DDRB_SDQ44 RP42 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SDQ40 VSS DQ44 DDRB_SDQ45 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z
141 DQ40 DQ45 142
DDRB_SDQ41 143 144 DDRB_SMA6 1 4
DQ41 VSS DDRB_SDQS5# DDRB_SMA7
145 VSS DQS5# 146 DDRB_SDQS5# 9 2 3
DDRB_SDM5 147 148 DDRB_SDQS5 RP38 56_0404_4P2R_5%
DM5 DQS5 DDRB_SDQS5 9
149 VSS VSS 150
DDRB_SDQ42 151 152 DDRB_SDQ46 DDRB_SMA2 1 4 +0.9VS
DDRB_SDQ43 DQ42 DQ46 DDRB_SDQ47 DDRB_SMA4
153 DQ43 DQ47 154 2 3
155 156 RP33 56_0404_4P2R_5%
DDRB_SDQ48 VSS VSS DDRB_SDQ52
157 DQ48 DQ52 158
DDRB_SDQ49 159 160 DDRB_SDQ53 DDRB_SBS1# 1 4 1 1 1 1 1
DQ49 DQ53 DDRB_SMA0 C146 C121 C144 C105 C97
161 VSS VSS 162 2 3
163 164 RP29 56_0404_4P2R_5%
NC,TEST CK1 DDRB_CLK1 8
165 166 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VSS CK1# DDRB_CLK1# 8 2 2 2 2 2
DDRB_SDQS6# 167 168 DDRB_SCS0# 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z
9 DDRB_SDQS6# DDRB_SDQS6 DQS6# VSS DDRB_SDM6 DDRB_SRAS#
9 DDRB_SDQS6 169 DQS6 DM6 170 2 3
171 172 RP25 56_0404_4P2R_5%
DDRB_SDQ50 VSS VSS DDRB_SDQ54
173 DQ50 DQ54 174
DDRB_SDQ51 175 176 DDRB_SDQ55 DDRB_SMA13 1 4 +0.9VS
DQ51 DQ55 DDRB_ODT0
177 VSS VSS 178 2 3
DDRB_SDQ56 179 180 DDRB_SDQ60 RP21 56_0404_4P2R_5%
DDRB_SDQ57 DQ56 DQ60 DDRB_SDQ61
181 DQ57 DQ61 182
183 184 DDRB_CKE1 1 2 1 1 1
DDRB_SDM7 VSS VSS DDRB_SDQS7# R70 56_0402_5% C154 C134 C125
185 DM7 DQS7# 186 DDRB_SDQS7# 9
187 188 DDRB_SDQS7
DDRB_SDQ58 VSS DQS7 DDRB_SDQS7 9 0.1U_0402_16V4Z 0.1U_0402_16V4Z
189 DQ58 VSS 190
DDRB_SDQ59 DDRB_SDQ62 2 2
0.1U_0402_16V4Z 2
191 DQ59 DQ62 192
193 194 DDRB_SDQ63
D_CK_SDATA VSS DQ63
14,16,20 D_CK_SDATA 195 SDA VSS 196
D_CK_SCLK 197 198 R24 1 2 10K_0402_5%
14,16,20 D_CK_SCLK SCL SAO
+3VS 199 200 R20 1 2 10K_0402_5% +3VS
4 VDDSPD SA1 4
201 GND GND 202

FOX_AS0A426-NARN-7F
CONN@

DIMM1 REV H:9.2mm (BOT)

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 15 of 50
A B C D E
 A B C D E F G H

FSLC FSLB FSLA CPU SRC PCI

+CLK_VDDSRC +CLK_VDD
Clock Generator
CLKSEL2 CLKSEL1 CLKSEL0 L11 2 L14 2
MHz MHz MHz +1.05VS 1
KC FBM-L11-201209-221LMAT_0805
+3VS 1
KC FBM-L11-201209-221LMAT_0805
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 266 100 33.3 C280 C289 C288 C315 C327 C297 C329 C331 C286 C305 C300 C330 C287 C328
C275 C333
10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
0 1 0 200 100 33.3 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

0 1 1 166 100 33.3 U15

1 1
+CLK_VDD ICS9LPRS387, PN:SA000020H10
Table : ICS9LPRS387 D_CK_SDATA
SLG8SP556V, PN:SA000020K00 SDATA 9 D_CK_SDATA 14,15,20
CLK_REQ# Control Free-Run 6 VDDREF D_CK_SCLK
SCLK 10 D_CK_SCLK 14,15,20
CR#_10(WLAN) PCIEX10 PCIEX0 19 VDD48
CR#_6(MCH) PCIEX6 PCIEX1 72 71 CLK_CPU_BCLK
VDDCPU CPUT0_LPR_F CLK_CPU_BCLK 4
CR#_4(NEW CARD) PCIEX4 12 70 CLK_CPU_BCLK#
VDDPCI CPUC0_LPR_F CLK_CPU_BCLK# 4
+3VS
CR#_9(MINI CARDII) PCIEX9 27 VDDPLL3
68 CLK_MCH_BCLK
CPUT1_LPR_F CLK_MCH_BCLK 7
SRC7(VGA_CLK): Discrete VGA[Enable] UMA[Disable] 55 VDDSRC

2
67 CLK_MCH_BCLK#
CPUC1_LPR_F CLK_MCH_BCLK# 7
R454
10K_0402_5% +CLK_VDDSRC 52 VDDSRC_IO
+3VS 24 CLK_DREF_96M
@ SRCT0_LPR/DOTT_96_LPR CLK_DREF_96M 8
38

1
CLK_PCI2 CK505_PWRGD VDDSRC_IO CLK_DREF_96M#
1 2 SRCC0_LPR/DOTC_96_LPR 25 CLK_DREF_96M# 8
R466 10K_0402_5% 62 VDDSRC_IO

1
D
CLK_PCI2=1, Trusted Mode Enable(No overclocking allowed) VGA: disable this pair by BIOS
2 31 28 CLK_DREF_SSC
CLK_ENABLE# 46 VDDPLL3_IO 27MHz_NonSS/SRCT1_LPR/SE1 CLK_DREF_SSC 8
mount to Enable ITP_CLK G
1 2 S Q16 66 29 CLK_DREF_SSC#
CLK_DREF_SSC# 8

3
R475 @ 10K_0402_5% VDDCPU_IO 27MHz_SS/SRCC1_LPR/SE2
2N7002_SOT23

CLK_PCI5
@ 23 VDD96_IO CLK_PCIE_SATA
VGA: disable this pair by BIOS
1 2 SRCT2_LPR/SATAT_LPR 32 CLK_PCIE_SATA 22
R474 10K_0402_5%
2 33 CLK_PCIE_SATA# 2
SRCC2_LPR/SATAC_LPR CLK_PCIE_SATA# 22
CLK_PCI5=0, Pin63,64 is SRC_CLK H_STP_CPU# 53
23 H_STP_CPU# CPU_STOP#
CLK_PCI5=1, Pin63,64 is ITP_CLK H_STP_PCI# CLK_PCIE_ICH
23 H_STP_PCI# 54 PCI_STOP# SRCT3_LPR 35 CLK_PCIE_ICH 23
1 2 CLK_PCI4 36 CLK_PCIE_ICH#
SRCC3_LPR CLK_PCIE_ICH# 23
R471 10K_0402_5%
CLK_PCI4=0, Pin28, 29 is SRC_CLK
13 39 CLK_PCIE_CARD
Pin24, 25 is DOT96_CLK PCI1 SRCT4_LPR CLK_PCIE_CARD 30
1 2 CK_PWRGD CLK_PCI2 14 40 CLK_PCIE_CARD#
PCI2/TME SRCC4_LPR CLK_PCIE_CARD# 30
R197 @ 10K_0402_5%
CLK_PCI_LPC R216 2 1 33_0402_5% CLK_PCI3 15
31 CLK_PCI_LPC PCI3
57 CLK_MCH_3GPLL
SRCT6_LPR CLK_MCH_3GPLL 8
CLK_PCI4 16
C309 1 PCI4/27_SELECT
2 @ 10P_0402_50V8J CLK_PCI_LPC
SRCC6_LPR 56 CLK_MCH_3GPLL#
CLK_MCH_3GPLL# 8
CLK_PCI_ICH R219 2 1 33_0402_5% CLK_PCI5 17
21 CLK_PCI_ICH PCI_F5/ITP_EN
C321 1 2 @ 10P_0402_50V8J CLK_PCI_ICH
61 CLK_PCIE_VGA
SRCT7_LPR CLK_PCIE_VGA 17
For EMI 10/9 0_0402_5% 2 1 R199 CK505_PWRGD1
23 CK_PWRGD CK_PWRGD/PD#
0_0402_5% 2 @ 1 R204 60 CLK_PCIE_VGA#
8,23,46 VGATE SRCC7_LPR CLK_PCIE_VGA# 17
+1.05VS C301
CLK_XTALIN CLK_PCIE_READER
UMA: disable this pair by BIOS
1 2 5 X1 CPUT2_ITP_LPR/SRCT8_LPR 64 CLK_PCIE_READER 26
2

R233 27P_0402_50V8J CLK_XTALOUT 4 63 CLK_PCIE_READER#

X2 CPUC2_ITP_LPR/SRCC8_LPR CLK_PCIE_READER# 26
@ 56_0402_5% Y1
C296 14.31818MHz_20P_FSX8L14.318181M20FDB
R231 R240 27P_0402_50V8J 11 44 CLK_PCIE_MINI2
CLK_PCIE_MINI2 29
2

3 2.2K_0402_5% 1K_0402_5% NC SRCT9_LPR 3

1 2
1

CLKSEL0 1 2 1 2 45 CLK_PCIE_MINI2#
MCH_CLKSEL0 8 SRCC9_LPR CLK_PCIE_MINI2# 29
CLK_ICH_48M R484 2 1 33_0402_5% CLKSEL0 20
23 CLK_ICH_48M USB_48MHz/FSLA
1 2 1 2 CPU_BSEL0 5 50 CLK_PCIE_MINI1
SRCT10_LPR CLK_PCIE_MINI1 29
R232 R241 CLKSEL1 2
@ 1K_0402_5% 0_0402_5% FSLB/TEST_MODE CLK_PCIE_MINI1#
SRCC10_LPR 51 CLK_PCIE_MINI1# 29
CLK_ICH_14M R212 2 1 33_0402_5% CLKSEL2 7
23 CLK_ICH_14M FSLC/TEST_SEL/REF0
+1.05VS 8 48 CLK_PCIE_LAN
REF1 SRCT11_LPR CLK_PCIE_LAN 27
47 CLK_PCIE_LAN#
SRCC11_LPR CLK_PCIE_LAN# 27
2

R456
@ 1K_0402_5% +3VS 69
R228 GNDCPU
R459 4.7K_0402_5% 3 37
GNDREF CR#3
2

1K_0402_5%
G

1 2 +3VS 1 2 +3VS
1

CLKSEL1 1 2 18 41 R214 10K_0402_5%

MCH_CLKSEL1 8 GNDPCI CR#4 EXP_CLKREQ# 30
23,29,30 ICH_SMBDATA 1 3 D_CK_SDATA
22 58
D

GND48 CR#6 MCH_CLKREQ# 8

1 2 1 2 CPU_BSEL1 5 Q48 (Pull High to +3VS at GMCH side)
R455 R461 2N7002_SOT23 30 65
@ 0_0402_5% 0_0402_5% GND CR7#
1 2 +3VS
+3VS 26 43 R213 10K_0402_5%
GND CR#9 MINI2_CLKREQ# 29
R221 1 2 +3VS
4.7K_0402_5% 34 49 R211 10K_0402_5%
GNDSRC CR10# MINI1_CLKREQ# 29
2

+1.05VS
G

1 2 +3VS
59 GNDSRC CR#11 46
23,29,30 ICH_SMBCLK 1 3 D_CK_SCLK
4 4
2

R465 42 21
D

GNDSRC CR#A SATA_CLKREQ# 23

@ 1K_0402_5% Q49 73 (Pull High to +3VS at ICH side)
2N7002_SOT23 GND_THERMAL_PAD
R463 R462 ICS9LPRS387BKLFT_MLF72_10x10
10K_0402_5% 1K_0402_5%
1

CLKSEL2 1 2 1 2 MCH_CLKSEL2 8 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
1
R464
2 1
R470
2 CPU_BSEL2 5
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
@ 0_0402_5% 0_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 16 of 50
A B C D E F G H
 5 4 3 2 1

+MXM_B+

160mil(4A) L34 2 1 B+
PCIE_MTX_C_GRX_N[0..15] KC FBM-L11-201209-221LMAT_0805 JAL90GM@
10 PCIE_MTX_C_GRX_N[0..15]
PM@ 2 160mil(4A) SDVO_SCLK R331 1 2 0_0402_5% D_EC_SMB_CK1
PCIE_MTX_C_GRX_P[0..15] 8 SDVO_SCLK
L35 2 1 C510 SDVO_SDATA R333 1 2 0_0402_5% D_EC_SMB_DA1
10 PCIE_MTX_C_GRX_P[0..15] 8 SDVO_SDATA
KC FBM-L11-201209-221LMAT_0805 JAL90GM@
PCIE_GTX_C_MRX_N[0..15] 1 1 PM@
10 PCIE_GTX_C_MRX_N[0..15] 1
C508 C504 0.1U_0603_25V7K
D PCIE_GTX_C_MRX_P[0..15] PM@ D
10 PCIE_GTX_C_MRX_P[0..15]
680P_0603_50V7K 68P_0402_50V8J
2 2

JMXM1A JMXM1B

+MXM_B+ 1 2 +1.8VS PCIE_GTX_C_MRX_N1 109 110

PWR_SRC 1V8RUN PCIE_GTX_C_MRX_P1 PEX_RX1# GND PCIE_MTX_C_GRX_N1
3 PWR_SRC 1V8RUN 4 111 PEX_RX1 PEX_TX1# 112
5 6 140mil(3.5A) 113 114 PCIE_MTX_C_GRX_P1
PWR_SRC 1V8RUN PCIE_GTX_C_MRX_N0 GND PEX_TX1
7 PWR_SRC 1V8RUN 8 115 PEX_RX0# GND 116
9 10 PCIE_GTX_C_MRX_P0 117 118 PCIE_MTX_C_GRX_N0
PWR_SRC 1V8RUN PEX_RX0 PEX_TX0# PCIE_MTX_C_GRX_P0
11 PWR_SRC 1V8RUN 12 119 GND PEX_TX0 120
13 14 CLK_PCIE_VGA# 121 122
PWR_SRC 1V8RUN 16 CLK_PCIE_VGA# PEX_REFCLK# PRSNT1#
15 16 CLK_PCIE_VGA 123 124
PWR_SRC RUNPWROK VGA_ON 33 16 CLK_PCIE_VGA PEX_REFCLK TV_C/HDTV_Pr
17 GND 5VRUN 18 +5VS 125 CLK_REQ# GND 126
19 GND GND 20 21 PLTRST_VGA# 127 PEX_RST# TV_Y/HDTV_Y/TV_CVBS 128
21 GND GND 22 22 HDA_SYNC_VGA 129 HDA_SYNC GND 130
23 GND GND 24 22 HDA_BITCLK_VGA 131 HDA_BCLK TV_CVBS/HDTV_Pb 132
D_EC_SMB_DA1 133 134
SMB_DAT GND HDA_RST_VGA# 22
D_EC_SMB_CK1 135 136 VGA_CRT_R VGA_CRT_R 19
SMB_CLK VGA_RED
137 THERM# GND 138
19 VGA_CRT_HSYNC VGA_CRT_HSYNC 139 140 VGA_CRT_G VGA_CRT_G 19
VGA_CRT_VSYNC VGA_HSYNC VGA_GRN
19 VGA_CRT_VSYNC 141 VGA_VSYNC GND 142
19 VGA_DDC_CLK VGA_DDC_CLK 143 144 VGA_CRT_B VGA_CRT_B 19
PCIE_GTX_C_MRX_N15 VGA_DDC_DATA HDA_SDI VGA_BLU
25 PEX_RX15# PRSNT2# 26 19 VGA_DDC_DATA 145 HDA_SDO GND 146
PCIE_GTX_C_MRX_P15 27 28 PCIE_MTX_C_GRX_N15 22 HDA_SDIN3 1 PM@ 2HDA_SDIN3_VGA 147 148 VGA_TZCLK- VGA_TZCLK- 18
PEX_RX15 PEX_TX15# PCIE_MTX_C_GRX_P15 R319 33_0402_5% IGP_UCLK# LVDS_UCLK# VGA_TZCLK+
29 GND PEX_TX15 30 22 HDA_SDOUT_VGA 149 IGP_UCLK LVDS_UCLK 150 VGA_TZCLK+ 18
C PCIE_GTX_C_MRX_N14 31 32 151 152 C
PCIE_GTX_C_MRX_P14 PEX_RX14# GND PCIE_MTX_C_GRX_N14 R516 GND GND
33 PEX_RX14 PEX_TX14# 34 +3VS 1 2 153 DP_L3# LVDS_UTX3# 154
35 36 PCIE_MTX_C_GRX_P14 1K_0402_5% @ 155 156
PCIE_GTX_C_MRX_N13 GND PEX_TX14 DP_L3 LVDS_UTX3 SPDIF_HDMI
37 PEX_RX13# GND 38 31 EC_ACIN 1 2 157 AC/BATT# GND 158 SPDIF_HDMI 34
PCIE_GTX_C_MRX_P13 39 40 PCIE_MTX_C_GRX_N13 159 160 VGA_TZOUT2- VGA_TZOUT2- 18
PEX_RX13 PEX_TX13# PCIE_MTX_C_GRX_P13 D30 @ DP_L2# LVDS_UTX2# VGA_TZOUT2+
41 GND PEX_TX13 42 161 DP_L2 LVDS_UTX2 162 VGA_TZOUT2+ 18
PCIE_GTX_C_MRX_N12 43 44 CH751H-40PT_SOD323-2 163 164
PCIE_GTX_C_MRX_P12 PEX_RX12# GND PCIE_MTX_C_GRX_N12 GND GND VGA_TZOUT1-
45 PEX_RX12 PEX_TX12# 46 1 2 165 DP_L1# LVDS_UTX1# 166 VGA_TZOUT1- 18
47 48 PCIE_MTX_C_GRX_P12 167 168 VGA_TZOUT1+ VGA_TZOUT1+ 18
PCIE_GTX_C_MRX_N11 GND PEX_TX12 R534 DP_L1 LVDS_UTX1
49 PEX_RX11# GND 50 169 GND GND 170
PCIE_GTX_C_MRX_P11 51 52 PCIE_MTX_C_GRX_N11 0_0402_5% 171 172 VGA_TZOUT0- VGA_TZOUT0- 18
PEX_RX11 PEX_TX11# PCIE_MTX_C_GRX_P11 PM@ DP_L0# LVDS_UTX0# VGA_TZOUT0+
53 GND PEX_TX11 54 173 DP_L0 LVDS_UTX0 174 VGA_TZOUT0+ 18
PCIE_GTX_C_MRX_N10 55 56 175 176
PCIE_GTX_C_MRX_P10 PEX_RX10# GND PCIE_MTX_C_GRX_N10 GND GND VGA_TXCLK-
57 PEX_RX10 PEX_TX10# 58 177 DVI_B_CLK LVDS_LCLK# 178 VGA_TXCLK- 18
59 60 PCIE_MTX_C_GRX_P10 179 180 VGA_TXCLK+ VGA_TXCLK+ 18
PCIE_GTX_C_MRX_N9 GND PEX_TX10 DVI_B_CLK LVDS_LCLK
61 PEX_RX9# GND 62 181 DVI_B_HPD/DVI_C_HPD/GND GND 182
PCIE_GTX_C_MRX_P9 63 64 PCIE_MTX_C_GRX_N9 183 184
PEX_RX9 PEX_TX9# PCIE_MTX_C_GRX_P9 DP_AUX# LVDS_LTX3#
65 GND PEX_TX9 66 185 DP_AUX LVDS_LTX3 186
PCIE_GTX_C_MRX_N8 67 68 187 188
PCIE_GTX_C_MRX_P8 PEX_RX8# GND PCIE_MTX_C_GRX_N8 GND DP_HPD VGA_TXOUT2-
69 PEX_RX8 PEX_TX8# 70 189 DVI_B_TX2# LVDS_LTX2#/DVI_C_TX2# 190 VGA_TXOUT2- 18
71 72 PCIE_MTX_C_GRX_P8 191 192 VGA_TXOUT2+ VGA_TXOUT2+ 18
PCIE_GTX_C_MRX_N7 GND PEX_TX8 DVI_B_TX2 LVDS_LTX2/DVI_C_TX2
73 PEX_RX7# GND 74 193 GND GND 194
PCIE_GTX_C_MRX_P7 75 76 PCIE_MTX_C_GRX_N7 195 196 VGA_TXOUT1- VGA_TXOUT1- 18
PEX_RX7 PEX_TX7# PCIE_MTX_C_GRX_P7 DVI_B_TX1# LVDS_LTX1#/DVI_C_LTX1# VGA_TXOUT1+
77 GND PEX_TX7 78 197 DVI_B_TX1 LVDS_LTX1/DVI_C_LTX1 198 VGA_TXOUT1+ 18
PCIE_GTX_C_MRX_N6 79 80 199 200
PCIE_GTX_C_MRX_P6 PEX_RX6# GND PCIE_MTX_C_GRX_N6 GND GND VGA_TXOUT0-
81 PEX_RX6 PEX_TX6# 82 201 DVI_B_TX0# LVDS_LTX0#/DVI_C_LTX0# 202 VGA_TXOUT0- 18
83 84 PCIE_MTX_C_GRX_P6 203 204 VGA_TXOUT0+ VGA_TXOUT0+ 18
PCIE_GTX_C_MRX_N5 GND PEX_TX6 DVI_DET DVI_B_TX0 LVDS_LTX0/DVI_C_LTX0
85 PEX_RX5# GND 86 20,31 DVI_DET 205 DVI_A_HPD GND 206
PCIE_GTX_C_MRX_P5 87 88 PCIE_MTX_C_GRX_N5 20 VGA_DVI_TXC- VGA_DVI_TXC- 207 208 I2CC_SDA I2CC_SDA 18
B PEX_RX5 PEX_TX5# PCIE_MTX_C_GRX_P5 VGA_DVI_TXC+ DVI_A_CLK# DDCC_DAT I2CC_SCL B
89 GND PEX_TX5 90 20 VGA_DVI_TXC+ 209 DVI_A_CLK DDCC_CLK 210 I2CC_SCL 18
PCIE_GTX_C_MRX_N4 91 92 211 212 ENVDD
PEX_RX4# GND GND LVDS_PPEN ENVDD 18
PCIE_GTX_C_MRX_P4 93 94 PCIE_MTX_C_GRX_N4 20 VGA_DVI_TXD2- VGA_DVI_TXD2- 213 214
PEX_RX4 PEX_TX4# PCIE_MTX_C_GRX_P4 VGA_DVI_TXD2+ DVI_A_TX2# LVDS_BL_BRGHT ENBKL
95 GND PEX_TX4 96 20 VGA_DVI_TXD2+ 215 DVI_A_TX2 LVDS_BLEN 216 ENBKL 10,31
PCIE_GTX_C_MRX_N3 97 98 217 218 VGA_DVI_SDATA VGA_DVI_SDATA 20
PCIE_GTX_C_MRX_P3 PEX_RX3# GND PCIE_MTX_C_GRX_N3 VGA_DVI_TXD1- GND DDCB_DAT VGA_DVI_SCLK
99 PEX_RX3 PEX_TX3# 100 20 VGA_DVI_TXD1- 219 DVI_A_TX1# DDCB_CLK 220 VGA_DVI_SCLK 20
101 102 PCIE_MTX_C_GRX_P3 20 VGA_DVI_TXD1+ VGA_DVI_TXD1+ 221 222 +2.5VS
PCIE_GTX_C_MRX_N2 GND PEX_TX3 DVI_A_TX1 2V5RUN
103 PEX_RX2# GND 104 223 GND GND 224
PCIE_GTX_C_MRX_P2 105 106 PCIE_MTX_C_GRX_N2 20 VGA_DVI_TXD0- VGA_DVI_TXD0- 225 226 +3VS
PEX_RX2 PEX_TX2# PCIE_MTX_C_GRX_P2 VGA_DVI_TXD0+ DVI_A_TX0# 3V3RUN
107 GND PEX_TX2 108 20 VGA_DVI_TXD0+ 227 DVI_A_TX0 3V3RUN 228
229 GND 3V3RUN 230

231 GND GND 232

QUASA_CA0481-230N00
CONN@ QUASA_CA0481-230N00 +3VS
CONN@

2
+2.5VS +5VS

G
1 3 D_EC_SMB_DA1
31,40 EC_SMB_DA1

S
1 1 Q52
+1.05VS +1.05VS +1.05VS +1.05VS +1.05VS C72 C512 2N7002_SOT23
PM@

2
0.1U_0402_16V4Z

G
1 1 1 1 1 PM@ 2 2
C598 C599 C600 C601 C602 0.1U_0402_16V4Z 1 3 D_EC_SMB_CK1
31,40 EC_SMB_CK1
@ @ @ @ @ PM@

S
A A
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z Q53
2 2 2 2 2 2N7002_SOT23
PM@

For Return Path between GND and 1.05V Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 17 of 50
5 4 3 2 1
 5 4 3 2 1

D +3VS D

LCD POWER CIRCUIT

5
U24
+LCDVDD

P
NC
+3V +3VS INVTPWM 4 Y A 2 DPST_PWM 10
W=60mils

G
R274 NC7SZ14P5X_NL_SC70-5

3
1
300_0603_5% 1 @
R278 C371
100K_0402_5%

3 2
4.7U_0805_10V4Z

2
2

G
R280

2
Q33B

3
S
G +3VS 1 2 INVTPWM 1 3
2N7002DW-T/R7_SOT363-6 5 2 1 2 Q32

S
R277 1K_0402_5% AO3413_SOT23-3 10K_0402_5%
D
1
4

1
Q34

6
C372 +LCDVDD @
W=60mils 2N7002_SOT23 For GMCH DPST
GM@ Q33A 0.047U_0402_16V7K @
R276 1 2
10 GMCH_ENVDD 2 0_0402_5% 2
PM@ 2N7002DW-T/R7_SOT363-6 1 1
R279 1 2 0_0402_5% C370 C364
17 ENVDD

1
1

4.7U_0805_10V4Z 0.1U_0402_16V4Z
R275 2 2
100K_0402_5%
2

C C
TXOUT0- 1 4 VGA_TXOUT0-
VGA_TXOUT0- 17
TXOUT0+ 2 3 VGA_TXOUT0+
VGA_TXOUT0+ 17
RP2 PM@ 0_0404_4P2R_5%
TXOUT1- 1 4 VGA_TXOUT1-
VGA_TXOUT1- 17
TXOUT1+ 2 3 VGA_TXOUT1+
VGA_TXOUT1+ 17
RP4 PM@ 0_0404_4P2R_5%
TXOUT2- 1 4 VGA_TXOUT2-
+3VS VGA_TXOUT2- 17
TXOUT2+ 2 3 VGA_TXOUT2+
VGA_TXOUT2+ 17
RP6 PM@ 0_0404_4P2R_5%
TXCLK- 1 4 VGA_TXCLK-
VGA_TXCLK- 17

1
TXCLK+ 2 3 VGA_TXCLK+
VGA_TXCLK+ 17
R281 RP8 PM@ 0_0404_4P2R_5%
TZOUT0- 1 4 VGA_TZOUT0-
VGA_TZOUT0- 17
4.7K_0402_5% TZOUT0+ 2 3 VGA_TZOUT0+
D18 VGA_TZOUT0+ 17
2 RP10 PM@ 0_0404_4P2R_5%
BKOFF# 1 2 DISPOFF# TZOUT1- 1 4 VGA_TZOUT1-
31 BKOFF# VGA_TZOUT1- 17
TZOUT1+ 2 3 VGA_TZOUT1+
VGA_TZOUT1+ 17
RP12 PM@ 0_0404_4P2R_5%
+INVPWR_B+ CH751H-40PT_SOD323-2 TZOUT2- VGA_TZOUT2-
1 4 VGA_TZOUT2- 17
TZOUT2+ 2 3 VGA_TZOUT2+
VGA_TZOUT2+ 17
L16 2 1 B+ RP14 PM@ 0_0404_4P2R_5%
W=40mils KC FBM-L11-201209-221LMAT_0805 TZCLK- 1 4 VGA_TZCLK-
VGA_TZCLK- 17
DAC_BRIG 1 2 TZCLK+ 2 3 VGA_TZCLK+
VGA_TZCLK+ 17
L15 2 1 C367 220P_0402_50V7K RP16 PM@ 0_0404_4P2R_5%
KC FBM-L11-201209-221LMAT_0805 INVTPWM 1 2
1 1 C366 220P_0402_50V7K
C368 C361 DISPOFF# 1 2
C365 220P_0402_50V7K I2CC_SCL 1 4 GMCH_LCD_CLK GMCH_LCD_CLK 10
680P_0402_50V7K 68P_0402_50V8J I2CC_SDA 2 3 GMCH_LCD_DATA GMCH_LCD_DATA 10
2 2 RP1 GM@ 0_0404_4P2R_5%

B B

LCD/PANEL BD. Conn. TXOUT0- 2 3 GMCH_TXOUT0-

GMCH_TXOUT0- 10
TXOUT0+ 1 4 GMCH_TXOUT0+
GMCH_TXOUT0+ 10
RP3 GM@ 0_0404_4P2R_5%
TXOUT1- 2 3 GMCH_TXOUT1-
GMCH_TXOUT1- 10
JLVDS1 TXOUT1+ 1 4 GMCH_TXOUT1+
GMCH_TXOUT1+ 10
42 41 DAC_BRIG RP5 GM@ 0_0404_4P2R_5%
GND GND DAC_BRIG 31
+INVPWR_B+ 40 39 TXOUT2- 2 3 GMCH_TXOUT2-
40 39 GMCH_TXOUT2- 10
38 37 INVTPWM R272 1 2 0_0402_5% TXOUT2+ 1 4 GMCH_TXOUT2+
38 37 INVT_PWM 31 GMCH_TXOUT2+ 10
+3VS 36 35 DISPOFF# RP7 GM@ 0_0404_4P2R_5%
I2CC_SCL 36 35 TXCLK- GMCH_TXCLK-
17 I2CC_SCL 34 34 33 33 +LCDVDD 2 3 GMCH_TXCLK- 10
I2CC_SDA 32 31 TXCLK+ 1 4 GMCH_TXCLK+
17 I2CC_SDA 32 31 GMCH_TXCLK+ 10
30 29 W=60mils RP9 GM@ 0_0404_4P2R_5%
TZOUT0- 30 29 TZOUT0- GMCH_TZOUT0-
28 28 27 27 2 3 GMCH_TZOUT0- 10
TZOUT0+ 26 25 TXOUT0- +LCDVDD TZOUT0+ 1 4 GMCH_TZOUT0+
26 25 +3VS GMCH_TZOUT0+ 10
24 23 TXOUT0+ RP11 GM@ 0_0404_4P2R_5%
TZOUT1+ 24 23 TZOUT1- GMCH_TZOUT1-
22 22 21 21 2 3 GMCH_TZOUT1- 10
TZOUT1- 20 19 TXOUT1- TZOUT1+ 1 4 GMCH_TZOUT1+
20 19 GMCH_TZOUT1+ 10
18 17 TXOUT1+ 1 1 1 RP13 GM@ 0_0404_4P2R_5%
TZOUT2+ 18 17 C362 C369 C363 TZOUT2- GMCH_TZOUT2-
16 16 15 15 2 3 GMCH_TZOUT2- 10
TZOUT2- 14 13 TXOUT2+ TZOUT2+ 1 4 GMCH_TZOUT2+
14 13 GMCH_TZOUT2+ 10
12 11 TXOUT2- 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z RP15 GM@ 0_0404_4P2R_5%
TZCLK- 12 11 2 2 2 TZCLK- GMCH_TZCLK-
10 10 9 9 2 3 GMCH_TZCLK- 10
TZCLK+ 8 7 TXCLK- TZCLK+ 1 4 GMCH_TZCLK+
8 7 GMCH_TZCLK+ 10
0_0402_5% 6 5 TXCLK+ RP17 GM@ 0_0404_4P2R_5%
6 5
23 USB20_N6
R271 1 2USB20_CMOS_N6 4 4 3 3
R270 1 2USB20_CMOS_P6 2 1 +3VS
23 USB20_P6 2 1
0_0402_5%
ACES_88242-4001
CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 18 of 50
5 4 3 2 1
 A B C D E

CRT Connector D23 D22 D21

W=40mils
+5VS +R_CRT_VCC +CRT_VCC
DAN217_SC59 DAN217_SC59 DAN217_SC59
D5 F1 W=40mils

1
2 1 1 2

RB491D_SC59-3 1.1A_6VDC_FUSE
1
C63

3
0.1U_0402_16V4Z
2
1
+3VS 1

CRT_R 1 2 CRT_R_1 1 2 CRT_R_2 JCRT1

L21 FCM2012C-800_0805 L22 FCM2012C-800_0805 6
GM@ 11
CRT_G 1 2 CRT_G_1 1 2 CRT_G_2 1
L19 FCM2012C-800_0805 L20 FCM2012C-800_0805 7
GM@ 12
CRT_B 1 2 CRT_B_1 1 2 CRT_B_2 2
L17 FCM2012C-800_0805 L18 FCM2012C-800_0805 8

1
GM@ 13

1
R318 R312 1 1 1 1 1 1 1 1 1 3
R304 C429 C421 C405 C432 C428 C419 9
C430 C422 C406 14
150_0402_1% GM@ GM@ GM@ 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 4

2
2 2 2 GM@ 2 GM@ 2 GM@ 2 GM@ 2 GM@ 2 2 GM@ 10 16

2
150_0402_1% 10P_0402_50V8J 10P_0402_50V8J 22P_0402_50V8J 15 17
150_0402_1% 22P_0402_50V8J 22P_0402_50V8J 1 5
10P_0402_50V8J change to 12pf for Discrete C389
SUYIN_070549FR015S208CR
1 2 CRT_HSYNC_2 CONN@
L4 10_0603_5% 2
CRT_DET# 23,38
change to 15pf for Discrete 100P_0402_50V8J
1 2 CRT_VSYNC_2
L3 10_0603_5% 1 1 DSUB_12

2
+CRT_VCC C58
L3, L4 10_0603_5%
C66 1 R293
1 2 2 1
PN: SD013100A80 10P_0402_50V8J 10P_0402_50V8J 100K_0402_5%
C67 0.1U_0402_16V4Z R29 10K_0402_5% 2 2
DSUB_15

1
5

1
2 U4 C71 2 2
68P_0402_50V8J 1

OE#
CRT_HSYNC 2 4 CRT_HSYNC_1 2 1
A Y D_CRT_HSYNC 38
R544 C22 +CRT_VCC

G
JAL90@ 0_0402_5% 68P_0402_50V8J
74AHCT1G125GW_SOT353-5 2

3
+CRT_VCC

1 2
C62 0.1U_0402_16V4Z

1
U3

OE#
CRT_VSYNC 2 4 CRT_VSYNC_1 2 1
A Y D_CRT_VSYNC 38
R545

G
JAL90@ 0_0402_5%
74AHCT1G125GW_SOT353-5

3
+CRT_VCC

Place closed to chipset

+3VS pull-up 10k on AMD M82M MXM side

1
pull-up 2.2k on GPU side
R30 R22 1 2 R320
4.7K_0402_5% 4.7K_0402_5% PM@ 0_0402_5% VGA_DDC_DATA 17

2
3 3

G
NOTE: L : A-->B1
R321 GM@ 0_0402_5%
R43 1 GM@ 2 30.1_0402_1% CRT_VSYNC H: A-->B2 DSUB_12 1 3 2 1
10 GMCH_CRT_VSYNC 38 D_DDC_DATA GMCH_CRT_DATA 10

S
R50 +5VS
10 GMCH_CRT_HSYNC 1 GM@ 2 30.1_0402_1% CRT_HSYNC Q50

2
2N7002_SOT23

G
R322 1 GM@ 2 0_0402_5% CRT_B_S U28
10 GMCH_CRT_B
16 DSUB_15 1 3 2 1
R327 1 GM@ 0_0402_5% CRT_G_S VCC 38 D_DDC_CLK R326 GMCH_CRT_CLK 10
2 1

S
10 GMCH_CRT_G 20,38 EC_DOCKIN#_S0 SEL
15 2 Q51 GM@ 0_0402_5%
OE# 1B1 D_CRT_R 38
R329 1 GM@ 2 0_0402_5% CRT_R_S 5 2N7002_SOT23
10 GMCH_CRT_R 2B1 D_CRT_G 38
3B1 11 D_CRT_B 38 1 2 R325 VGA_DDC_CLK 17
CRT_R_S 4 14 PM@ 0_0402_5%
CRT_G_S 1A 4B1
7 2A
CRT_B_S 9 pull-up 2.2k on GPU side
3A CRT_R
12 4A 1B2 3
6 CRT_G pull-up 10k on AMD M82M MXM side
R42 2B2
17 VGA_CRT_VSYNC 1 2 PM@ 0_0402_5% CRT_VSYNC
3B2 10 CRT_B
4B2 13
R49 1 2 PM@ 0_0402_5% CRT_HSYNC 8
17 VGA_CRT_HSYNC GND
R323 1 2 PM@ 0_0402_5% CRT_B_S FSAV330MTC_TSSOP16
17 VGA_CRT_B
JAL90@
R328 1 2 PM@ 0_0402_5% CRT_G_S
17 VGA_CRT_G
R330 1 2 PM@ 0_0402_5% CRT_R_S
17 VGA_CRT_R
CRT_B_S R518 1 JAW50@2 0_0402_5% CRT_B

CRT_G_S R519 1 JAW50@2 0_0402_5% CRT_G

4 4
CRT_R_S R520 1 JAW50@2 0_0402_5% CRT_R

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 19 of 50
A B C D E
 5 4 3 2 1

DDC to Docking +HDMI_5V_OUT +HDMI_5V_OUT

DDC to HDMI CONN
3.3V Level JHDMI1
3.3V Level HDMI_HPD 19
EC_DOCKIN HP_DET
38 EC_DOCKIN +HDMI_5V_OUT 18 +5V

1
EC_DOCKIN#_S0 17
19,38 EC_DOCKIN#_S0 DDC/CEC_GND
R52 R51 R67 R72 HDMI_SDATA 16
R542 1 JAL90PM@ SDA
+3VS 2 4.7K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% HDMI_SCLK 15 SCL

2
G

G
D +5VS R548 1 @ 2 2.2K_0402_5% JAL90PM@ JAL90PM@ JAL90PM@ JAL90PM@ 14 D
Reserved
13

2
VGA_DVI_SCLK VGA_DVI_SCLK HDMI_SCLK HDMI_R_CK- CEC
17 VGA_DVI_SCLK 3 1 D_DVI_SCLK 38 3 1 12 CK- GND 20

D
11 CK_shield GND 21
Q46 Q5 HDMI_R_CK+ 10 22
CK+ GND

2
G

G
BSH111_SOT23 BSH111_SOT23 HDMI_R_D0- 9 23
JAL90@ JAL90@ D0- GND
8 D0_shield
17 VGA_DVI_SDATA VGA_DVI_SDATA 3 1 D_DVI_SDATA 38 VGA_DVI_SDATA 3 1 HDMI_SDATA HDMI_R_D0+ 7
HDMI_R_D1- D0+

D
6 D1-
+3VS R543 1 JAL90PM@
2 4.7K_0402_5% Q47 Q3 5
R549 1 @ D1_shield
+5VS 2 2.2K_0402_5% BSH111_SOT23 BSH111_SOT23 Place closed to JHDMI1 HDMI_R_D1+ 4 D1+
JAL90@ JAL90@ HDMI_R_D2- 3 D2-
2 D2_shield
HDMI_R_D2+ 1 D2+
TYCO_1939864-1
MP:Update HDMI Hot Plug DET circuit. CONN@

+HDMI_5V_OUT 1 2 D_DVI_DET 38
R344 JAL90@ 0_0402_5%
HDMI_HPD
1
C440 2 JAL90@ 1 +3VS

2
JAL90@ R332 R336 +HDMI_5V_OUT
1
5

0.1U_0402_16V4Z U30 2.2K_0402_5% 100K_0402_5% C439

2 JAL90@ JAL90@ D6 F2
W=40mils
P

OE#

2 A Y 4 1 JAL90PM@
2 DVI_DET 17,31 0.1U_0402_16V4Z +5VS 2 1 +HDMI_5V 1 2 HDMI_CLK- 1 2 HDMI_R_CK-
R574 0_0402_5% 2 R351 JAL90@ 0_0402_5%
1

1
G

RB491D_SC59-3 1.1A_6VDC_FUSE
C 1 2 OE JAL90@ JAL90@ C443 L24 C
3

JAL90@ R569 @ 0_0402_5% 0.1U_0402_16V4Z 1 2

74AHCT1G125GW_SOT353-5 JAL90@ 2 1 2
EC_DVI_DET 31
4 4 3 3
@ WCM-2012-900T_0805
+HDMI_5V_OUT
U40 HDMI_CLK+ HDMI_R_CK+
1 2
VGA_DVI_SCLK 2 8 R354 JAL90@ 0_0402_5%
VGA_DVI_SDATA 1A VCC D_DVI_SCLK +3VS
5 2A 1B 3
EC_DOCKIN#_S0 1 6 D_DVI_SDATA
1OE# 2B HDMI_TX0- HDMI_R_D0-
7 2OE# GND 4 1 2

2
R358 JAL90@ 0_0402_5%
SN74CBTD3306CPWR_TSSOP8
@ D19 L25
+HDMI_5V_OUT SS1040_SOD123 1 2
U41 JAL90@ 1 2

1
VGA_DVI_SCLK 2 8
VGA_DVI_SDATA 1A VCC HDMI_SCLK +3VS_D80
5 2A 1B 3 4 4 3 3
EC_DOCKIN 1 6 HDMI_SDATA
1OE# 2B @ WCM-2012-900T_0805
7 2OE# GND 4

11
15
24
36
48

22
1 1

2
6
SN74CBTD3306CPWR_TSSOP8 U27 C431 C427 HDMI_TX0+ 1 2 HDMI_R_D0+
@ JAL90@ JAL90@ R364 JAL90@ 0_0402_5%

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7

AVDD
0.1U_0402_16V4Z
VGA_DVI_TXC+ 2 2
17 VGA_DVI_TXC+ 4 D0+
+3VS 1 2 VGA_DVI_TXC- 5 0.1U_0402_16V4Z HDMI_TX1- 1 2 HDMI_R_D1-
17 VGA_DVI_TXC- D0-
R310 JAL90@ 4.7K_0402_5% VGA_DVI_TXD0+ 7 R365 JAL90@ 0_0402_5%
B 17 VGA_DVI_TXD0+ D1+ B
1 2 MS VGA_DVI_TXD0- 8 25 HDMI_TX2-
17 VGA_DVI_TXD0- D1- D3-_B
R311 @ 0_0402_5% VGA_DVI_TXD1+ 9 26 HDMI_TX2+ L26
17 VGA_DVI_TXD1+ D2+ D3+_B
VGA_DVI_TXD1- 10 28 HDMI_TX1- 1 2
17 VGA_DVI_TXD1- D2- D2-_B 1 2
+3VS 2 1 JAL90@ OE
17 VGA_DVI_TXD2+
VGA_DVI_TXD2+ 12 D3+ D2+_B 29 HDMI_TX1+
D20 CH751H-40PT_SOD323-2 VGA_DVI_TXD2- 13 31 HDMI_TX0-
17 VGA_DVI_TXD2- D3- D1-_B
1 2 32 HDMI_TX0+ 4 3
R305 JAL90@ 4.7K_0402_5% @ D1+_B HDMI_CLK- 4 3
T5 PAD 16 SEL_OUT D0-_B 34
PAD @ 55 35 HDMI_CLK+ @ WCM-2012-900T_0805
T3 SEL_IN D0+_B
+3VS 1 2 19 HDMI_TX1+ 1 2 HDMI_R_D1+
14,15,16 D_CK_SCLK SCL/S3
R301 @ 4.7K_0402_5% 20 37 D_DVI_TXD2- 38 R367 JAL90@ 0_0402_5%
14,15,16 D_CK_SDATA SDA/S2 D3-_A
1 2 A2 38 D_DVI_TXD2+ 38
R307 JAL90@ 0_0402_5% MS D3+_A
1 MS D2-_A 40 D_DVI_TXD1- 38
+3VS 1 2 PAD @ 17 41 D_DVI_TXD1+ 38 HDMI_TX2- 1 2 HDMI_R_D2-
T6 TEST_OUT D2+_A
R300 @ 4.7K_0402_5% 54 43 D_DVI_TXD0- 38 R372 JAL90@ 0_0402_5%
A3 OE TEST_IN D1-_A
1 2 56 OE D1+_A 44 D_DVI_TXD0+ 38
R306 JAL90@ 0_0402_5% 46 D_DVI_TXC- 38 L27
A0 D0-_A
49 A0/S4 D0+_A 47 D_DVI_TXC+ 38 1 1 2 2
A1 50
A2 A1/S5
+3VS 1 2 51 A2/S6 NC 18
R303 @ 4.7K_0402_5% A3 52 57 4 3
A0 A3/S7 T-pad 4 3
1 2
VSS10

AVSS

R309 JAL90@ 0_0402_5% @ WCM-2012-900T_0805

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

NOTE: L : D-->A
+3VS 1 2
R302 @ 4.7K_0402_5% H: D-->B HDMI_TX2+ 1 2 HDMI_R_D2+
1 2 A1 PI3HDMI412ADZBE_TQFN56_8X8 R373 JAL90@ 0_0402_5%
3
14
21
27
30
33
39
42
45
53

23

R308 JAL90@ 0_0402_5% JAL90@

A A
SMBus Address: 1100 000X (b)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 20 of 50
5 4 3 2 1
 5 4 3 2 1

DMI for ESI-compatible operation

+3VS
Low= DMI for ESI-compatible operation
PCI_GNT#1 High= Default* (Internal pull-up)
RP46
1 8 PCI_DEVSEL#
2 7 PCI_FRAME#
D 3 6 PCI_REQ#1 D
4 5 PCI_REQ#2
U9B
8.2K_1206_8P4R_5% D11 F1 PCI_REQ#0
AD0 REQ0# PCI_GNT#0
C8 AD1 GNT0# G4
RP43 PCI_REQ#1
1 8 PCI_PLOCK#
D9
E12
AD2 PCI REQ1#/GPIO50 B6
A7 PCI_GNT#1 @
AD3 GNT1#/GPIO51 PAD T16
2 7 PCI_IRDY# E9 F13 PCI_REQ#2
PCI_PERR# AD4 REQ2#/GPIO52 PCI_GNT#2 @
3 6 C9 AD5 GNT2#/GPIO53 F12 PAD T25
4 5 PCI_PIRQB# E10 E6 PCI_REQ#3
AD6 REQ3#/GPIO54 PCI_GNT#3
B7 AD7 GNT3#/GPIO55 F6
8.2K_1206_8P4R_5% C7 AD8 PCI_CBE#0 @
C5 AD9 C/BE0# D8 PAD T20
G11 B4 PCI_CBE#1 @ PAD
AD10 C/BE1# T18
F8 D6 PCI_CBE#2 @ PAD
AD11 C/BE2# T22
F11 A5 PCI_CBE#3 @ PAD
+3VS AD12 C/BE3# T17
E7 AD13
A3 D3 PCI_IRDY#
RP47 AD14 IRDY# PCI_PAR @
D2 AD15 PAR E3 PAD T23
1 8 PCI_PIRQH# F10 R1 PCI_RST#
AD16 PCIRST# PCI_RST# 30
2 7 PCI_PIRQE# D5 C6 PCI_DEVSEL#
PCI_REQ#0 AD17 DEVSEL# PCI_PERR#
3 6
PCI_PIRQG#
D10 AD18 PERR# E4
PCI_PLOCK#
Place closely pin B10
4 5 B3 AD19 PLOCK# C2
F7 J4 PCI_SERR#
8.2K_1206_8P4R_5% AD20 SERR# PCI_STOP# CLK_PCI_ICH
C3 AD21 STOP# A4
F3 F5 PCI_TRDY#
AD22 TRDY#

2
RP48 F4 D7 PCI_FRAME#
PCI_PIRQF# AD23 FRAME#
1 8 C1 AD24
2 7 PCI_SERR# G7 C14 PLT_RST# R356
AD25 PLTRST# PLT_RST# 8,23,26,27,31
C 3 6 PCI_PIRQA# H7 D4 CLK_PCI_ICH 10_0402_5% C
AD26 PCICLK CLK_PCI_ICH 16
4 5 PCI_PIRQC# D1 R2 @

1
AD27 PME#
G5 AD28
8.2K_1206_8P4R_5% H6 1
AD29 C450
G1 AD30
RP36 H3 10P_0402_50V8J
PCI_STOP# AD31 @
1 8
PCI_PIRQD# 2
2 7
PCI_REQ#3
3
4
6
5 PCI_TRDY# PCI_PIRQA# J5
Interrupt I/F H4 PCI_PIRQE#
PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF#
E1 PIRQB# PIRQF#/GPIO3 K6
8.2K_1206_8P4R_5% PCI_PIRQC# J6 F2 PCI_PIRQG#
PCI_PIRQD# PIRQC# PIRQG#/GPIO4 PCI_PIRQH#
C4 PIRQD# PIRQH#/GPIO5 G2
ICH9-M ES_FCBGA676

A16 Swap Override Strap

Low= A16 swap override Enable
PCI_GNT#3 High= Default*

R345 1 2 1K_0402_5% PCI_GNT#3

@
B B

+3VS

5
U7
Boot BIOS Strap PLT_RST# 2 B

P
Y 4 PLT_RST_BUF# 29
PCI_GNT#0 SPI_CS#1 Boot BIOS Loaction 1 A

1
NC7SZ08P5X_NL_SC70-5

3
R37
0 1 SPI 100K_0402_5%

1 0 PCI

2
+3VS

1 1 LPC*

5
U6
2 B

P
1
Y 4 2
R35
1
100_0402_5%
PLTRST_VGA# 17 For VGA/B
A
G
R350 1 2 1K_0402_5% PCI_GNT#0 PM@

1
@ NC7SZ08P5X_NL_SC70-5
3

PM@ R36
R337 1 2 1K_0402_5% 100K_0402_5%
SPI_CS#1 23
@ PM@

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 21 of 50
5 4 3 2 1
 5 4 3 2 1

+RTCVCC CMOS Settings R347 TPM Settings R374

C130
18P_0402_50V8J Clear CMOS SHORT Clear ME RTC Registers SHORT
2 1 ICH_RTCX1 +1.05VS

1
Keep CMOS OPEN Keep ME RTC Registers OPEN

10M_0402_5%
R359 X1 H_DPRSTP# 2 1

1
3 4 R166 @ 56_0402_5%
NC OUT

R66
1M_0402_5% H_DPSLP# 2 1
32.768KHZ_12.5P_MC-306 2 1 R165 @ 56_0402_5%
2

SM_INTRUDER# NC IN
C131 U9A

2
D 18P_0402_50V8J C23 K5 LPC_AD0 D
RTCX1 FWH0/LAD0 LPC_AD0 31
2 1 ICH_RTCX2 C24 K4 LPC_AD1
+RTCVCC RTCX2 FWH1/LAD1 LPC_AD1 31
L6 LPC_AD2
FWH2/LAD2 LPC_AD2 31
+RTCVCC 1 2 ICH_RTCRST# A25 K2 LPC_AD3
RTCRST# FWH3/LAD3 LPC_AD3 31
R348 +RTCVCC 1 2 ICH_SRTCRST# F20
20K_0402_5% R349 SM_INTRUDER# SRTCRST# LPC_FRAME#
C22 INTRUDER# FWH4/LFRAME# K3 LPC_FRAME# 31
1

20K_0402_5%

RTC

LPC
R355 close to RAM door close to RAM door ICH_INTVRMEN B22 J3
332K_0402_1% INTVRMEN LDRQ0#
A22 LAN100_SLP LDRQ1#/GPIO23 J1
1 2 1 2 R384 2 1 10K_0402_5% +3VS
R347 @ R374 @ E25 N7 EC_GA20
EC_GA20 31
2

10K_0603_5% 10K_0603_5% GLAN_CLK A20GATE H_A20M#

A20M# AJ27 H_A20M# 4
ICH_INTVRMEN C444 C464 C13
1U_0603_10V6K 1U_0603_10V6K LAN_RSTSYNC DPRSTP# R153 1 0_0402_5% H_DPRSTP#
High = Internal VR Enable DPRSTP# AJ25
DPSLP# R150 1
2
0_0402_5% H_DPSLP#
H_DPRSTP# 5,8,46
1 2 1 2 F14 LAN_RXD0 DPSLP# AE23 2 H_DPSLP# 5
G13 LAN_RXD1
D14 AJ26 FERR# 1 2 H_FERR#
LAN_RXD2 FERR# H_FERR# 4

LAN / GLAN
R154 56_0402_5%
+3VS D13 AD22 H_PWRGOOD 2 1
LAN_TXD_0 CPUPWRGD H_PWRGOOD 5 +1.05VS
D12 R167 56_0402_5%
LAN_TXD_1 H_IGNNE#
E13 LAN_TXD_2 IGNNE# AF25 H_IGNNE# 4
1

R157 PROJECT_ID2 B10 AE22 H_INIT# 2 1

GPIO56 INIT# H_INIT# 4 +3VS
AG25 H_INTR R378 10K_0402_5%

CPU
INTR H_INTR 4
10K_0402_5% +1.5VS_PCIE_ICH 1 2 GLAN_COMP B28 L3 EC_KBRST#
GLAN_COMPI RCIN# EC_KBRST# 31
R62 24.9_0402_1% B27
2

HDA_BITCLK_ICH GLAN_COMPO H_NMI

33 HDA_BITCLK_MDC 1 2 NMI AF23 H_NMI 4
SATA_LED# R412 33_0402_5% AF6 AF24 H_SMI#
HDA_BIT_CLK SMI# H_SMI# 4
33 HDA_SYNC_MDC 1 2 HDA_SYNC_ICH AH4 R258 need to place within 2" of ICH9M
R414 33_0402_5% HDA_SYNC H_STPCLK#
C
STPCLK# AH27 H_STPCLK# 4 R257 must be place within 2" of R258 w/o stub. C
1 2 HDA_RST_ICH# AE7
33 HDA_RST_MDC# HDA_RST#
R419 33_0402_5% AG26 THRMTRIP_ICH# R155 1 2 54.9_0402_1% H_THERMTRIP#
+3V THRMTRIP# H_THERMTRIP# 4,8
34 HDA_SDIN0 AF4 HDA_SDIN0
33 HDA_SDIN1 AG4 HDA_SDIN1 TP12 AG27 2 1 +1.05VS
8 HDA_SDIN2 AH3 R168 56_0402_5%
HDA_SDIN2
AE5

IHDA
17 HDA_SDIN3 HDA_SDIN3
1

SATA4RXN AH11
R61 1 2 HDA_SDOUT_ICH AG5 AJ11
33 HDA_SDOUT_MDC HDA_SDOUT SATA4RXP
JAL90@ R413 33_0402_5% AG12
10K_0402_5% SATA4TXN
AG7 HDA_DOCK_EN#/GPIO33 SATA4TXP AF12
AE8
2

HDA_DOCK_RST#/GPIO34
PROJECT_ID2 32 SATA_LED# SATA_LED# AG8 SATALED#
SATA5RXN AH9
25 SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 AJ16 AJ9
SATA0RXN SATA5RXP
1

SATA for HDD 25 SATA_DTX_C_IRX_P0 SATA_DTX_C_IRX_P0 AH16 AE10

R532 SATA_ITX_DRX_N0 SATA0RXP SATA5TXN
AF17 SATA0TXN SATA5TXP AF10
JAW50@ SATA_ITX_DRX_P0 AG17
10K_0402_5% SATA0TXP CLK_PCIE_SATA#
SATA_CLKN AH18 CLK_PCIE_SATA# 16

SATA
25 SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_N1 AH13 AJ18 CLK_PCIE_SATA
CLK_PCIE_SATA 16
2

SATA_DTX_C_IRX_P1 SATA1RXN SATA_CLKP SATARBIAS

SATA for ODD 25 SATA_DTX_C_IRX_P1
SATA_ITX_DRX_N1
AJ13 SATA1RXP SATARBIAS# AJ7
R156 1
AG14 SATA1TXN SATARBIAS AH7 2 24.9_0402_1%
SATA_ITX_DRX_P1 AF14 10mils width less than 500mils
SATA1TXP

ICH9-M ES_FCBGA676

B HDA_BITCLK_ICH B
34 HDA_BITCLK_AUDIO 1
R420
2
33_0402_5%
close ICH9
34 HDA_SYNC_AUDIO 1 2 HDA_SYNC_ICH SATA_ITX_DRX_N0 1 2 SATA_ITX_C_DRX_N0
R422 33_0402_5% C521 0.01U_0402_16V7K SATA_ITX_C_DRX_N0 25
HDA for AUDIO HDA_RST_ICH# SATA_ITX_DRX_P0 SATA_ITX_C_DRX_P0
34 HDA_RST_AUDIO# 1 2 1 2 SATA_ITX_C_DRX_P0 25
R407 33_0402_5% C520 0.01U_0402_16V7K
34 HDA_SDOUT_AUDIO 1 2 HDA_SDOUT_ICH
R421 33_0402_5%
SATA_ITX_DRX_N1 1 2 SATA_ITX_C_DRX_N1
C518 0.01U_0402_16V7K SATA_ITX_C_DRX_N1 25
JAL90GM@
1 2 HDA_BITCLK_ICH SATA_ITX_DRX_P1 1 2 SATA_ITX_C_DRX_P1
8 HDA_BITCLK_MCH SATA_ITX_C_DRX_P1 25
R408 33_0402_5% C517 0.01U_0402_16V7K
8 HDA_SYNC_MCH JAL90GM@
1 2 HDA_SYNC_ICH
R410 33_0402_5%
MAINPWON 40,41
HDA for GMCH JAL90GM@
1 2 HDA_RST_ICH#
8 HDA_RST_MCH#
R411 33_0402_5%
8 HDA_SDOUT_MCH JAL90GM@
1 2 HDA_SDOUT_ICH R164

1
R409 33_0402_5% @ 330_0402_5% C
+1.05VS 1 2 2 Q8
B
PM@ 1 2 HDA_BITCLK_ICH E 2SC2411K_SOT23
17 HDA_BITCLK_VGA

3
R425 33_0402_5% @
17 HDA_SYNC_VGA PM@ 1 2 HDA_SYNC_ICH
+VCC_HDA_ICH R424 33_0402_5% H_THERMTRIP#
HDA for VGA PM@ HDA_RST_ICH#
17 HDA_RST_VGA# 1 2
R423 1K_0402_5%
17 HDA_SDOUT_VGA PM@ 1 2 HDA_SDOUT_ICH
R406 R426 33_0402_5%
A
1K_0402_5% Flash Descriptor Security Override Strap A
@ Low= Descriptor Security override
XOR Chain Entrance Strap GPIO33
HDA_SDOUT_ICH High= Default* (Internal pull-up)
ICH_TP3 HDA_SDOUT Description
ICH_TP3 23
0 0 RSVD Security Classification Compal Secret Data Compal Electronics, Inc.
R65 0 1 Enter XOR Chain 2007/09/20 2008/09/20 Title
1K_0402_5%
Issued Date Deciphered Date
@ 1 0 Normal Operation THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1 1 Set PCIE port config bit 1 Custom I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 22 of 50
5 4 3 2 1
 5 4 3 2 1

+3VS
Place closely pin B2 Place closely pin AC1
1 2 SERIRQ U9C
R385 10K_0402_5% 16,29,30 ICH_SMBCLK ICH_SMBCLK G16 AH23 PROJECT_ID1 CLK_ICH_48M CLK_ICH_14M
PM_CLKRUN# ICH_SMBDATA SMBCLK SATA0GP/GPIO21 PROJECT_ID0
R379
1 2
8.2K_0402_5%
16,29,30 ICH_SMBDATA
LINKALERT#
A13 SMBDATA SMB SATA1GP/GPIO19 AF19
R401 1 2 10K_0402_5%

SATA
GPIO
E17 LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36 AE21

1
1 2 EC_THERM# ICH_SMLINK0 C17 AD20
R151 8.2K_0402_5% ICH_SMLINK1 SMLINK0 SATA5GP/GPIO37 R400 R81
B18 SMLINK1
1 2 H_STP_PCI# H1 CLK_ICH_14M 10_0402_5% 10_0402_5%
CLK14 CLK_ICH_14M 16
R47 @ 10K_0402_5% EC_SWI# CLK_ICH_48M @ @
1 2 H_STP_CPU# 31 EC_SWI# F19 RI# clocks CLK48 AF3 CLK_ICH_48M 16

2
R343 @ 10K_0402_5% PAD @ SUS_STAT# R4 P1 SUS_CLK PAD 1 1
T26 SUS_STAT#/LPCPD# SUSCLK T27
1 2 SB_SPKR XDP_DBRESET# G19 @ C509 C175
4 XDP_DBRESET# SYS_RESET#
R380 @ 1K_0402_5% C16 PM_SLP_S3# 10P_0402_50V8J 10P_0402_50V8J
D SLP_S3# PM_SLP_S3# 31 D
1 2 CR_WAKE# PM_SYNC# M6 E16 PM_SLP_S4# @ @
8 PM_SYNC# PMSYNC#/GPIO0 SLP_S4# PM_SLP_S4# 31 2 2
R149 10K_0402_5% G17 PM_SLP_S5#

SYS / GPIO
SLP_S5# PM_SLP_S5# 31
1 2 ICH_SPI_MOSI EC_LID_OUT# A17
31 EC_LID_OUT# SMBALERT#/GPIO11
R41 @ 1K_0402_5% C10 S4_STATE#
OCP# H_STP_PCI# S4_STATE#/GPIO26
1 2 16 H_STP_PCI# A14 STP_PCI#
R418 10K_0402_5% H_STP_CPU# E19 G20 ICH_PWROK LAN_RST# 1 2
16 H_STP_CPU# STP_CPU# PWROK ICH_PWROK 8
1 2 CR_CPPE# R342 10K_0402_5%
R415 10K_0402_5% PM_CLKRUN# L4 M2 DPRSLPVR 1 2 No used Integrated LAN,

Power MGT
31 PM_CLKRUN# CLKRUN# DPRSLPVR/GPIO16 PM_DPRSLPVR 8,46
1 2 ICH_GPIO17 R381 100_0402_5%
R399 @ 10K_0402_5%
29,30 ICH_PCIE_WAKE#
ICH_PCIE_WAKE# E20 B13 PM_BATLOW# connecting LAN_RST# to GND
ICH_GPIO18 SERIRQ WAKE# BATLOW#
1 2 31 SERIRQ M5 SERIRQ
R87 @ 10K_0402_5% EC_THERM# AJ23 R3 PBTN_OUT# ICH_PWROK 1 2
31 EC_THERM# THRM# PWRBTN# PBTN_OUT# 31
1 2 ICH_GPIO20 R324 10K_0402_5%
R158 @ 10K_0402_5% VGATE 2 1 ICH_VGATE D21 D20 LAN_RST# 1 2
8,16,46 VGATE VRMPWRGD LAN_RST# PLT_RST# 8,21,26,27,31
1 2 SATA_CLKREQ# R338 0_0402_5% R341 @ 0_0402_5%
R94 10K_0402_5% PAD @ ICH_TP11 A20 D22 SB_RSMRST# EC_PWROK 1 2
T14 TP11 RSMRST#
1 2 ICH_GPIO38 R339 10K_0402_5%
R398 @ 10K_0402_5% OCP# AG19 R5 CK_PWRGD
4 OCP# GPIO1 CK_PWRGD CK_PWRGD 16
1 2 ICH_GPIO39 CRT_DET AH21
R403 @ 10K_0402_5% CR_CPPE# GPIO6 ICH_PWROK R340 2 @
26 CR_CPPE# AG21 GPIO7 CLPWROK R6 1 0_0402_5%
1 2 ICH_GPIO48 EC_SMI# A21
31 EC_SMI# GPIO8 +3VS
R404 10K_0402_5% C12 B16 PM_SLP_M# PAD
31 EC_SCI# GPIO12 SLP_M# T15
ICH_GPIO13 C21 @
+3V ICH_GPIO17 GPIO13
AE18 GPIO17 CL_CLK0 F24 CL_CLK0 8

5
ICH_GPIO18 K1 B19 U29

GPIO
Controller Link
ICH_SMBCLK ICH_GPIO20 GPIO18 CL_CLK1 EC_PWROK
1 2 AF8 2

P
GPIO20 B EC_PWROK 31,33
R46 2.2K_0402_5% CR_WAKE# AJ22 F22 ICH_PWROK 4
+3V 26 CR_WAKE# SCLOCK/GPIO22 CL_DATA0 CL_DATA0 8 Y
1 2 ICH_SMBDATA PAD @ ICH_GPIO27 A9 C19 1 VGATE
T7 GPIO27 CL_DATA1 A

G
R45 2.2K_0402_5% @ ICH_GPIO28 D19
T21 PAD GPIO28
1 2 EC_SWI# SATA_CLKREQ# L1 C25 CL_VREF0_ICH NC7SZ08P5X_NL_SC70-5
16 SATA_CLKREQ#

3
SATACLKREQ#/GPIO35 CL_VREF0
1

R370 10K_0402_5% ICH_GPIO38 AE19 A19 CL_VREF1_ICH

ICH_SMLINK0 R59 ICH_GPIO39 SLOAD/GPIO38 CL_VREF1
1 2 AG22 SDATAOUT0/GPIO39
C R363 10K_0402_5% 10K_0402_5% ICH_GPIO48 C
AF21 SDATAOUT1/GPIO48 CL_RST0# F21 CL_RST#0 8
1 2 ICH_SMLINK1 @ ICH_GPIO49 AH24 D18 @
R362 10K_0402_5% ICH_GPIO57 GPIO49 CL_RST1# R179 2
A8 1 0_0402_5%
2

LINKALERT# ICH_GPIO57 GPIO57/CLGPIO5 ICH_GPIO24 @ Q10

1 2 MEM_LED/GPIO24 A16 PAD T8 2 1 +3V
R368 10K_0402_5% SB_SPKR M7 C18 ICH_GPIO10 R346 100K_0402_5% MMBT3906_SOT23-3
34 SB_SPKR SPKR GPIO10/SUS_PWR_ACK
1

1 2 XDP_DBRESET# AJ24 C11 ICH_ACIN 2 1 SB_RSMRST# 1 3

C
MISC
8 MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT ACIN 31,32,39,42 EC_RSMRST# 31
R78 10K_0402_5% R58 B21 C20 ICH_GPIO9 @ D24

E
22 ICH_TP3 TP3 WOL_EN/GPIO9 PAD T19
1 2 ICH_PCIE_WAKE# 100K_0402_5%
T30 PAD @ ICH_TP8 AH20 TP8
CH751H-40PT_SOD323-2

1
R369 1K_0402_5% @ ICH_TP9 AJ20

B
T11 PAD

2
PM_BATLOW# @ ICH_TP10 TP9 R180
1 2 T12 PAD AJ21 1 2 +3V
2

R44 8.2K_0402_5% TP10 R177 4.7K_0402_5%

10K_0402_5%
1 2 EC_LID_OUT# ICH9-M ES_FCBGA676
R357 10K_0402_5% D11A

2
1 2 ICH_GPIO10 U9D 1
R361 10K_0402_5% PCIE_PTX_C_IRX_N1 N29 V27 DMI_MTX_IRX_N0 6
30 PCIE_PTX_C_IRX_N1 PERN1 DMI0RXN DMI_MTX_IRX_N0 8
1 2 ICH_GPIO13 PCIE_PTX_C_IRX_P1 N28 V26 DMI_MTX_IRX_P0 2
30 PCIE_PTX_C_IRX_P1 PERP1 DMI0RXP DMI_MTX_IRX_P0 8
R360 10K_0402_5% For Express Card 30 PCIE_ITX_C_PRX_N1 C480 ABO@
2 1 0.1U_0402_16V7K PCIE_ITX_PRX_N1 P27 U29 DMI_ITX_MRX_N0
PETN1 DMI0TXN DMI_ITX_MRX_N0 8
1 2 S4_STATE# C487 ABO@
2 1 0.1U_0402_16V7K PCIE_ITX_PRX_P1 P26 U28 DMI_ITX_MRX_P0 BAV99DW-7_SOT363

Direct Media Interface

30 PCIE_ITX_C_PRX_P1 PETP1 DMI0TXP DMI_ITX_MRX_P0 8
R60 @ 10K_0402_5%
PCIE_PTX_C_IRX_N2 L29 Y27 DMI_MTX_IRX_N1 D11B
29 PCIE_PTX_C_IRX_N2 PERN2 DMI1RXN DMI_MTX_IRX_N1 8
1 2 PROJECT_ID0 PCIE_PTX_C_IRX_P2 L28 Y26 DMI_MTX_IRX_P1 4
29 PCIE_PTX_C_IRX_P2 PERP2 DMI1RXP DMI_MTX_IRX_P1 8
R417 EM@ 10K_0402_5% For Wireless LAN 29 PCIE_ITX_C_PRX_N2 C475 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_N2 M27 W29 DMI_ITX_MRX_N1 3
PETN2 DMI1TXN DMI_ITX_MRX_N1 8
1 2 29 PCIE_ITX_C_PRX_P2 C479 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_P2 M26 W28 DMI_ITX_MRX_P1 5
PETP2 DMI1TXP DMI_ITX_MRX_P1 8

1
R416 ABO@ 10K_0402_5%

PCI - Express
1 2 PROJECT_ID1 PCIE_PTX_C_IRX_N3 J29 AB27 DMI_MTX_IRX_N2 BAV99DW-7_SOT363 R176
27 PCIE_PTX_C_IRX_N3 PERN3 DMI2RXN DMI_MTX_IRX_N2 8
R405 10K_0402_5% PCIE_PTX_C_IRX_P3 J28 AB26 DMI_MTX_IRX_P2 2.2K_0402_5%
27 PCIE_PTX_C_IRX_P3 PERP3 DMI2RXP DMI_MTX_IRX_P2 8
1 2 PM_DPRSLPVR For PCIE LAN 27 PCIE_ITX_C_PRX_N3 C472 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_N3 K27 AA29 DMI_ITX_MRX_N2
PETN3 DMI2TXN DMI_ITX_MRX_N2 8
R382 100K_0402_5% 27 PCIE_ITX_C_PRX_P3 C468 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_P3 K26 AA28 DMI_ITX_MRX_P2
DMI_ITX_MRX_P2 8

2
ICH_GPIO49 PETP3 DMI2TXP
1 2
R152 @ 1K_0402_5% PCIE_PTX_C_IRX_N4 G29 AD27 DMI_MTX_IRX_N3
29 PCIE_PTX_C_IRX_N4 PERN4 DMI3RXN DMI_MTX_IRX_N3 8
PCIE_PTX_C_IRX_P4 G28 AD26 DMI_MTX_IRX_P3
29 PCIE_PTX_C_IRX_P4 PERP4 DMI3RXP DMI_MTX_IRX_P3 8
For Robson2 29 PCIE_ITX_C_PRX_N4 C465 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_N4 H27 AC29 DMI_ITX_MRX_N3
B PETN4 DMI3TXN DMI_ITX_MRX_N3 8 B
29 PCIE_ITX_C_PRX_P4 C461 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_P4 H26 AC28 DMI_ITX_MRX_P3
PETP4 DMI3TXP DMI_ITX_MRX_P3 8 +3VS
PCIE_PTX_C_IRX_N5 E29 T26 CLK_PCIE_ICH#
26 PCIE_PTX_C_IRX_N5 PERN5 DMI_CLKN CLK_PCIE_ICH# 16
PCIE_PTX_C_IRX_P5 E28 T25 CLK_PCIE_ICH
26 PCIE_PTX_C_IRX_P5 PERP5 DMI_CLKP CLK_PCIE_ICH 16
+3V 1 2 CP_PE# For Card Reader 26 PCIE_ITX_C_PRX_N5 C454 2ABO@1 0.1U_0402_16V7K PCIE_ITX_PRX_N5 F27 PETN5
R388 EM@ 10K_0402_5% 26 PCIE_ITX_C_PRX_P5 C455 2ABO@1 0.1U_0402_16V7K PCIE_ITX_PRX_P5 F26 AF29 R134 24.9_0402_1% Within 500 mils R352
PETP5 DMI_ZCOMP
1 2 USB_OC#4 DMI_IRCOMP AF28 DMI_IRCOMP 1 2 +1.5VS_PCIE_ICH 3.24K_0402_1%
R99 10K_0402_5% C29 PERN6/GLAN_RXN USB20_N0
C28 PERP6/GLAN_RXP USBP0N AC5 USB20_N0 30
D27 AC4 USB20_P0 USB Conn. CL_VREF0_ICH
+3VS PETN6/GLAN_TXN USBP0P USB20_P0 30
RP49 D26 AD3 USB20_N1
PETP6/GLAN_TXP USBP1N USB20_N1 30
1 8 USB_OC#5 AD2 USB20_P1 New Card 1
USBP1P USB20_P1 30
2 7 USB_OC#9 ICH_SPI_CLK R38 1 @ 2 15_0402_5% ICH_SPI_CLK_R D23 AC1 USB20_N2 C445 R353
SPI_CLK USBP2N USB20_N2 30
2

3 6 USB_OC#8 ICH_SPI_CS0# R53 1 @ 2 15_0402_5% ICH_SPI_CS0#_R D24 AC2 USB20_P2 USB Conn. 453_0402_1%
SPI_CS0# USBP2P USB20_P2 30
4 5 USB_OC#11 R148 F23 AA5 USB20_N3 0.1U_0402_16V4Z
21 SPI_CS#1 SPI_CS1#GPIO58/CLGPIO6 USBP3N USB20_N3 38 2
10K_0402_5% AA4 USB20_P3 DOCKING Conn.
USBP3P USB20_P3 38
10K_1206_8P4R_5% High: CRT Plugged ICH_SPI_MOSI R40 @ 2 15_0402_5% ICH_SPI_MOSI_R USB20_N4
ICH_SPI_MISO R54
1
@ 2 15_0402_5% ICH_SPI_MISO_R
D25 SPI_MOSI SPI USBP4N AB2
USB20_P4
USB20_N4 29
1 E23 AB3 USB20_P4 29 USB/B
1

RP50 CRT_DET SPI_MISO USBP4P USB20_N5

USBP5N AA1 USB20_N5 30
1 8 USB_OC#10 USB_OC#0 N4 AA2 USB20_P5 Bluetooth
30 USB_OC#0 OC0#/GPIO59 USBP5P USB20_P5 30
1

USB_OC#3 D CP_PE# USB20_N6 +3V

2 7 30 CP_PE# N5 OC1#/GPIO40 USBP6N W5 USB20_N6 18
USB_OC#7 USB_OC#2 USB20_P6
3
4
6
5 USB_OC#6
19,38 CRT_DET# 2
Q9 G
30 USB_OC#2
USB_OC#3
N6
P6
OC2#/GPIO41 USB USBP6P W4
Y3 USB20_N7
USB20_P6 18 CMOS Camera
OC3#/GPIO42 USBP7N USB20_N7 29
2N7002_SOT23 S USB_OC#4 M1 Y2 USB20_P7 Mini Card(Robson2)
29 USB_OC#4 USB20_P7 29
3

10K_1206_8P4R_5% USB_OC#5 OC4#/GPIO43 USBP7P USB20_N8 R63

N2 OC5#/GPIO29 USBP8N W1 USB20_N8 29
USB_OC#6 M4 W2 USB20_P8 Mini Card(WLAN) 3.24K_0402_1%
OC6#/GPIO30 USBP8P USB20_P8 29
USB_OC#7 M3 V2
USB_OC#8 OC7#/GPIO31 USBP9N
N3 V3
Internal TPM Strap DMI Termination Voltage USB_OC#9 N1
OC8#/GPIO44
OC9#/GPIO45
USBP9P
USBP10N U5 USB20_N10
USB20_N10 30
CL_VREF1_ICH
USB_OC#10 USB20_P10 Finger Print
Low= Disable* Low= Desktop used USB_OC#11
P5
P3
OC10#/GPIO46 USBP10P U4
U1
USB20_P10 30
SPI_MOSI High= iTPM enable by MCH strap GPIO49 High= Mobile* (Internal pull-up) OC11#/GPIO47 USBP11N
USBP11P U2 C137
1
R64
A USBRBIAS 453_0402_1% A
AG2
2 1 AG1
USBRBIAS
USBRBIAS#
No Reboot Strap 0.1U_0402_16V4Z
R137 2
22.6_0402_1%
Within 500 mils ICH9-M ES_FCBGA676 Low= Default*
ICH SPI ROM for HDCP +3VS SB_SPKR High= "No Reboot"
+3VS R55 U5
3.3K_0402_5% ICH_SPI_CS0# 1 8
@ ICH_SPI_WP# CS# VCC ICH_SPI_CLK
R34 1
1
@
2
2 ICH_SPI_HOLD#
3
7
WP#
HOLD#
SCLK
SI
6
5 ICH_SPI_MOSI Security Classification Compal Secret Data Compal Electronics, Inc.
3.3K_0402_5% 4 2 ICH_SPI_MISO 2007/09/20 2008/09/20 Title
GND SO Issued Date Deciphered Date
MX25L4005AMC-12G_SO8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
If ICH SPI not used, Left NC SPI ROM Footprint 150mil DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401551 I
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 21, 2008 Sheet 23 of 50
5 4 3 2 1
 5 4 3 2 1

+5VS +3VS U9F

+RTCVCC A23 A15 +1.05VS U9E
VCCRTC VCC1_05[01]
1 1 VCC1_05[02] B15 AA26 VSS[001] VSS[107] H5

2
C448 C446 +ICH_V5REF A6 C15 1 1 AA27 J23
R57 D8 V5REF VCC1_05[03] C485 C484 VSS[002] VSS[108]
VCC1_05[04] D15 AA3 VSS[003] VSS[109] J26
100_0402_5% CH751H-40PT_SOD323-2 0.1U_0402_16V4Z E15 AA6 J27
2 2 +ICH_V5REF_SUS VCC1_05[05] 0.1U_0402_16V4Z VSS[004] VSS[110]
AE1 V5REF_SUS VCC1_05[06] F15 AB1 VSS[005] VSS[111] AC22
1U_0402_6.3V4Z 2 2
L11 AA23 K28
1

1
+ICH_V5REF VCC1_05[07] 0.1U_0402_16V4Z VSS[006] VSS[112]
AA24 VCC1_5_B[01] VCC1_05[08] L12 AB28 VSS[007] VSS[113] K29
2 AA25 VCC1_5_B[02] VCC1_05[09] L14 AB29 VSS[008] VSS[114] L13
C135 AB24 L16 AB4 L15
VCC1_5_B[03] VCC1_05[10] VSS[009] VSS[115]
AB25 VCC1_5_B[04] VCC1_05[11] L17 AB5 VSS[010] VSS[116] L2
1U_0402_6.3V6K AC24 L18 AC17 L26
1 VCC1_5_B[05] VCC1_05[12] +1.5VS_DMIPLL_ICH VSS[011] VSS[117]
AC25 VCC1_5_B[06] VCC1_05[13] M11 AC26 VSS[012] VSS[118] L27
AD24 VCC1_5_B[07] VCC1_05[14] M18 AC27 VSS[013] VSS[119] L5
L7 1

CORE
D AD25 VCC1_5_B[08] VCC1_05[15] P11 2 +1.5VS AC3 VSS[014] VSS[120] L7 D
+5VALW +5V +3V MBK1608301YZF_0603
AE25 VCC1_5_B[09] VCC1_05[16] P18 AD1 VSS[015] VSS[121] M12
AE26 VCC1_5_B[10] VCC1_05[17] T11 1 (10UF*1, 0.01UF*1) AD10 VSS[016] VSS[122] M13
AE27 T18 C162 AD12 M14
VCC1_5_B[11] VCC1_05[18] VSS[017] VSS[123]
2

AE28 U11 C166 AD13 M15

R135 R133 D9 VCC1_5_B[12] VCC1_05[19] VSS[018] VSS[124]
AE29 VCC1_5_B[13] VCC1_05[20] U18 10U_0805_10V4Z AD14 VSS[019] VSS[125] M16
100_0402_5% 2
CH751H-40PT_SOD323-2 F25 VCC1_5_B[14] VCC1_05[21] V11 AD17 VSS[020] VSS[126] M17
10_0402_5% G25 V12 0.01U_0402_16V7K AD18 M23
@ VCC1_5_B[15] VCC1_05[22] VSS[021] VSS[127]
H24 V14 AD21 M28
1

+ICH_V5REF_SUS VCC1_5_B[16] VCC1_05[23] VSS[022] VSS[128]

H25 VCC1_5_B[17] VCC1_05[24] V16 AD28 VSS[023] VSS[129] M29
2 J24 VCC1_5_B[18] VCC1_05[25] V17 +1.05VS AD29 VSS[024] VSS[130] N11

VCCA3GP
C204 J25 V18 AD4 N12
VCC1_5_B[19] VCC1_05[26] VSS[025] VSS[131]
K24 VCC1_5_B[20] 1 (4.7UF*1) AD5 VSS[026] VSS[132] N13
1U_0402_6.3V6K K25 C474 AD6 N14
1 VCC1_5_B[21] VSS[027] VSS[133]
L23 VCC1_5_B[22] AD7 VSS[028] VSS[134] N15
+1.5VS_PCIE_ICH L24 R29 4.7U_0805_10V4Z AD9 N16
VCC1_5_B[23] VCCDMIPLL 2 VSS[029] VSS[135]
(220UF*1, 22UF*2, 2.2UF*1) L25 VCC1_5_B[24] AE12 VSS[030] VSS[136] N17
+1.5VS L33 2 1 M24 W23 AE13 N18
KC FBM-L11-201209-221LMAT_0805 VCC1_5_B[25] VCC_DMI[1] VSS[031] VSS[137]
1 M25 VCC1_5_B[26] VCC_DMI[2] Y23 AE14 VSS[032] VSS[138] N26
1 1 N23 VCC1_5_B[27] AE16 VSS[033] VSS[139] N27
C516 + C463 C496 C476 N24 AB23 AE17 P12
VCC1_5_B[28] V_CPU_IO[1] +1.05VS VSS[034] VSS[140]
N25 VCC1_5_B[29] V_CPU_IO[2] AC23 1 1 AE2 VSS[035] VSS[141] P13
220U_D2_4VM_R15 10U_0805_10V4Z P24 C462 C469 C499 (4.7UF*1, 0.1UF*2) AE20 P14
2 2 2 VCC1_5_B[30] VSS[036] VSS[142]
P25 VCC1_5_B[31] VCC3_3[01] AG29 AE24 VSS[037] VSS[143] P15
10U_0805_10V4Z 2.2U_0603_6.3V6K R24 AJ6 4.7U_0805_10V4Z 0.1U_0402_16V4Z AE3 P16
VCC1_5_B[32] VCC3_3[02] 2 2 VSS[038] VSS[144]
R25 VCC1_5_B[33] VCC3_3[07] AC10 AE4 VSS[039] VSS[145] P17
R26 0.1U_0402_16V4Z AE6 P2
VCC1_5_B[34] VSS[040] VSS[146]
R27 VCC1_5_B[35] VCC3_3[03] AD19 AE9 VSS[041] VSS[147] P23

VCCP_CORE
T24 VCC1_5_B[36] VCC3_3[04] AF20 AF13 VSS[042] VSS[148] P28
T27 VCC1_5_B[37] VCC3_3[05] AG24 close to AG29 close to AD19 close to G6 AF16 VSS[043] VSS[149] P29
T28 VCC1_5_B[38] VCC3_3[06] AC20 AF18 VSS[044] VSS[150] P4
T29 VCC1_5_B[39] +3VS AF22 VSS[045] VSS[151] P7
+1.5VS_SATAPLL_ICH U24 AH26 R11
C VCC1_5_B[40] VSS[046] VSS[152] C
U25 VCC1_5_B[41] VCC3_3[08] B9 1 1 1 1 1 1 AF26 VSS[047] VSS[153] R12
+1.5VS L9 1 2 V24 F9 C506 C511 C514 C473 C460 C459 AF27 R13
MBK1608301YZF_0603 VCC1_5_B[42] VCC3_3[09] VSS[048] VSS[154]
V25 VCC1_5_B[43] VCC3_3[10] G3 AF5 VSS[049] VSS[155] R14
1 1 U23 G6 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z AF7 R15
VCC1_5_B[44] VCC3_3[11] 2 2 2 2 2 2 VSS[050] VSS[156]

PCI
C221 W24 J2 AF9 R16
C224 VCC1_5_B[45] VCC3_3[12] 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VSS[051] VSS[157]
W25 VCC1_5_B[46] VCC3_3[13] J7 AG13 VSS[052] VSS[158] R17
10U_0805_10V4Z K23 VCC1_5_B[47] VCC3_3[14] K7 AG16 VSS[053] VSS[159] R18
2 1U_0402_6.3V4Z
2
(10UF*1, 1UF*1) Y24 VCC1_5_B[48] close to AJ6 close to B9 close to K7 AG18 VSS[054] VSS[160] R28
Y25 VCC1_5_B[49] AG20 VSS[055] VSS[161] T12
AJ4 +VCC_HDA_ICH AG23 T13
VCCHDA +3VS VSS[056] VSS[162]
R160 GLPM@ 0_0603_5% AG3 T14
VSS[057] VSS[163]
VCCSUSHDA AJ3 +1.5VS AG6 VSS[058] VSS[164] T15
+5VALW R159 0_0603_5%
AJ19 VCCSATAPLL 1 AG9 VSS[059] VSS[165] T16
C225 JAL90GM@ AH12 T17
VSS[060] VSS[166]
VCCSUS1_05[1] AC8 TP_VCCSUS1_05_ICH_1 @ PAD T29 AH14 VSS[061] VSS[167] T23
+1.5VS AC16 VCC1_5_A[01] VCCSUS1_05[2] F17 TP_VCCSUS1_05_ICH_2 @ PAD T24
0.1U_0402_16V4Z AH17 VSS[062] VSS[168] B26
3

S
2
G AD15 VCC1_5_A[02] AH19 VSS[063] VSS[169] U12
37 SBPWR_EN# 2 1 1 AD16 VCC1_5_A[03] AH2 VSS[064] VSS[170] U13
C507 C502 AE15 AD8 TP_VCCSUS1_5_ICH_1 @ +VCCSUS_HDA_ICH AH22 U14
VCC1_5_A[04] VCCSUS1_5[1] PAD T28 +3V VSS[065] VSS[171]
ARX

1 Q6 D AF15 R162 GLPM@ 0_0603_5% AH25 U15

1

C227 AO3413_SOT23-3 1U_0402_6.3V4Z VCC1_5_A[05] +VCCSUS1_5_ICH_INT_2 VSS[066] VSS[172]

AG15 VCC1_5_A[06] VCCSUS1_5[2] F18 +1.5V AH28 VSS[067] VSS[173] U16
2 2 R161 0_0603_5%
AH15 VCC1_5_A[07] 1 1 AH5 VSS[068] VSS[174] U17
0.1U_0402_16V4Z AJ15 C458 C226 JAL90GM@ AH8 AD23
2 +5V VCC1_5_A[08] VSS[069] VSS[175]
1U_0402_6.3V4Z VCCSUS3_3[01] A18
0.1U_0402_16V4Z 0.1U_0402_16V4Z
Check Power Source AJ12 VSS[070] VSS[176] U26
AC11 D16 AJ14 U27
VCCPSUS

VCC1_5_A[09] VCCSUS3_3[02] 2 2 VSS[071] VSS[177]

AD11 VCC1_5_A[10] VCCSUS3_3[03] D17 AJ17 VSS[072] VSS[178] U3
AE11 VCC1_5_A[11] VCCSUS3_3[04] E22 AJ8 VSS[073] VSS[179] V1
AF11 VCC1_5_A[12] B11 VSS[074] VSS[180] V13
ATX

AG10 VCC1_5_A[13] B14 VSS[075] VSS[181] V15

AG11 VCC1_5_A[14] B17 VSS[076] VSS[182] V23
AH10 VCC1_5_A[15] B2 VSS[077] VSS[183] V28
AJ10 VCC1_5_A[16] VCCSUS3_3[05] AF1 +3V B20 VSS[078] VSS[184] V29
B B23 VSS[079] VSS[185] V4 B
AC9 VCC1_5_A[17] 1 1 B5 VSS[080] VSS[186] V5
C451 C490 C497 B8 W26
VSS[081] VSS[187]
AC18 VCC1_5_A[18] C26 VSS[082] VSS[188] W27
AC19 0.022U_0402_16V7K 0.1U_0402_16V4Z (0.1UF*1, 0.022UF*2) C27 W3
VCC1_5_A[19] 2 2 VSS[083] VSS[189]
VCCSUS3_3[06] T1 E11 VSS[084] VSS[190] Y1
AC21 T2 0.022U_0402_16V7K E14 Y28
VCC1_5_A[20] VCCSUS3_3[07] VSS[085] VSS[191]
VCCSUS3_3[08] T3 E18 VSS[086] VSS[192] Y29
G10 VCC1_5_A[21] VCCSUS3_3[09] T4 E2 VSS[087] VSS[193] Y4
G9 VCC1_5_A[22] VCCSUS3_3[10] T5 close to A18 close to T1 E21 VSS[088] VSS[194] Y5
VCCSUS3_3[11] T6 E24 VSS[089] VSS[195] AG28
AC12 U6 E5 AH6
VCCPUSB

VCC1_5_A[23] VCCSUS3_3[12] VSS[090] VSS[196]

AC13 VCC1_5_A[24] VCCSUS3_3[13] U7 E8 VSS[091] VSS[197] AF2
close to AC7 AC14 VCC1_5_A[25] VCCSUS3_3[14] V6 F16 VSS[092] VSS[198] B25
VCCSUS3_3[15] V7 F28 VSS[093]
+1.5VS AJ5 VCCUSBPLL VCCSUS3_3[16] W6 F29 VSS[094]
1 1 VCCSUS3_3[17] W7 G12 VSS[095]
USB CORE

C515 C503 AA7 Y6 G14 A1

VCC1_5_A[26] VCCSUS3_3[18] VSS[096] VSS_NCTF[01]
close to AJ5 AB6 VCC1_5_A[27] VCCSUS3_3[19] Y7 G18 VSS[097] VSS_NCTF[02] A2
0.1U_0402_16V4Z AB7 T7 G21 A28
2 2 VCC1_5_A[28] VCCSUS3_3[20] VSS[098] VSS_NCTF[03]
AC6 VCC1_5_A[29] G24 VSS[099] VSS_NCTF[04] A29
0.1U_0402_16V4Z AC7 G26 AH1
VCC1_5_A[30] VSS[100] VSS_NCTF[05]
G27 VSS[101] VSS_NCTF[06] AH29
2 1 +VCCLAN1_05_INT_ICH A10 VCCLAN1_05[1] G8 VSS[102] VSS_NCTF[07] AJ1
C449 A11 G22 +VCCCL1_05_INT_ICH H2 AJ2
0.1U_0402_16V4Z VCCLAN1_05[2] VCCCL1_05 +VCCCL1_5_INT_ICH VSS[103] VSS_NCTF[08]
VCCCL1_5 G23 H23 VSS[104] VSS_NCTF[09] AJ28
+3VS +VCCLAN_ICH A12 H28 AJ29
R56 0_0603_5% VCCLAN3_3[1] VSS[105] VSS_NCTF[10]
1 B12 VCCLAN3_3[2] 1 1 1 H29 VSS[106] VSS_NCTF[11] B1
C138 A24 +3VS C457 C453 C456 B29
VCCCL3_3[1] @ @ VSS_NCTF[12]
VCCCL3_3[2] B24 (0.1UF*1)
GLAN POWER

+1.5VS +VCC_GLANPLL_ICH A27 1U_0402_6.3V4Z

2 R48 0_0603_5% VCCGLANPLL 2 2 2 ICH9-M ES_FCBGA676
1
0.1U_0402_16V4Z C139 D28 0.1U_0402_16V4Z 0.1U_0402_16V4Z
A
C126 VCCGLAN1_5[1] A
D29 VCCGLAN1_5[2]
(10UF*1, 2.2UF*1)10U_0805_10V4Z
2
E26 VCCGLAN1_5[3]
E27 VCCGLAN1_5[4] (1UF*1, 0.1UF*1)
2.2U_0603_6.3V6K
A26 VCCGLAN3_3
+1.5VS +VCCGLAN_ICH
R76 0_0603_5% ICH9-M ES_FCBGA676
C157
(4.7UF*1)
+3VS Security Classification Compal Secret Data Compal Electronics, Inc.
4.7U_0805_10V4Z 2007/09/20 2008/09/20 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 24 of 50
5 4 3 2 1
 5 4 3 2 1

+5VS +3VS

0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 1 1 1 1
C573 C576 C578 C564 C562 C558
<BOM Structure>
2 2 2 2 2 2

D 1000P_0402_50V7K 10U_0805_10V4Z 1000P_0402_50V7K 10U_0805_10V4Z D

SATA HDD Conn.

JSATA2

1 GND
SATA_ITX_C_DRX_P0 2
22 SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_N0 HTX+
22 SATA_ITX_C_DRX_N0 3 HTX-
4 GND
SATA_DTX_IRX_N0 5
SATA_DTX_IRX_P0 HRX-
6 HRX+
7 GND

+3VS 8 VCC3.3
9 VCC3.3
10 VCC3.3
11 GND
22 SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 1 2 SATA_DTX_IRX_N0 12
C551 0.01U_0402_16V7K GND
13 GND
+5VS 14 VCC5
22 SATA_DTX_C_IRX_P0 SATA_DTX_C_IRX_P0 1 2 SATA_DTX_IRX_P0 15
C552 0.01U_0402_16V7K VCC5
16 VCC5
17 GND
18 RESERVED
19 GND
C 20 C
VCC12
21 VCC12 GND 24
22 VCC12 GND 23

OCTEK_SAT-22SU1G_22P_NR-T
CONN@

+5VS

0.1U_0402_16V4Z

1 1 1
C259 C254 C260

2 2 2

1000P_0402_50V7K 10U_0805_10V4Z

SATA ODD Conn.

JSATA1
B B
1 GND
SATA_ITX_C_DRX_P1 2
22 SATA_ITX_C_DRX_P1 SATA_ITX_C_DRX_N1 A+
22 SATA_ITX_C_DRX_N1 3 A-
4 GND
SATA_DTX_IRX_N1 5
SATA_DTX_IRX_P1 B-
6 B+
7 GND

R173 1 @ 2 1K_0402_1% 8 DP
+5VS 9 +5V
10 +5V
11 MD
22 SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_N1 1 2 SATA_DTX_IRX_N1 12 15
C264 0.01U_0402_16V7K GND GND
13 GND GND 14

22 SATA_DTX_C_IRX_P1 SATA_DTX_C_IRX_P1 1 2 SATA_DTX_IRX_P1

C262 0.01U_0402_16V7K SANTA_206401-1_13P
CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 25 of 50
5 4 3 2 1
 5 4 3 2 1

MDIO PULL HIGH/LOW ?

+3VS L38 +1.8VS_APVDD C534
40mil MBK1608121YZF_0603 0.1U_0402_16V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z
40mil ABO@
+1.8VS 1 2
@ +3V_MCVCC
1 1 1 1 1 1 1 1 1
C547 C533 C527 C545 C549 C526
ABO@ ABO@ XDWP_SDWP 1 2
D ABO@ ABO@ ABO@ ABO@ 10U_0805_10V4Z 0.1U_0402_16V4Z R453 ABO@ 10K_0402_5% D
2 2 2 2 2 2 2 2 2
XD_RB 1 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z C532 C546 R429 ABO@ 10K_0402_5%
0.1U_0402_16V4Z 1000P_0402_50V7K
ABO@ ABO@ +3VS

XD_CLE 1 2
U34 R452 ABO@ 10K_0402_5%

3 5 +1.8VS_APVDD XDCD0#_SDCD# 1 2
16 CLK_PCIE_READER# APCLKN APVDD
4 10 R427 ABO@ 4.7K_0402_5%
16 CLK_PCIE_READER APCLKP APV18
TAV33 30 +3VS
PCIE_ITX_C_PRX_N5 9 XDCD1#_MSCD# 1 2
23 PCIE_ITX_C_PRX_N5 APRXN
PCIE_ITX_C_PRX_P5 8 19 R430 ABO@ 4.7K_0402_5%
23 PCIE_ITX_C_PRX_P5 APRXP DV33
ABO@ 20
C530 1 0.1U_0402_16V7K PCIE_PTX_IRX_N5 DV33
23 PCIE_PTX_C_IRX_N5 2 11 APTXN DV33 44
23 PCIE_PTX_C_IRX_P5 C529 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_P5 12 18 +1.8VS_APVDD
ABO@ APTXP DV18
DV18 37
R443 1 2 8.2K_0402_1% APREXT 7
ABO@ APREXT XD_SD_MS_D0
APREXT 12 mil MDIO0 48
47 XD_SD_MS_D1
MDIO1 XD_SD_MS_D2
+3VS 38 PCIES_EN MDIO2 46
39 45 XD_SD_MS_D3 XD_RE 1 2
PCIES JMB385 MDIO3
MDIO4 43 SDCMD_MSBS_XDWE# R436 ABO@ 200K_0402_5%
42 MDIO5 R535 1 ABO@ 2 22_0402_5% XDCE_SDCLK_MSCLK
MDIO5 XDWP_SDWP XD_ALE
MDIO6 41 1 2
40 XD_CLE R428 ABO@ 200K_0402_5%
C
MDIO7 XD_D4 C
MDIO8 29
8,21,23,27,31 PLT_RST# 1 28 XD_D5
XRSTN MDIO9 XD_D6
2 XTEST MDIO10 27
26 XD_D7
R538 MDIO11 XD_RE
MDIO12 25
23 CR_CPPE# 1 @ 2 0_0402_5% 13 23 XD_RB
@ TP_SEECLK SEEDAT MDIO13 XD_ALE
T32 PAD 14 SEECLK MDIO14 22
D31 34
CH751H-40PT_SOD323-2 XDCD1#_MSCD# NC
15 CR1_CD1N NC 35
23 CR_WAKE# 1 2 XDCD0#_SDCD# 16 36
@ CR1_CD0N NC
1 @ 2 6
R539 MC_PWREN# APGND D26
17 CR1_PCTLN
0_0402_5% MC_PWREN# 30 mil 24 XDCD0#_SDCD# 2
GND XD_CD#
GND 31 1
21 32 XDCD1#_MSCD# 3
32 5IN1_LED# CR1_LEDN GND
GND 33
DAN202UT106_SC70-3 C524
ABO@ ABO@
270P_0402_50V7K
JMB385-LGEZ0B_LQFP48_7X7
ABO@

4 IN 1 Socket Push Type(New)

B JREAD1 B

3 21
Memory Card Power Switch +3V_MCVCC
XD_SD_MS_D0 32
XD-VCC SD-VCC
MS-VCC 28
+3V_MCVCC

XD_SD_MS_D1 XD-D0 XDCE_SDCLK_MSCLK

10 XD-D1 7 IN 1 CONN SD_CLK 20
XD_SD_MS_D2 9 14 XD_SD_MS_D0
+3VS +3V_MCVCC XD_SD_MS_D3 XD-D2 SD-DAT0 XD_SD_MS_D1
8 XD-D3 SD-DAT1 12
XD_D4 7 30 XD_SD_MS_D2
U35 XD_D5 XD-D4 SD-DAT2 XD_SD_MS_D3
40mil XD_D6
6 XD-D5 SD-DAT3 29
XD_D4 (MMC Data Bit 4)
1 GND OUT 8 5 XD-D6 SD-DAT4 27
2 7 XD_D7 4 23 XD_D5 (MMC Data Bit 5)
IN OUT C548 1 C543 1 C544 1 XD-D7 SD-DAT5 XD_D6 (MMC Data Bit 6)
3 IN OUT 6 SD-DAT6 18
MC_PWREN# 4 5 SDCMD_MSBS_XDWE# 34 16 XD_D7 (MMC Data Bit 7)
EN# FLG ABO@ XDWP_SDWP XD-WE SD-DAT7 SDCMD_MSBS_XDWE#
33 XD-WP SD-CMD 25
1

TPS2061DRG4_SO8 4.7U_0805_10V4Z 0.1U_0402_16V4Z XD_ALE 35 1 XDCD0#_SDCD#

R431 ABO@ 2 2 2 XD_CD# XD-ALE SD-CD-SW
@ 40 XD-CD
300_0603_5% 0.1U_0402_16V4Z XD_RB 39 2 XDWP_SDWP
@ ABO@ XD_RE XD-R/B SD-WP-SW
38 XD-RE
XDCE_SDCLK_MSCLK 37
1 2

XD_CLE XD-CE XDCE_SDCLK_MSCLK

D 36 XD-CLE MS-SCLK 26
17 XD_SD_MS_D0
MC_PWREN# Q40 MS-DATA0 XD_SD_MS_D1
2 11 7IN1 GND MS-DATA1 15
G 2N7002_SOT23 31 19 XD_SD_MS_D2
@ 7IN1 GND MS-DATA2 XD_SD_MS_D3
S 24
3

MS-DATA3 XDCD1#_MSCD#
MS-INS 22
13 SDCMD_MSBS_XDWE#
MS-BS
41 7IN1 GND
42 7IN1 GND
A A
MC_PWREN# 1 2 +3V_MCVCC TAITW_R015-B10-LM
R435 ABO@ 0_0805_5% CONN@
1
C525
ABO@
4.7U_0805_10V4Z
2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 26 of 50
5 4 3 2 1
 5 4 3 2 1

LAN RTL8111C/8102E

B3
e
a0
d
f
o
r
8
1
1
1
C
4
.
7
u
H
c
h
o
k
e

0
m
A
+3V_LAN
L1 8111C@ +LAN_AVDD18 L2 +1.8V_LAN
60mil 40mil 4.7UH_1008HC-472EJFS-A_5%_1008 MBK1608121YZF_0603
+3VALW 1
R290
2
0_1206_5% +CTRL_18
40mil 20mil
1 2 1 2
1 1 1 1
C426 C423 C408 C387 1 1 1 1 1 1 1 1 1
1 2 C11 C12 C14 C24 C25 C26 C27 C401 C407
0.1U_0402_16V4Z 0.1U_0402_16V4Z R14
D 2 2 2 2 8102E@ 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z D
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0_0805_5% 2 2 2 2 2 2 2 2 2
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1
+3V_LAN
R23
0_0805_5%

1
8111C@
R19

2
0_0603_5%
8111C@ +1.2V_LAN
40mil
40mil

2
+CTRL_12 1 2
1 1 R18
C392 C15 8102E@ 1 1 1 1 1 1 1 1
8111C@ 8111C@ 0_0805_5% C404 C418 C388 C398 C424 C425 C417 C414
0.1U_0402_16V4Z 10U_0805_10V4Z
2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

+3V_LAN 2 1 LAN_PME#
R296
100K_0402_5%

C U25 C
Place closed to Chip
23 PCIE_PTX_C_IRX_P3 C415 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_P3 29 45 LAN_DO
HSOP EEDO LAN_DI
EEDI/AUX 47
23 PCIE_PTX_C_IRX_N3 C416 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_N3 30 48 LAN_SK
HSON EESK LAN_CS
EECS 44
PCIE_ITX_C_PRX_P3 23
23 PCIE_ITX_C_PRX_P3 HSIP
PCIE_ITX_C_PRX_N3 24
23 PCIE_ITX_C_PRX_N3 HSIN
LED3 54
55 R315
LED2 3.6K_0402_5%
33 CLKREQB LED1 56 LAN_LINK# 28
LED0 57 LAN_ACTIVITY# 28 1 2 +3V_LAN
16 CLK_PCIE_LAN 26 REFCLK_P
27 3 LAN_MIDI0+ U26
16 CLK_PCIE_LAN# REFCLK_N MDIP0 LAN_MIDI0+ 28
4 LAN_MIDI0- LAN_DO 4 5 2
MDIN0 LAN_MIDI0- 28 DO GND
R297 1 2 0_0402_5% LAN_RESET# 20 6 LAN_MIDI1+ LAN_DI 3 6 C420 @
8,21,23,26,31 PLT_RST# PERSTB MDIP1 LAN_MIDI1+ 28 DI NC
7 LAN_MIDI1- LAN_SK 2 7 0.1U_0402_16V4Z
MDIN1 LAN_MIDI1- 28 SK NC
9 LAN_MIDI2+ LAN_CS 1 8 +3V_LAN
MDIP2 LAN_MIDI2+ 28 CS VCC 1
+CTRL_18 1 10 LAN_MIDI2-
SROUT12 MDIN2 LAN_MIDI2- 28
12 LAN_MIDI3+ AT93C46-10SI-2.7_SO8
MDIP3 LAN_MIDI3+ 28
+LAN_AVDD18 5 13 LAN_MIDI3- @
FB12 MDIN3 LAN_MIDI3- 28

+3V_LAN R292 1 8111C@ 2 0_0603_5% ENSR 62 ENSR

DVDD12 21 +1.2V_LAN
R294 1 2 2.49K_0402_1% 64 32
RSET DVDD12
DVDD12 38
DVDD12 43
DVDD12 49
R298 1 2 0_0402_5% LAN_PME# 19 52
31 EC_PME# LANWAKEB DVDD12
B ISOLATEB B
36 ISOLATEB
+3VS 22
EVDD12 +1.8V_LAN
EVDD12 28
LAN_X1 60 CKTAL1
1

R314 LAN_X2 61 16 +3V_LAN

1K_0402_1% CKTAL2 VDD33
VDD33 37
VDD33 46
53
2

ISOLATEB VDD33
65 EXPOSE_PAD
1

63 +CTRL_12
R313 VDDSR +3V_LAN
25 EGND
15K_0402_1% 2 +AVDD33
AVDD33
31 EGND AVDD33 59

1
2

8 +LAN_AVDD18 R15
AVDD12 0_0805_5%
+1.2V_LAN 15 NC AVDD12 11
17 NC AVDD12 14
18 58 +1.2V_LAN

2
NC AVDD12
34 NC
Y2 35 +AVDD33
LAN_X1 LAN_X2 NC
1 2 39 NC IGPIO 50 1 1
40 51 C23 C28
25MHZ_20P NC OGPIO
1 1 41 NC
42 0.1U_0402_16V4Z 0.1U_0402_16V4Z
C400 C397 NC 2 2
27P_0402_50V8J 27P_0402_50V8J RTL8111C-GR_QFN64_9X9
2 2
8111C@

Place closed to Pin2 & Pin59

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 27 of 50
5 4 3 2 1
 5 4 3 2 1

LAN RTL8111C/8102E
D T1 D
1 TCT1 MCT1 24
L_LAN_MIDI0+ 2 23 RJ45_MIDI0+
L_LAN_MIDI0- TD1+ MX1+ RJ45_MIDI0-
3 TD1- MX1- 22
4 TCT2 MCT2 21
L_LAN_MIDI1+ 5 20 RJ45_MIDI1+
L_LAN_MIDI1- TD2+ MX2+ RJ45_MIDI1-
6 TD2- MX2- 19
7 TCT3 MCT3 18 1 2
L_LAN_MIDI2+ 8 17 RJ45_MIDI2+
L_LAN_MIDI2- TD3+ MX3+ RJ45_MIDI2- C3
9 TD3- MX3- 16
10 15 220P_0402_50V7K
L_LAN_MIDI3+ TCT4 MCT4 RJ45_MIDI3+ JRJ45
11 TD4+ MX4+ 14
L_LAN_MIDI3- 12 13 RJ45_MIDI3- 2 1 12 Amber LED+
TD4- MX4- +3V_LAN
R1 1K_0402_5%
350uH_GSL5009-1 LF L_LAN_ACTIVITY# 11
LAN_MIDI0+ R521 1 JAW50@2 0_0402_5% L_LAN_MIDI0+ Amber LED-
SHLD2 16
RJ45_MIDI3- 8 Guide Pin
LAN_MIDI0- R522 1 JAW50@2 0_0402_5% L_LAN_MIDI0- PR4-
SHLD1 15
RJ45_MIDI3+ 7 PR4+

1
LAN_MIDI1+ R523 1 JAW50@2 0_0402_5% L_LAN_MIDI1+ RJ45_MIDI1- 6
R2 R3 PR2-
LAN_MIDI1- R524 1 JAW50@2 0_0402_5% L_LAN_MIDI1- 75_0402_1% 75_0402_1% RJ45_MIDI2- 5
LAN_TCT PR3-

1
RJ45_MIDI2+ 4
LAN_MIDI2+ R525 1 JAW50@2 0_0402_5% L_LAN_MIDI2+ PR3+
1 1 1 1 R4 R6 RJ45_MIDI1+ 3
LAN_MIDI2- R526 1 JAW50@2 0_0402_5% L_LAN_MIDI2- C380 C379 C376 C375 75_0402_1% 75_0402_1% PR2+
RJ45_MIDI0- 2

2
C 0.1U_0402_16V4Z 0.1U_0402_16V4Z PR1- C
SHLD2 14
LAN_MIDI3+ R527 1 JAW50@2 0_0402_5% L_LAN_MIDI3+ 2 2 2 2 RJ45_GND RJ45_MIDI0+ 1 PR1+
SHLD1 13
LAN_MIDI3- R528 1 JAW50@2 0_0402_5% L_LAN_MIDI3- 0.1U_0402_16V4Z 0.1U_0402_16V4Z 40mil L_LAN_LINK# 10 Green LED-

+3V_LAN 2 1 9 Green LED+

LAN_ACTIVITY# R529 1 JAW50@2 0_0402_5% L_LAN_ACTIVITY# R5 1K_0402_5%
Place close to TCT pin FOX_JM36113-L2R8-7F
LAN_LINK# R530 1 JAW50@2 0_0402_5% L_LAN_LINK# CONN@
1 2
C9
+3V_LAN 220P_0402_50V7K

RJ45_GND 1 2 LANGND 40mil

1 1
C4
56
50
38
27
18
10
4

U1 1000P_1206_2KV7K C2 C1
4.7U_0805_10V4Z
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
VDD0

D_LAN_MIDI0+ 2 2
0B1 48 D_LAN_MIDI0+ 38
47 D_LAN_MIDI0- D_LAN_MIDI0- 38
LAN_MIDI0+ 1B1 0.1U_0402_16V4Z
27 LAN_MIDI0+ 2 A0
43 D_LAN_MIDI1+ D_LAN_MIDI1+ 38
LAN_MIDI0- 2B1 D_LAN_MIDI1-
27 LAN_MIDI0- 3 A1 3B1 42 D_LAN_MIDI1- 38

37 D_LAN_MIDI2+ D_LAN_MIDI2+ 38
LAN_MIDI1+ 4B1 D_LAN_MIDI2-
27 LAN_MIDI1+ 7 A2 5B1 36 D_LAN_MIDI2- 38
B L_LAN_ACTIVITY# B
1 2
27 LAN_MIDI1- LAN_MIDI1- 8 32 D_LAN_MIDI3+ D_LAN_MIDI3+ 38 C5
A3 6B1 D_LAN_MIDI3- 68P_0402_50V8J
7B1 31 D_LAN_MIDI3- 38
@
27 LAN_MIDI2+ LAN_MIDI2+ 11 22 D_LAN_ACTIVITY#
A4 0LED1 D_LAN_ACTIVITY# 38
23 D_LAN_LINK# L_LAN_LINK# 1 2
1LED1 D_LAN_LINK# 38
27 LAN_MIDI2- LAN_MIDI2- 12 52 C8
A5 2LED1 68P_0402_50V8J
46 L_LAN_MIDI0+ @
LAN_MIDI3+ 0B2 L_LAN_MIDI0-
27 LAN_MIDI3+ 14 A6 1B2 45
LAN_MIDI3- 15 41 L_LAN_MIDI1+
27 LAN_MIDI3- A7 2B2
3B2 40 L_LAN_MIDI1- For EMI
17 35 L_LAN_MIDI2+
31,38 EC_DOCKIN# SEL 4B2 L_LAN_MIDI2-
5B2 34
LAN_ACTIVITY# 19 30 L_LAN_MIDI3+
27 LAN_ACTIVITY# LAN_LINK# LED0 6B2 L_LAN_MIDI3-
27 LAN_LINK# 20 LED1 7B2 29
54 LED2
25 L_LAN_ACTIVITY#
0LED2 L_LAN_LINK#
NOTE: L : A-->B1 5 NC 1LED2 26
51
H: A-->B2 57
2LED2
PAD_GND
GND10
GND11
GND12
GND13
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9

PI3L500-AZFEX_TQFN56_11X5
1
6
9
13
16
21
24
28
33
39
44
49
53
55

A A
JAL90@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 28 of 50
5 4 3 2 1
 A B C D E

For Robson2
+1.5VS +3VS

1
C342
1
C344
1
C312
1
C343
1
C352
Mini Card Power Rating
JAL90@ JAL90@ JAL90@ JAL90@ JAL90@ Power Primary Power (mA) Auxiliary Power (mA)
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2 2
Peak Normal Normal
1 1
+3VS 1000 750
JMINI1 +3V 330 250 250 (wake enable)
1 1 2 2 +3VS
3 3 4 4 +1.5VS 500 375 5 (Not wake enable)
5 5 6 6 +1.5VS
16 MINI1_CLKREQ# 7 7 8 8
9 9 10 10
16 CLK_PCIE_MINI1# 11 11 12 12
16 CLK_PCIE_MINI1 13 13 14 14
15 15 16 16

17 17 18 18
19 19 20 20
21 22 PLT_RST_BUF#
21 22 PLT_RST_BUF# 21
23 PCIE_PTX_C_IRX_N4 23 23 24 24
23 PCIE_PTX_C_IRX_P4 25 25 26 26
27 27 28 28
29 30 MINI1_SMBCLK R234 1 @ 2 0_0402_5% ICH_SMBCLK ICH_SMBCLK 16,23,30
29 30 MINI1_SMBDATA
23 PCIE_ITX_C_PRX_N4 31 31 32 32 R229 1 @ 2 0_0402_5% ICH_SMBDATA ICH_SMBDATA 16,23,30
23 PCIE_ITX_C_PRX_P4 33 33 34 34
35 35 36 36 USB20_N7 23
37 37 38 38 USB20_P7 23
+3VS 39 39 40 40
41 42 (LED_WWAN#)
41 42
43 44 (LED_WLAN#)
43 44
For MINICARD Port80 Debug JAL90@
45 45 46 46
47 47 48 48
E51TXD_P80DATA R472 1 2 0_0402_5% CL_RST#1_R 49 50
31 E51TXD_P80DATA 49 50
E51RXD_P80CLK 51 52
31 E51RXD_P80CLK 51 52
2 2

G1
G2
G3
G3
FOX_AS0B226-S99N-7F

53
54
55
56
CONN@

For Wireless LAN

+3VS_WLAN +1.5VS

+3VS_WLAN R487 1 2 0_1206_5% +3VS 1 1 1 1 1 1

C569 C347 C311 C318 C335 C345
R478 1 @ 2 0_1206_5% +3V
2
4.7U_0805_10V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
4.7U_0805_10V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z To USB/B Connector
3 JMINI2
80mil +5VALW 3
JP11
R251 1 @ 2 0_0402_5% 1 (WAKE#) 2 +3VS_WLAN 1 +5VALW
23,30 ICH_PCIE_WAKE# 1 2 1
WLAN_BT_DATA 3 4 2
30 WLAN_BT_DATA 3 4 2
WLAN_BT_CLK 5 6 +1.5VS 3 1
30 WLAN_BT_CLK 5 6 3 SYSON# 30,37,38
16 MINI2_CLKREQ# 7 8 9 4 C6
7 8 GND 4 USB20_N4
9 9 10 10 10 GND 5 5 USB20_N4 23
11 12 6 USB20_P4 4.7U_0805_10V4Z
16 CLK_PCIE_MINI2# 11 12 6 USB20_P4 23 2
16 CLK_PCIE_MINI2 13 13 14 14 7 7
15 15 16 16 8 8 USB_OC#4 23
ACES_87212-08G0L
17 18 CONN@
17 18 WL_OFF#
19 19 20 20 WL_OFF# 31
21 22 PLT_RST_BUF#
21 22 +3V_WLAN R246 1
23 PCIE_PTX_C_IRX_N2 23 23 24 24 2 0_0603_5% +3VS
25 26 R242 1 @ 2 0_0603_5% +3V
23 PCIE_PTX_C_IRX_P2 25 26
27 27 28 28
29 30 MINI2_SMBCLK R237 1 @ 2 0_0402_5% ICH_SMBCLK
29 30 MINI2_SMBDATA R230 1
23 PCIE_ITX_C_PRX_N2 31 31 32 32 @ 2 0_0402_5% ICH_SMBDATA
23 PCIE_ITX_C_PRX_P2 33 33 34 34
35 35 36 36 USB20_N8 23
37 37 38 38 USB20_P8 23
+3VS_WLAN 39 39 40 40
41 42 (LED_WWAN#)
41 42
43 44 (LED_WLAN#) MINI1_LED# 32
43 44
For MINICARD Port80 Debug 45 45 46 46

E51TXD_P80DATA R531 1 2 0_0402_5% CL_RST#2_R

47
49
47 48 48
50
(9~16mA)
E51RXD_P80CLK 49 50
51 51 52 52
G1
G2
G3
G3

4 FOX_AS0B226-S99N-7F 4
53
54
55
56

CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 29 of 50
A B C D E
 A B C D E

New Card Power Switch

New Card Socket (Left/TOP)
U14 +3VALW_CARD +3VS_CARD +1.5VS_CARD
40mil JEXP1
+1.5VS 12 1.5Vin 1.5Vout 11 +1.5VS_CARD Imax = 0.275A Imax = 1.35A Imax = 0.75A
14 1.5Vin 1.5Vout 13
1 GND
60mils C292
1 1
C294 C304
1 1
C303 C281
1 1
C282
23 USB20_N1 2 USB_D-
+3VS 2 3.3Vin 3.3Vout 3 +3VS_CARD 23 USB20_P1 3 USB_D+
1 CP_USB# 1
4 3.3Vin 3.3Vout 5 4 CPUSB#
40mil 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 5
ABO@ 2 2
0.1U_0402_16V4Z ABO@ 2 2
0.1U_0402_16V4Z ABO@ 2 2
0.1U_0402_16V4Z RSV
+3V 17 AUX_IN AUX_OUT 15 +3VALW_CARD 6 RSV
ABO@ ABO@ ABO@ 16,23,29 ICH_SMBCLK 7
PCI_RST# SMB_CLK
21 PCI_RST# 6 SYSRST# OC# 19 16,23,29 ICH_SMBDATA 8 SMB_DATA
+1.5VS_CARD 9 +1.5V
SYSON 20 8 PERST1# 10
31,37,43,44 SYSON SHDN# PERST# +1.5V
23,29 ICH_PCIE_WAKE# 11 WAKE#
SUSP# 1 16 +3VALW_CARD 12
31,33,37,45 SUSP# STBY# NC +3.3VAUX
PERST1# 13
CP_PE# PERST#
10 CPPE# GND 7 +3VS_CARD 14 +3.3V
(Internal Pull High to AUXIN) +3VS 15
CP_USB# CLKREQ1# +3.3V
9 CPUSB# Thermal_Pad 21 16 CLKREQ#
(Internal Pull High to AUXIN) 23 CP_PE# CP_PE# 17
RCLKEN1 +3VS CPPE#
18 RCLKEN 1 16 CLK_PCIE_CARD# 18 REFCLK-
C307 19
16 CLK_PCIE_CARD REFCLK+
G577NSR91U_TQFN20_4x4 ABO@ 20 GND

1
0.1U_0402_16V4Z 21
2 23 PCIE_PTX_C_IRX_N1 PERn0
ABO@ R220 22
23 PCIE_PTX_C_IRX_P1 PERp0

5
10K_0402_5% U16 23
ABO@ CLKREQ1# GND
2 24

G Vcc
B 23 PCIE_ITX_C_PRX_N1 PETn0
4 EXP_CLKREQ# 16 23 PCIE_ITX_C_PRX_P1 25

2
Y PETp0
1 A 26 GND

1
+3VS +3V +1.5VS D ABO@ 27 29

3
RCLKEN1 2 Q25 NC7SZ32P5X_NL_SC70-5 GND GND
28 GND GND 30
G 2N7002_SOT23
1 1 1 S ABO@ FOX_1CH4110C_LT

3
C310 C298 C283 CONN@

10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z

ABO@ 2 ABO@ 2 ABO@ 2
2 2

USB CONN. (Stack-up Type)

Bluetooth Conn. Finger Print Conn.
+USB_VCCA +USB_VCCA
W=80mils
+USB_VCCA
W=80mils
+USB_VCCA
+3VALW +3VS +3V +3VS
1 1
1 1
C523 + C187 C481+ C217
1

1 1 R577 R578 220U_C6_6.3V_M_R15 @ 150U_D2_6.3VM

C316 C332 0_0603_5% 0_0603_5% 2 2 2 2
ABO@ ABO@ @ 470P_0402_50V7K 470P_0402_50V7K
0.1U_0402_16V4Z 1U_0603_10V4Z
2

2
3

2 2
S
G
3 ABO@ JP8 JUSB2 JUSB1 3
31 BT_ON# 1 2 2
R222 10K_0402_5% Q24 C163 6 1 1
ABO@ AO3413_SOT23-3 0.1U_0402_16V4Z G2 USB20_N0 VCC USB20_N2 VCC
D 5 23 USB20_N0 2 23 USB20_N2 2
1

+FP_VCC G1 USB20_P0 D- USB20_P2 D-

1 2 1 4 4 23 USB20_P0 3 D+ 23 USB20_P2 3 D+
C317 W=40mils USB20_N10 3 4 4
23 USB20_N10 3 GND GND
ABO@ +BT_VCC USB20_P10 2
23 USB20_P10 2
0.1U_0402_16V4Z 1 5 5
2 1 GND1 GND1
1 1 6 GND2 6 GND2
1

C308 C325 ACES_85201-04051 7 7

ABO@ ABO@ R235 GND3 GND3
CONN@ 8 GND4 8 GND4
4.7U_0805_10V4Z 300_0603_5%
2 2 ABO@ SUYIN_020173MR004G565ZR SUYIN_020173MR004G565ZR
0.1U_0402_16V4Z CONN@ CONN@
2
1

D
2 Q26
G 2N7002_SOT23 +3V
S ABO@ 80mil
3

+5VALW

1
+USB_VCCA R170
+BT_VCC U33 0_0402_5%
1 8 R169 1 2
GND OUT USB_OC#2 23
JP10 2 7 100K_0402_5%
D25 IN OUT
1 9 3 6

2
1 GND USB20_P0 USB20_P2 IN OUT
2 2 6 CH3 CH2 3 1 4 EN# FLG 5 1 2 USB_OC#0 23
3 C522 R171
23 USB20_P5 3
4 TPS2061DRG4_SO8 10K_0402_5% 1
23 USB20_N5 4
5 4.7U_0805_10V4Z C240
5 2
29 WLAN_BT_DATA 6 6 +USB_VCCA 5 Vp Vn 2
7 0.1U_0402_16V4Z
29 WLAN_BT_CLK 7 2
8 8 GND 10
4 4
29,37,38 SYSON#
ACES_87213-0800G USB20_N2 4 1 USB20_N0
CH4 CH1
CONN@
@ CM1293-04SO_SOT23-6

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 30 of 50
A B C D E
 5 4 3 2 1

+3VALW For EC Tools

L13
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 +EC_VCCA +3VALW
1 1 C299 1 1 2
1
2 FBM-L11-160808-800LMT_0603 JP13 Place on RAM door
C284 1 KSI[0..7] 1
+3VALW KSI[0..7] 32 1
C319 C277 C267 C268 2 E51RXD_P80CLK
KSO[0..17] 2 E51RXD_P80CLK 29
1000P_0402_50V7K 1000P_0402_50V7K C302 3 E51TXD_P80DATA
2 2 2 2 1 1 KSO[0..17] 32 3 E51TXD_P80DATA 29
1 2 EC_PME# 4
R203 10K_0402_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 4

ECAGND
@ ACES_85205-0400
@
D
+3VALW Place on MiniCard D
JP9

111
125
22
33
96

67
1 1

9
U13 2 E51RXD_P80CLK
2 E51TXD_P80DATA
3

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
3
4 4
ACES_85205-0400
1 21 INVT_PWM @
22 EC_GA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM 18
2 23 BEEP#
22 EC_KBRST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# 34
23 SERIRQ 3 SERIRQ# FANPWM1/GPIO12 26 ENCODER_DIR 35
22 LPC_FRAME# 4 LFRAME# ACOFF/FANPWM2/GPIO13 27 ACOFF 42
C291 LPC_AD3 5 2 1 ECAGND 3S/4S# 1 2
22 LPC_AD3 LAD3
@ 22P_0402_50V8J LPC_AD2 7 PWM Output C322 0.01U_0402_16V7K R188 4.7K_0402_5%
22 LPC_AD2 LAD2
2 1 R196 2 1 @ 33_0402_5% LPC_AD1 8 63 BATT_TEMP
22 LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP 40
LPC_AD0 BATT_OVP
22 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64 BATT_OVP 42
ADP_I/AD2/GPIO3A 65 ADP_I 42
12 AD Input 66 AD_BID0
16 CLK_PCI_LPC PCICLK AD3/GPIO3B
8,21,23,26,27 PLT_RST# 13 PCIRST#/GPIO05 AD4/GPIO42 75
37 76 +3VALW
ECRST# SELIO2#/AD5/GPIO43 PGD_IN 46
EC_SCI# 20
23 EC_SCI# SCI#/GPIO0E
+3VALW 2 1 23 PM_CLKRUN# 38 CLKRUN#/GPIO1D
R223 47K_0402_5% 68 DAC_BRIG ID_JAL90_JAW50# 2 1
DAC_BRIG/DA0/GPIO3C DAC_BRIG 18
2 1 70 EN_DFAN1 R186 JAL90@ 100K_0402_5%
EN_DFAN1/DA1/GPIO3D EN_DFAN1 36
C320 0.1U_0402_16V4Z DA Output 71 IREF 2 1
IREF/DA2/GPIO3E IREF 42
KSI0 55 72 R540 JAW50@
KSI0/GPIO30 DA3/GPIO3F CALIBRATE# 42
KSI1 56 100K_0402_5%
KSI2 KSI1/GPIO31
57 KSI2/GPIO32
+3VALW KSI3 58 83 EC_MUTE
KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE 35
C KSI4 59 84 C
KSI4/GPIO34 PSDAT1/GPIO4B EC_I2C_INT1 32 +3VALW
KSI5 60 85
KSI5/GPIO35 PSCLK2/GPIO4C DOCKIN# 38
2

KSI6 61 PS2 Interface 86 BT_LED# 32

R209 KSI7 KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK 65W/90W#
62 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E 87 TP_CLK 32 2 1
10K_0402_5% KSO0 39 88 TP_DATA R187 100K_0402_5%
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA 32
KSO1 40
KSO2 KSO1/GPIO21
41
1

KSO3 KSO2/GPIO22 3S/4S#

42 KSO3/GPIO23 SDICS#/GPXOA00 97 3S/4S# 42
D13 KSO4 43 98 65W/90W#
KSO4/GPIO24 SDICLK/GPXOA01 65W/90W# 42
EC_RCIRRX KSO5 SBPWR_EN
33 RCIRRX 1 2
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
ID_JAL90_JAW50#
SBPWR_EN 37,44 Analog Board ID definition,
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109
CH751H-40PT_SOD323-2 KSO7 46 SPI Device Interface Please see page 3.
KSO8 KSO7/GPIO27
47 KSO8/GPIO28
KSO9 48 119 EC_SPIDI/FWR#
KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO 32 +3VALW
+5VS KSO10 49 120 EC_SPIDO/FRD#
KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI 32
KSO11 50 SPI Flash ROM 126 EC_SPICLK
KSO11/GPIO2B SPICLK/GPIO58 EC_SPICLK 32
KSO12 51 128 EC_SPICS#/FSEL#
KSO12/GPIO2C SPICS# EC_SPICS#/FSEL# 32

2
1 2 TP_CLK KSO13 52 KSO13/GPIO2D
R195 4.7K_0402_5% KSO14 53 R218
KSO14/GPIO2E
1 2 TP_DATA KSO15 54 KSO15/GPIO2F CIR_RX/GPIO40 73 EC_RCIRRX Ra 100K_0402_5%
R194 4.7K_0402_5% KSO16 81 74
KSO16/GPIO48 CIR_RLC_TX/GPIO41 ENCODER_PULSE 35
KSO17 82 89 FSTCHG
FSTCHG 42

1
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 BATT_GRN_LED# AD_BID0
BATT_CHGI_LED#/GPIO52 90 BATT_GRN_LED# 32
91 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED# 32

2
EC_SMB_CK1 77 GPIO 92 BATT_AMB_LED# 1
17,40 EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BATT_AMB_LED# 32
EC_SMB_DA1 78 93 PWR_LED R215 C306
17,40 EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PWR_LED 32
EC_SMB_CK2 79 SM Bus 95 SYSON Rb ABO@
+3VALW 4,32 EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON 30,37,43,44
EC_SMB_DA2 80 121 VR_ON 33K_0402_5%
4,32 EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 33,46 2
127 ACIN 0.1U_0402_16V4Z
ACIN 23,32,39,42

1
B AC_IN/GPIO59 B
1 2 EC_SMB_CK1
R206 2.2K_0402_5%
1 2 EC_SMB_DA1 23 PM_SLP_S3#
PM_SLP_S3# 6 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 100 EC_RSMRST# 23
R207 2.2K_0402_5% PM_SLP_S5# 14 101 EC_LID_OUT#
23 PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# 23
EC_SMI# 15 102 EC_ON
23 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 33
LID_SW# 16 103
32 LID_SW# LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SWI# 23
EC_GPIOB 17 104 EC_PWROK EC_CRY1 EC_CRY2
SUSP#/GPIO0B ICH_PWROK/GPXO06 EC_PWROK 23,33
EC_GPIOC 18 GPO 105 BKOFF#
PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# 18
1 2 LID_SW# 27 EC_PME#
EC_PME# 19 EC_PME#/GPIO0D GPIO WL_OFF#/GPXO09 106 WL_OFF#
WL_OFF# 29 1 1
R198 100K_0402_5% 25 107 C271 C270
8 MCH_TSATN_EC# EC_THERM#/GPIO11 GPXO10 EC_ACIN 17

4
FAN_SPEED1 28 108
36 FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11 EC_DOCKIN# 28,38
BT_ON# 29 15P_0402_50V8J 15P_0402_50V8J

OUT
IN
30 BT_ON# FANFB2/GPIO15 2 2
E51TXD_P80DATA 30
E51RXD_P80CLK EC_TX/GPIO16
31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 PM_SLP_S4# 23
ON/OFF 32 112 ENBKL
+3VS 33 ON/OFF ON_OFF/GPIO18 ENBKL/GPXID2 ENBKL 10,17
PWR_SUSP_LED EAPD

NC

NC
32 PWR_SUSP_LED 34 PWR_LED#/GPIO19 GPXID3 114 EAPD 34
NUM_LED# 36 GPI 115
32 NUM_LED# NUMLED#/GPIO1A GPXID4 EC_THERM# 23
116 SUSP#
SUSP# 30,33,37,45

3
GPXID5
1 2 EC_SMB_CK2 GPXID6 117 PBTN_OUT#
PBTN_OUT# 23
R200 2.2K_0402_5% 118
GPXID7 ARCADE# 32
1 2 EC_SMB_DA2 EC_CRY1 122 XCLK1
X2
R201 2.2K_0402_5% EC_CRY2 123 124 32.768KHZ_12.5P_MC-306
XCLK0 V18R
1
AGND

C269 For KB926 C0 reversion

GND
GND
GND
GND
GND

+3VS 4.7U_0805_10V4Z C323 100P_0402_50V8J

KB926QFC0_LQFP128_14X14 2 BATT_TEMP 2 1
11
24
35
94
113

69

20mil C324 100P_0402_50V8J

1 @ 2 L12 BATT_OVP 2 1
A A
R560 4.7K_0402_5% ECAGND 2 1 C276 100P_0402_50V8J
1 JAL90GM@
2 FBM-L11-160808-800LMT_0603 ACIN 2 1
R561 4.7K_0402_5%
1 @ 2 EC_GPIOB
32 EC_ESB_CK
R558 0_0402_5%
1 @ 2 EC_GPIOC
32 EC_ESB_DA
R559 0_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

17,20 DVI_DET 1 JAL90GM@

2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
R555 0_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
JAL90GM@ B I
20 EC_DVI_DET
R550
1 2
0_0402_5%
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 31 of 50
5 4 3 2 1
 U19
To TP/B Conn.
JP7
+3VALW 1 2 C326 1 2 0.1U_0402_16V4Z EC_SPICS#/FSEL# 1 8 +SPI_VCC
R224 0_0603_5% SPI_WP# CS# VCC EC_SPICLK_R
3 WP# SCLK 6 +5VS 6 6 8 8
SPI_HOLD# 7 5 EC_SO_SPI_SI TP_CLK 5 7
HOLD# SI 31 TP_CLK 5 7
+SPI_VCC 4 2 EC_SI_SPI_SO TP_DATA 4
GND SO 31 TP_DATA 4
LEFT_BTN# 3
U18 MX25L512AMC-12G_SO8 RIGHT_BTN# 3
2 2
EC_SPICS#/FSEL# 1 8 @ 1
31 EC_SPICS#/FSEL# CE# VDD 1
R248 1 2 4.7K_0402_5% SPI_WP# 3 6 EC_SPICLK_R R226 1 2 0_0402_5% Reserved for BIOS simulator. 1 1
WP# SCK EC_SPICLK 31
R225 1 2 4.7K_0402_5% SPI_HOLD# 7 5 R227 1 2 0_0402_5% C148
+3VALW HOLD# SI R247 1
EC_SO_SPI_SI 31 Footprint SO8 ACES_85201-0605
4 VSS SO 2 2 0_0402_5% EC_SI_SPI_SO 31
C145
100P_0402_50V8J 100P_0402_50V8J CONN@
MX25L8005M2C-15G_SOP8 2 2

To Media/B Conn. TP_CLK

1 @ 2 +5VS TP_DATA
31 EC_ESB_CK
ENE suggestion SPI Frequency over 66MHz R562 0_0402_5%

3
1 @ 2 +5VS +3VS
SST: 50MHz 31 EC_ESB_DA
R563 0_0402_5% C147
MXIC: 70MHz JP2 D7
1 2 6 8 0.1U_0402_16V4Z @
ST: 40MHz 4,31 EC_SMB_CK2 6 8
R564 0_0402_5% 5 7 PSOT24C_SOT23
MEDIA_CK 5 7
4,31 EC_SMB_DA2 1 2 4

1
R565 0_0402_5% MEDIA_DA 4
3 3
31 EC_I2C_INT1 2 2
KSI[0..7] 1
INT_KBD Conn. KSO[0..17]
KSI[0..7] 31 1
ACES_85201-0605
SW2
SMT1-05-A_4P
SW3
SMT1-05-A_4P
KSO[0..17] 31
CONN@ LEFT_BTN# 3 1 RIGHT_BTN#3 1

JP4 4 2 4 2
(Left) KSO0 26 28

5
6

5
6
KSO1 KSO0 G2
25 KSO1 G1 27
KSO2 24
KSO3
KSO4
23
22
KSO2
KSO3 To LED/B Conn. (POWER/B) +5VS
+5VS
KSO5 KSO4
21 KSO5 1 JAL9050@
2
KSO6 20 R572 0_0402_5%
KSO7 KSO6
19 KSO7

1
KSO8 PWR_SUSP_LED#

S
18 KSO8 1 3
KSO9 17 Q37 R576 R575
KSO9

3
KSO10 16 JP6 AO3413_SOT23-3 10K_0402_5% 10K_0402_5%
KSO11 KSO10 +5VS_LED KAL20@ KAL20@ Q12B
15 1

G
KAL20@

2
KSO12 KSO11 1 2N7002DW-T/R7_SOT363-6
14 2

2
KSO13 KSO12 2 BT_LED
13 KSO13 3 3 +5VALW 31 PWR_SUSP_LED 5
KSO14 12 4
KSO14 4

1
KSO15 11 5 MEDIA_LED# Q54A Q54B

4
KSO16 KSO15 5 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 R184
10 KSO16 6 6 NUM_LED# 31
KSO17 9 7 KAL20@ KAL20@
KSO17 7 CAPS_LED# 31
KSI0 8 8 PWR_LED# BT_LED 2 5 BT_LED# PWR_LED# 10K_0402_5%
KSI1 KSI0 8
7 9 ON/OFFBTN# 33

2
KSI1 9

6
KSI2 6 10 PWR_SUSP_LED# Q12A

4
KSI3 KSI2 10 ACIN# 2N7002DW-T/R7_SOT363-6
5 KSI3 11 11
KSI4 4 12 LID_SW#
KSI4 12 LID_SW# 31
KSI5 3 13 31 PWR_LED 2
KSI6 KSI5 13
2 KSI6 14 14 +3VALW

1
KSI7 1 17 15 1 JAL90@ 2 ARCADE_BTN#

1
KSI7 G17 15 R570 0_0402_5% R183
(Right) 18 G18 16 16
1 KAL20@ 2 MINI1_LED# +3VALW
ACES_88747-2601 KSO16 C596 1 2 @ 100P_0402_50V8J ACES_85201-16051 R571 0_0402_5% 10K_0402_5% 1 2
CONN@ CONN@ R185 100K_0402_5%

2
KSO17 C597 1 2 @ 100P_0402_50V8J D12
2 ARCADE# 31
ARCADE_BTN# 1
KSO15 C48 1 2 @ 100P_0402_50V8J KSO7 C40 1 2 @ 100P_0402_50V8J 3 51ON#

KSO14 C47 1 2 @ 100P_0402_50V8J KSO6 C39 1 2 @ 100P_0402_50V8J

To BTN/B Conn. JP5
ACIN#
DAN202UT106_SC70-3
51ON# 33,39

1 +5VS

1
KSO13 C46 D
1 2 @ 100P_0402_50V8J KSO5 C38 1 2 @ 100P_0402_50V8J KSO0 2 +3VS
MINI1_LED# Q15 2 +3VS
3 MINI1_LED# 29 ACIN 23,31,39,42
KSO12 C45 1 2 @ 100P_0402_50V8J KSO4 C37 1 2 @ 100P_0402_50V8J KSI1 WL_BTN# KSI1 JAL90@ G
4 KSI4 2N7002_SOT23 S Q45A

3
5

2
KSI2 BT_BTN# KSO0 2N7002DW-T/R7_SOT363-6
KSI0 C49 6
1 2 @ 100P_0402_50V8J KSO3 C36 1 2 @ 100P_0402_50V8J 7
KSI2
KSI3 EMAIL_BTN# BT_LED# 1 6
8 BT_LED# 31 26 5IN1_LED#
KSO11 C44 1 2 @ 100P_0402_50V8J KSI4 C53 1 2 @ 100P_0402_50V8J KSI3
9 SATA_LED# MEDIA_LED#
KSO10 C43 KSO2
KSI4 IE_BTN# 10 22 SATA_LED# 4 3
1 2 @ 100P_0402_50V8J C35 1 2 @ 100P_0402_50V8J 11
KSI1 C50
KSI5 E-KEY_BTN# 12
1 2 @ 100P_0402_50V8J KSO1 C34 1 2 @ 100P_0402_50V8J Q45B

5
ACES_85201-1205 +3VS 2N7002DW-T/R7_SOT363-6
CONN@
KSI2 C51 1 2 @ 100P_0402_50V8J KSO0 C33 1 2 @ 100P_0402_50V8J

KSO9 C42 1 2 @ 100P_0402_50V8J KSI5 C54 1 2 @ 100P_0402_50V8J SW1 PWR_LED# C89 1 2 @ 100P_0402_50V8J
SMT1-05-A_4P +3VS
KSI3 C52 1 2 @ 100P_0402_50V8J KSI6 C55 1 2 @ 100P_0402_50V8J
KSO0
3 1
KSI5
R556
10K_0402_5%
ON/OFFBTN# C87 1 2 @ 100P_0402_50V8J FOR EMI
KSO8 C41 1 2 @ 100P_0402_50V8J KSI7 C56 1 2 @ 100P_0402_50V8J 4 2 1 @2 MINI1_LED# C74 1 2 @ 100P_0402_50V8J

JAL90@ BT_LED# C79 1 2 @ 100P_0402_50V8J

5
6

(E-KEY_BTN#) KSI5 C373 1 2 @ 100P_0402_50V8J

KSI5 PWR_SUSP_LED#C88 1 2 @ 100P_0402_50V8J

KSO0 KSO0 C80 1 2 @ 100P_0402_50V8J

R268 LED1 ARCADE_BTN# C86 1 2 @ 100P_0402_50V8J
3

2
4.99K_0402_1% SW4 KSI1 C81 1 2 @ 100P_0402_50V8J
Compal Footprint +5VALW 1 JAL90@ 2 3 YG 1 PWR_LED# SMT1-05-A_4P NUM_LED# C91 1 2 @ 100P_0402_50V8J
3 1 D29 KSI2 C82 1 2 @ 100P_0402_50V8J
4 2 R266 KSO0 KSI5 SM05T1G_SOT23-3 CAPS_LED# C92 1 2 @ 100P_0402_50V8J
+5VALW 1 JAL90@ 2 4 A 2 PWR_SUSP_LED# 4 2 @ KSI3 C83 1 2 @ 100P_0402_50V8J
3 1 4.99K_0402_1% MEDIA_LED# C90 1 2 @ 100P_0402_50V8J
1

JAW50@ KSI4 C84 1 2 @ 100P_0402_50V8J

5
6

HT-297UD/CB _BLUE/AMB_0603 (E-KEY_BTN#)

JAL90@
For ESD 10/31
R269 LED2
1.69K_0402_1%
1 2 3 1 BATT_GRN_LED#
+5VALW YG
BATT_GRN_LED# 31 Security Classification Compal Secret Data Compal Electronics, Inc.
R267 2007/09/20 2008/09/20 Title
4 2 BATT_AMB_LED#
Issued Date Deciphered Date
+5VALW 1 2
2.49K_0402_1%
A
BATT_AMB_LED# 31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
HT-297DQ/GQ_AMB/YG_0603 B I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 32 of 50
 A B C D E

Power Button
ON/OFF switch HDA MDC Conn.
+3V

+3VALW
TOP Side JMDC1
GLPM@ 1
C351
15mil 1
R252
2
0_0402_5%
+3V
1 2
1 R254 @ 10K_0603_5% +MDC_VCC 1U_0603_10V4Z 1
1 GND1 RES0 2 1 2 +1.5V

2
R250 0_0402_5% 2
22 HDA_SDOUT_MDC 3 IAC_SDATA_OUT RES1 4
1 2 R236 5 6 JAL90GM@
GND2 3.3V +3V
R493 @ 10K_0603_5% 22 HDA_SYNC_MDC 7 8
100K_0402_5% HDA_SDIN1_MDC IAC_SYNC GND3
22 HDA_SDIN1 1 2 9 IAC_SDATA_IN GND4 10
Bottom Side 22 HDA_RST_MDC#
R249 33_0402_5% 11 12 HDA_BITCLK_MDC 22

1
D14 IAC_RESET# IAC_BITCLK

1
2 ON/OFF 31
ON/OFFBTN# 1 R253

GND
GND
GND
GND
GND
GND
32 ON/OFFBTN#
3 51ON# 0_0402_5%
51ON# 32,39
DAN202UT106_SC70-3 ACES_88018-124G

13
14
15
16
17
18

2
CONN@ 1
C346
Connector for MDC Rev1.5
22P_0402_50V8J

1
2
2
C334 D16

1000P_0402_50V7K RLZ20A_LL34
1 For EMI

2
1
D
EC_ON 2 Q29
31 EC_ON
G
2

S 2N7002_SOT23
R238 3
10K_0402_5%
2 2
1

Power ON Circuit
+3VS

+3VALW +3VALW
1

U17A U17B
R243 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
14

14

180K_0402_5%
D15 @
P

P
2

1 2 1 2 3 4 SYS_PWROK 1 2
31,46 VR_ON I O I O EC_PWROK 23,31
R244 @ 0_0402_5%
G

CH751H-40PT_SOD323-2 2
@
For South Bridge
7

C340
1U_0603_10V6K
@ 1

3 3

+3VS

+3VALW +3VALW
+RTCBATT
1

R245
10K_0402_1% U17C U17D
14

14

R557 @ SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14

CIR

2
10K_0402_1%
P

P
2

1 2 5 6 9 8 +3VALW R432
30,31,37,45 SUSP# I O I O VS_ON 43
2 1K_0402_5%
1

D
For +VCCP/+1.05VS

1
SUSP 2 C338
37,45 SUSP
7

1 1
G 0.1U_0402_16V7K R512
Q28 S 1 100_0805_5% D27
3

2N7002_SOT23 JAL90@

2
IR1
3 4 RCIRRX +RTCVCC
Vs OUT RCIRRX 31
1 2

2
+3VS GND GND
1
+3VALW +3VALW C592 TSOP36236TR_4P
C314 1 BAS40-04_SOT23-3
JAL90@ JAL90@ C593
+CHGRTC
1

1 2 0.1U_0402_16V4Z 4.7U_0805_10V4Z JAL90@ 1

R217 2 1000P_0402_50V7K C528
31.6K_0402_1% U17E U17F 2
14

14

PM@ SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 0.1U_0402_16V4Z

2
P

P
2

11 I O 10 13 I O 12 VGA_ON 17
1

4 D 4
2
SUSP 2
7

G C313
Q22 S 1U_0603_10V6K
3

2N7002_SOT23 PM@ 1
PM@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 33 of 50
A B C D E
 A B C D E F G H

+VDDA

+5VAMP
60mil U37 (output = 300 mA)

1
R498 L45 1 2 1
10K_0402_5%
+5VS
KC FBM-L11-201209-221LMAT_0805 IN
OUT 5 40mil +VDDA
1 1 2 GND
L43 1 2 C566 C565 1 4.75V

2
KC FBM-L11-201209-221LMAT_0805 3 4 C568
10U_0805_10V4Z SHDN BYP
1 2
C585 1U_0402_6.3V4Z 2 2
0.1U_0402_16V4Z G9191-475T1U_SOT23-5 4.7U_0805_10V4Z
1

1
C575 2
R497
10K_0402_5%
1 2 1

2
C587 0.01U_0402_16V7K
1 2 MONO_IN BOM Option
1U_0402_6.3V4Z
ALC268 268@

1
C
C595 1 2 1
R515
2 2 Q42
1
R496
2
1.3K_0402_1% ALC888S-VB 888VB@
31 BEEP# B
1U_0402_6.3V4Z
560_0402_5% E 2SC2411K_SOT23 ALC888S-VC 888VC@

3
C594 1 R514 L46
23 SB_SPKR 2 1 2
1U_0402_6.3V4Z MBK1608121YZF_0603
10mil

1
560_0402_5% +3VS_DVDD 1 2

R513
D28
CH751H-40PT_SOD323-2
HD Audio Codec 1 1
+3VS

1
10K_0402_5% C586 C589
R508

2
0.1U_0402_16V4Z 0_0603_5%
2 2
GLPM@
10U_0805_10V4Z

2
L47
+AVDD_HDA MBK1608121YZF_0603
10mil +1.5VS_DVDD 1 2 +1.5VS
JAL90GM@
L44 1 2 0.1U_0402_16V4Z 40mil 1 1
+VDDA
FBM-L11-160808-800LMT_0603 1 1 C588 C591
C580
C572 0.1U_0402_16V4Z 10U_0805_10V4Z
2 10U_0805_10V4Z 2 2 2

25

38

9
2 2 U38

DVDD
AVDD1

AVDD2

DVDD_IO
MIC2_VREFO

14 35 AMP_LEFT
LINE2-L FRONT_L AMP_LEFT 35

1
15 36 AMP_RIGHT R445
LINE2-R FRONT_R AMP_RIGHT 35
2.2K_0402_5%
1 2 MIC2_C_L 16 39 HP_LEFT For EMI 5/14 15mil 268@
MIC2_L SURR_L HP_LEFT 35
INT_MIC_R C583 268@ 4.7U_0805_6.3V6K

2
1 2 MIC2_C_R 17 41 HP_RIGHT DMIC_CLK_R INT_MIC_R
MIC2_R SURR_R HP_RIGHT 35
C582 268@ 4.7U_0805_6.3V6K R442 268@ FBM-11-160808-700T_0603
LINE_L 1 2 LINE_C_L 23 45 DMIC_DATA_R 1
35 LINE_L LINE1_L SIDE_L
C577 4.7U_0805_6.3V6K R439 268@ FBM-11-160808-700T_0603 C535
LINE_R 1 2 LINE_C_R 24 46 DMIC_CLK_268 1 2 DMIC_CLK 268@
35 LINE_R LINE1_R SIDE_R
C570 4.7U_0805_6.3V6K For EMI R490 @ 0_0402_5% 220P_0402_50V7K
2
18 CD_L CENTER 43

20 CD_R LFE 44 1 2 1 2 C590

R500 0_0402_5% 22P_0402_50V8J
19 CD_GND
BITCLK 6 HDA_BITCLK_AUDIO 22
MIC1_L 1 2 MIC1_C_L 21
35 MIC1_L MIC1_L
C581 4.7U_0805_6.3V6K
35 MIC1_R
MIC1_R
C579
1 2 MIC1_C_R 22
4.7U_0805_6.3V6K MIC1_R SDATA_IN 8 HDA_SDIN0_AUDIO 1
R501
2
33_0402_5%
HDA_SDIN0 22 Digital MIC
MONO_IN 12 37
PCBEEP PIN37_VREFO +3VS
29 JP1
LINE1_VREFO
22 HDA_RST_AUDIO# 11 RESET# 1 1
3 DMIC_CLK DMIC_CLK_R 3
LINE2_VREFO 31 2 2
22 HDA_SYNC_AUDIO 10 10mil R441 888VC@ 0_0603_5% 3 5
SYNC DMIC_DATA DMIC_DATA_R 3 G1
MIC1_VREFO_L 28 MIC1_VREFO_L 4 4 G2 6
22 HDA_SDOUT_AUDIO 5 R438 888VC@ 0_0603_5%
SDATA_OUT ACES_88266-04001
Place close to Codec HDA_GPIO0 MIC1_VREFO_R 32 MIC1_VREFO_R
CONN@
2 SPDIFO2

2
HDA_GPIO3 3 30 MIC2_VREFO
R492 2 GPIO0/DMIC_CLK MIC2_VREFO
35,38 HP_PLUG# 1 39.2K_0402_1% SENSE_A 13 SENSE A 10mil D17 1 2
34 27 CODEC_VREF SM05T1G_SOT23-3
R494 1 SENSE B VREF
35,38 LINEIN_PLUG# 2 10K_0402_1% 1 1 @ C603
R495 2 1 20K_0402_1% 47 40 C574 220P_0402_50V8J
35,38 MIC_PLUG# 31 EAPD SPDIFI/EAPD JDREF 2 1
C571 For ESD 10/11 JAL90@

1
1
35,38 SPDIF 1 2SPDIF_R 48 SPDIFO SENSE C 33 0.1U_0402_16V4Z 10U_0805_10V4Z C604
R491 0_0402_5% R488 2 2 220P_0402_50V8J
DMIC_DATA 1 2 4 26 20K_0402_1% JAL90@
R499 888VC@ 0_0402_5% GPIO1/DMIC_DATA AVSS1
7 DVSS AVSS2 42
1 2

2
R504 888VB@ 0_0402_5% ALC888S-VC_LQFP48_7x7
Sense Pin Impedance Codec Signals 1 2 888VC@
1
R433
2
0_0805_5%
1
R479
2
0_0805_5%
R505 268@ 0_0402_5%
39.2K PORT-A (PIN 39, 41) DGND AGND
1 2 1 2
R446 0_0805_5% R489 0_0805_5%
20K PORT-B (PIN 21, 22)
SENSE A
1 2 1 2
10K PORT-C (PIN 23, 24) DMIC_DATA 1 2 HDA_GPIO0 R458 0_0805_5% R509 0_0805_5%
R506 @ 0_0402_5%
SPDIF_HDMI 1 2
17 SPDIF_HDMI
5.1K PORT-D (PIN 35, 36) R502 888VC@ 0_0402_5%

DMIC_DATA 1 2 HDA_GPIO3 GND GNDA GND GNDA

4 R507 888VB@ 0_0402_5% 4
39.2K PORT-E (PIN 14, 15) DMIC_CLK 1 2
R503 888VC@ FBMA-L10-160808-301LMT_0603
20K PORT-F (PIN 16, 17)
SENSE B For EMI
10K PORT-G (PIN 43, 44)
Security Classification Compal Secret Data Compal Electronics, Inc.
5.1K PORT-H (PIN 45, 46) Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 34 of 50
A B C D E F G H
 A B C D E

+5VAMP Int. Speaker Conn.

W=40mil 20mil JP3
+3VS
1 1 SPKL+ R9 1 2 0_0603_5% SPK_L+ 1
SPKL- R11 0_0603_5% SPK_L- 1
1 1 2 2 2
C541 C536 SPKR+ R26 1 2 0_0603_5% SPK_R+ 3 5
C542 0.1U_0402_16V4Z SPKR- R28 0_0603_5% SPK_R- 3 G1
1 2 4 4 G2 6
C559 0.1U_0402_16V4Z 2 2
0.47U_0603_16V4Z 2 4.7U_0805_10V4Z ACES_88266-04001

2
1 2 AMP_RIGHT_C-1 1 2 AMP_RIGHT_C CONN@
34 AMP_RIGHT C554 1U_0402_6.3V4Z D3

11

19

20
10

1
1 2 AMP_LEFT_C-1 1 2 AMP_LEFT_C U36 D1 SM05T1G_SOT23-3
34 AMP_LEFT C563 C555 1U_0402_6.3V4Z SM05T1G_SOT23-3 @

CVDD

HVDD

PVDD
PVDD

VDD
1

1
0.47U_0603_16V4Z @
1 R473 R467 1

1
2.2K_0402_5% 2.2K_0402_5% 3 22 SPKR+
INR_A ROUT+ SPKR-
5 21

2
INL_A ROUT-
HPF Fc = 154Hz For ESD 10/11
R450 1 2 100K_0402_5% 27 8 SPKL+
/AMP EN LOUT+ SPKL-
LOUT- 9
+5VAMP R451 1 2 100K_0402_5% 24 HP EN HPOUT_R
HP_R 17
+5VAMP HP_RIGHT 1 2 HP_RIGHT_C 1 2 HP_RIGHT_R 4 18 HPOUT_L +5VAMP
34 HP_RIGHT C560 4.7U_0805_6.3V6K R468 39K_0402_5% HP_LEFT_R INR_H HP_L
6 INL_H
HP_LEFT 1 2 HP_LEFT_C 1 2 +5VAMP
34 HP_LEFT
1

C561 4.7U_0805_6.3V6K R469 39K_0402_5% VOL_AMP 26 HP_PLUG#

/SD HP_PLUG# 34,38

2
R449 15
CVSS

3
43K_0402_1% 28 R511
BEEP
VSS 16 100K_0402_5%

2
1 12 1 Q44B
2

CP+ C539 R510 2N7002DW-T/R7_SOT363-6

14 2 5

6 1
VOL_AMP C556 CP- GND Q43
PGND 23 1U_0603_10V4Z 100K_0402_5%
1U_0603_10V4Z 25 7 AO3413_SOT23-3

4
BIAS PGND
1

D 2 2 JAL90@
13

1
CGND
1

3
S
1 2 EC_MUTE EC_MUTE 31 1 GND 29 G Q44A
R447 G C537 2 SPDIF_PLUG# 2 2N7002DW-T/R7_SOT363-6
100K_0402_1% C540 S Q41 APA2057A_TSSOP28
S/PDIF Out JACK
3

2N7002_SOT23 2.2U_0805_10V6K D

1
3

2
2
0.01U_0402_16V7K 2
LINE Out/Headphone Out
2

+5VSPDIF D32
PJDLC05_SOT23-3
20mil
Gain= 10dB 2 2
2 C567 C557 2

For ESD Protect

1
330P_0402_50V7K 330P_0402_50V7K
R486 1 1 JHP1
56.2_0603_1% 1
HPOUT_L 1 2 HPOUT_L_1 1 2 HPOUT_L_2 2
For Docking L42 FBM-11-160808-700T_0603 6
HPOUT_R 1 2 HPOUT_R_1 1 2 HPOUT_R_2 3
D_HPOUT_L R485 1 JAL90@ 2 56.2_0603_1% HPOUT_L L41 FBM-11-160808-700T_0603
38 D_HPOUT_L
D_HPOUT_R R476 1 2 56.2_0603_1% HPOUT_R R477 SPDIF_PLUG# 5
38 D_HPOUT_R
JAL90@ 56.2_0603_1%
4
SPDIF 7
34,38 SPDIF
+5VSPDIF 8
1 10
C584
D_LINE_L R457 1 JAL90@ 2 0_0603_5% LINE_L 100P_0402_50V8J 9
38 D_LINE_L
D_LINE_R R460 1 JAL90@ 2 0_0603_5% LINE_R
38 D_LINE_R 2 SINGA_2SJ-E373-T01
CONN@

D_MIC_L R440 1 JAL90@ 2 0_0603_5% MIC1_L

LINE-IN JACK
38 D_MIC_L
D_MIC_R R444 1 JAL90@ 2 0_0603_5% MIC1_R JLINE1
38 D_MIC_R
8
7

R434 1 JAL90@ 2 0_0603_5%

38 AUDIO_GNDA
LINEIN_PLUG# 5
34,38 LINEIN_PLUG#
3 R551 L40 3
4
75_0603_1% FBM-11-160808-700T_0603
34 LINE_R 1 JAL90@ 2 LINE_R_1 1 2 LINE_R_R 3
6
34 LINE_L 1 JAL90@ 2 LINE_L_1 1 2 LINE_L_R 2
L39 1
Volume Control Circuit +3VS
R552
75_0603_1%
FBM-11-160808-700T_06031 1
SINGA_2SJ-E351-S03
+3VS C550 C553 CONN@
220P_0402_50V7K 220P_0402_50V7K
(HDA Jack)
1

C354 JAL90@ 2 2
+3VS 2 1 R265 For ESD
1

100K_0402_5%
R263 R255 0.1U_0402_16V4Z JAL90@ I/O status:
MIC JACK
4

U39 10K_0402_5% 10K_0402_5% a. input/output mount 75 ohm 34,38 MIC_PLUG#

2

JAL90@ JAL90@ +3VS

b. input only mount 1K ohm
GND

U21 1 JMIC1
2

C358 MIC1_VREFO_L MIC1_VREFO_R 8

P

NC

2 1 2 2 4 0.1U_0402_16V4Z 7
A R257 10K_0402_5% A Y
G

1
JAL90@ 2
JAL90@
1 NC7SZ14P5X_NL_SC70-5 U22 R437 R448 5
3

COM 2.2K_0402_5% 2.2K_0402_5%

JAL90@ 1 CD1# VCC 14
2 13 R553 L37 4
D1 CD2# 75_0603_1% FBM-11-160808-700T_0603
3 1 2 3 12

2
B R261 10K_0402_5% CP1 D2
4 SD1# CP2 11 34 MIC1_R 1 JAL90@ 2 MIC1_R_1 1 2 MIC1_R_R 3
JAL90@ 1 1 5 10 6
GND

Q1 SD2#
0.01U_0402_16V7K

0.01U_0402_16V7K

C356 C353 6 09 1 1 JAL90@ 2 MIC1_L_1 1 2 MIC1_L_R 2

Q1# Q2 34 MIC1_L
JAL90@ JAL90@ 7 08 L36 1
XRE094PHDINB1-2-12-E-7016_3P GND Q2# C357 R554 FBM-11-160808-700T_06031 1
5

JAL90@ 2 2 TC74LCX74FT_TSSOP14 75_0603_1% SINGA_2SJ-E351-S01

0.1U_0402_16V4Z
2 C531 C538 CONN@
JAL90@ JAL90@
4 220P_0402_50V7K 220P_0402_50V7K 4
2 2
(HDA Jack)
ENCODER_DIR 31
ENCODER_PULSE 31

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 35 of 50
A B C D E
 H2 H8 H11 H14 H17 H19 H20 H21
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0

@ @ @ @ @ @ @ @
FAN1 Conn

1
+5VS
C10 10U_0805_10V4Z +5VS H23 H24
1 2 H_3P0 H_3P0

1
U2 D2 @ @

1
1 8 1SS355_SOD323-2
VEN GND
2 VIN GND 7
+VCC_FAN1 3 6

2
EN_DFAN1 VO GND D4
31 EN_DFAN1 4 VSET GND 5
1 2 H3 H5 H10 H12 H13 H16 H18 H26
APL5605KI_SOP8 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2
BAS16_SOT23-3
C396
10U_0805_10V4Z @ @ @ @ @ @ @ @

1
1 2
+3VS C399
1000P_0402_50V7K
1 2 H15 H6 H7

1
H_4P2 H_4P2 H_4P2
R299
10K_0402_5%
40mil @ @ @

1
JP12
2

+VCC_FAN1
1
31 FAN_SPEED1 2
3
1
C393 ACES_85205-03001
1000P_0402_50V7K CONN@
H9 H22
2 H_4P1N H_4P6X4P1N

@ @

1
FD1 FD3 FD4 FD2

@ @ @ @

1
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80

COVER LIGHTConn
+5VS
JP14
1 1
1 2 2
C355
470P_0402_50V7K
@ 3
2 G1
4 G2
ACES_88266-02001
CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 36 of 50
 A B C D E

+5VALW TO +5VS +3VALW TO +3V_SB(ICH8M AUX Power) +5VALW

+5VALW +5VS +3VALW +3V

2
U23 U32 R259
8 1 8 1 100K_0402_5%
D S D S
7 D S 2 7 D S 2

2
6 3 1 1 6 3 1 1

1
D S C348 C350 R256 D S C501 C500 R397
1 1 5 D G 4 1 5 D G 4
C360 C359 470_0603_5% C467 470_0603_5% SYSON#
29,30,38 SYSON#
SI4800BDY-T1-E3_SO8 10U_0805_10V4Z SI4800BDY-T1-E3_SO8 10U_0805_10V4Z

6
10U_0805_10V4Z 2 2
1U_0603_10V4Z 2 2
1U_0603_10V4Z

3 1
1 2 2
10U_0805_10V4Z 2
10U_0805_10V4Z 1
Q31A

3
SYSON 2
30,31,43,44 SYSON
Q39B 2N7002DW-T/R7_SOT363-6

1
Q30B 2N7002DW-T/R7_SOT363-6 5 SBPWR_EN#

1
+VSB 2 1 5VS_GATE 2N7002DW-T/R7_SOT363-6 5 SUSP +VSB 2 1 3V_GATE R260
R258 R394 100K_0402_5%

4
6
200K_0402_5% 1 200K_0402_5% 1

4
6
C349 C493

2
Q39A
Q30A 0.1U_0603_25V7K SBPWR_EN# 2 0.1U_0603_25V7K
SUSP 2
2N7002DW-T/R7_SOT363-6 2 +5VALW
2
2N7002DW-T/R7_SOT363-6

1
1

2
R264
100K_0402_5%

1
SUSP
+3VALW TO +3VS 33,45 SUSP

3
+3VALW +3VS

U20 Q31B
8 D S 1 30,31,33,45 SUSP# 5
7 2 2N7002DW-T/R7_SOT363-6
D S

2
6 3 1 1

4
D S

1
1 1 5 4 C336 C337 R239
C339 C341 D G 470_0603_5% R262
SI4800BDY-T1-E3_SO8 10U_0805_10V4Z 10K_0402_5%
10U_0805_10V4Z 2 2
1U_0603_10V4Z
1 1
2 2 2
10U_0805_10V4Z 2

2
D
2 SUSP
G
S Q27
3

5VS_GATE 2N7002_SOT23

+5VALW

2
+1.8V to +1.8VS +1.5V to +1.5VS R182
100K_0402_5%
+1.8V +1.8VS +1.5V +1.5VS

1
U11 U12
8 D S 1 8 D S 1
7 2 1 1 7 2 1 1 24 SBPWR_EN# SBPWR_EN#
D S D S
2

2
6 3 C274 C273 6 3 C290 C279
D S R192 D S R193
1 1 5 D G 4 1 1 5 D G 4
C272 C266 10U_0805_10V4Z 470_0603_5% C285 C293 10U_0805_10V4Z 470_0603_5%

1
SI4856ADY_SO8 PM@ 2 2
1U_0603_10V4Z PM@ SI4800BDY-T1-E3_SO8 2 2
1U_0603_10V4Z D
10U_0805_10V4Z JAL90PM@ PM@ 10U_0805_10V4Z 31,44 SBPWR_EN 2
1

1
PM@ 2 2
10U_0805_10V4Z 2 2
10U_0805_10V4Z G
PM@ SI4856/AO4430 Q11 S

3
3

1
2N7002_SOT23
R181
Q14B Q19B 100K_0402_5%
+VSB 2 1 1.8VS_GATE 2N7002DW-T/R7_SOT363-6 5 SUSP +VSB 2 1 1.5VS_GATE 2N7002DW-T/R7_SOT363-6 5 SUSP
R191 PM@ R205

2
510K_0402_5% 1 510K_0402_5% 1
4

4
3 PM@ C278 C295 3
6

6
PM@
0.1U_0603_25V7K 0.1U_0603_25V7K
Q14A 2 Q19A 2
SUSP 2 2N7002DW-T/R7_SOT363-6 SUSP 2 2N7002DW-T/R7_SOT363-6
PM@
1

+1.5VS +2.5VS +1.05VS +0.9VS +1.8V +1.5V

2

R190 R288 R33 R139 R189 R208

470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5%
PM@ @ @
1

1
1

D D D D D D
2 SUSP 2 SUSP 2 SUSP 2 SUSP 2 SYSON# 2 SYSON#
G G G G G G
S Q13 S Q36 S Q1 S Q7 S Q17 S Q20
3

2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23

PM@ @ @

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 37 of 50
A B C D E
 5 4 3 2 1

+3VS +5VS

1
R533 R547
+3VS +5VS 10K_0402_5% 10K_0402_5%
+3VALW JAL90@ @
R546

2
1

1
D 10K_0402_5% D
EC_DOCKIN#_S0 19,20
R284 @

3
10K_0402_5%
R282 JAL90@ Q35B
JAL90@ 2N7002DW-T/R7_SOT363-6

2
10K_0402_5% 5 JAL90@

4
Q35A
2N7002DW-T/R7_SOT363-6
28,31 EC_DOCKIN# 2 JAL90@
EC_DOCKIN 20
1

1
C605
@
0.1U_0402_16V4Z
2

JDOCK1
C C
DOCK_B+ 67 ACER DOCK 65
19V_5A GND
+5VALW 68 5V_USB_3A GND 66
+3VALW
Normal
34,35 LINEIN_PLUG# 33 LIN_IN_DT# GND 1
35 D_LINE_L 34 LIN_IN_L DVI_CLK 2 D_DVI_TXC+ 20
1

46 P3 P1 1
35 D_LINE_R 35 LIN_IN_R DVI_CLK# 3 D_DVI_TXC- 20
R283 47 (67) (65) 2
34,35 MIC_PLUG# 36 MIC_DT# GND 4
48 3
10K_0402_5% 35 D_MIC_L 37 MIC_L DVI_TX0 5 D_DVI_TXD0+ 20
49 33 20 4
35 D_MIC_R 38 MIC_R DVI_TX0# 6 D_DVI_TXD0- 20
AUDIO_GNDA 50 34 21 5
35 AUDIO_GNDA 39 7
2

DOCKIN# GNDA 51 35 22 6 GND

31 DOCKIN# 40 DOCK_DT1# DVI_TX1 8 D_DVI_TXD1+ 20
52 36 23 7
1 34,35 SPDIF 41 SPDIF 24 DVI_TX1# 9 D_DVI_TXD1- 20
C374 53 37 8
42 GND GND 10
D_LAN_MIDI2+ 54 38 25 9
28 D_LAN_MIDI2+ 43 LAN_2 DVI_TX2 11 D_DVI_TXD2+ 20
0.1U_0402_16V4Z D_LAN_MIDI2- 55 39 26 10
28 D_LAN_MIDI2- 44 LAN_2# DVI_TX2# 12 D_DVI_TXD2- 20
2 56 40 27 11
45 GND 28 12 GND 13
57 41 D_CRT_R_R R566 1 JAL90@ 2 0_0603_5%
VGA_R 14 D_CRT_R 19
58 42 29 13
59 43 30 14 GND 15
46 16 D_CRT_R_G R567 1 JAL90@ 2 0_0603_5%
GND 60 44 31 15 VGA_G D_CRT_G 19
USB20_P3 47 17
23 USB20_P3 USB 61 45 32 16 GND
USB20_N3 48 18 D_CRT_R_B R568 1 JAL90@ 2 0_0603_5%
23 USB20_N3 USB# 62 17 VGA_B D_CRT_B 19
29,30,37 SYSON# 49 USB_EN# GND 19
63 P4 P2 18
50 RESERVED 64 (68) (66) 19
19,23 CRT_DET# 51 VGA_DT#
52 20 DOCK_DT2# R273 1 JAL90@ 2 1K_0402_5%
LAN_PWR DOCK_DT2#
28 D_LAN_ACTIVITY# 53 LAN_ACT HP_L 21 D_HPOUT_L 35
28 D_LAN_LINK# 54 LAN_LINK HP_R 22 D_HPOUT_R 35
B B
55 GND HP_DT# 23 HP_PLUG# 34,35
28 D_LAN_MIDI0+ D_LAN_MIDI0+ 56 24 AUDIO_GNDA
D_LAN_MIDI0- LAN_0 GNDA
28 D_LAN_MIDI0- 57 LAN_0# DVI_DT 25 D_DVI_DET 20
58 GND DVI_DCDT 26 D_DVI_SDATA 20
28 D_LAN_MIDI1+ D_LAN_MIDI1+ 59 27 D_DVI_SCLK 20
D_LAN_MIDI1- LAN_1 DVI_DDCCK
28 D_LAN_MIDI1- 60 LAN_1# VGA_VS 28 D_CRT_VSYNC 19
61 GND VGA_HS 29 D_CRT_HSYNC 19
28 D_LAN_MIDI3+ D_LAN_MIDI3+ 62 30
LAN_3 VGA_DDCCK D_DDC_CLK 19
28 D_LAN_MIDI3- D_LAN_MIDI3- 63 31
LAN_3# VGA_DDCDT D_DDC_DATA 19
64 GND 5V_S0 32 +5VS

72 GND GND 69
73 GND ACER DVR1027 Rev: 0.5 GND 70
74 GND GND 71
D_LINE_L C607 1 2 @ 220P_0402_50V7K
JAE_SP07-10207-22
D_LINE_R C608 1 2 @ 220P_0402_50V7K CONN@

D_MIC_L C615 1 2 @ 220P_0402_50V7K

D_MIC_R C616 1 2 @ 220P_0402_50V7K

D_HPOUT_L C617 1 2 @ 220P_0402_50V7K

D_HPOUT_R C618 1 2 @ 220P_0402_50V7K

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 38 of 50
5 4 3 2 1
 A B C D

Place at HW side VIN

PD11
PDS1040-13_POWERDI5-3
SP02000EF00 2
1
PJP1 1 1

3 PR1
6 DOCK_B+ 1M_0402_1%
G2
1 2
5 PL1 VIN VIN
G1 SMB3025500YA_2P PJ1 VS
DC_IN_S1 1 2DC_IN_S2 2 1
2 1

1
4 4
JUMP_43X79 PR2 PR3
10K_0402_5% 84.5K_0402_1%
3 PR5
3

8
PC2 PR4 PD2 22K_0402_5%

2
PC3 PC4 100P_0402_50V8J PC1 10K_0402_5% 1SS355_SOD323-2 3 1 2

P
1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K +
2 1 2 2 1 1

2
2 23,31,32,42 ACIN 0

20K_0402_1%
- 2

1
G

PR6
PU1A

1
PC6
0.1U_0603_25V7K
1 LM358DT_SO8 PC5

4
1 PR7 PD3 1000P_0402_50V7K

2
10K_0402_5% GLZ4.3B_LL34-2

2
E&T_4510-E04C-01R

2
<BOM Structure>
PR8
10K_0402_5%
1 2
RTCVREF

2 2

Vin Dectector
Min. Typ Max.
- PBJ1 + H-->L 16.976V 17.525V 17.728V
2 1 +RTCBATT L-->H 17.430V 17.901V 18.384V
+RTCBATT

ML1220T13RE
45@

VIN 2
PJ2
1 2
PJ3
1
+3VALWP 2 1 +3VALW +1.5VP 2 1 +1.5V
JUMP_43X118 JUMP_43X118
2

PD4
LL4148_LL34-2

PD5 PJ4 PJ5

1

LL4148_LL34-2 2 1 2 1
+5VALWP 2 1 +5VALW +0.9VSP 2 1 +0.9VS
BATT+ 2 1
1

3 3

JUMP_43X118 JUMP_43X79
PR9 PR10
PQ1 68_1206_5% 68_1206_5%
TP0610K-T1-E3_SOT23-3
PR11
PJ6
2

200_0603_5% PJ7
CHGRTCP 1 2 N1 3 1 2 1 +1.8VP 2 1 +1.8V
VS +VSBP 2 1 +VSB 2 1
JUMP_43X39 JUMP_43X118
1

PR12 PC8
100K_0402_1% PC7 0.1U_0603_25V7K
0.22U_1206_25V7K
2

PR13 PJ8 PJ17

2

22K_0402_1% 2 1 +1.8VP 2 1 +1.8V

+1.05VSP 2 1 +1.05VS 2 1
1 2
32,33 51ON# JUMP_43X118 JUMP_43X118

PJ16 PJ9
RTCVREF +1.05VSP 2 2 1 1 +1.05VS +2.5VSP 2 2 1 1 +2.5VS
1

PR14 JUMP_43X118 JUMP_43X118

PU2 200_0603_5%
PR15 PR16 G920AT24U_SOT89-3
560_0603_5% 560_0603_5% 3.3V
2

1 2 1 2 3 2 N2
OUT IN
+CHGRTC
1

GND PC10
4
PC9 1U_0805_25V4Z 4

10U_0805_10V4Z 1
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 39 of 50
A B C D
 A B C D

PH1 under CPU botten side :

CPU thermal protection at 96 degree C
Recovery at 60 degree C
VL
VL
VL
VMB

2
PL2 PR17

1
1 1

PJP2 SMB3025500YA_2P 47K_0402_1%

1 1 BATT_S1 1 2 BATT+ PH1 PC11
MAINPWON 22,41
2 100K_0603_1%_TH11-4H104FT 0.1U_0603_25V7K PR18

1
2 47K_0402_1%
3 3

1
4 EC_SMCA 1 2

2
4 EC_SMDA PC12 PC13 PR19 PQ2
5 5

8
6 1000P_0402_50V7K 0.01U_0402_25V7K 13.3K_0402_1% DTC115EUA_SC70-3

2
6 PD6
7 1 2 3

P
7 +
O 1 2 1 2
SUYIN_250133MR007G115ZL TM_REF1 2 -

G
PU3A LL4148_LL34-2
LM393DG_SO8

3
2

0.22U_0603_16V7K
PR20 PR21

13.3K_0402_1%
100_0402_1% 100_0402_1%

1
PC14
PR23

1000P_0402_50V7K
PR22
100K_0402_1%
1

2 1 VL

1
PR24

PC15
6.49K_0402_1%

2
2 1 +3VALWP

1
1

PR25
PR26 100K_0402_1%
1K_0402_1%

2
2

2 2

BATT_TEMP 31

EC_SMB_CK1 17,31 PH2 near main Battery CONN :

BAT. thermal protection at 79 degree C
EC_SMB_DA1 17,31
Recovery at 47 degree C
VL

2
@ PR27
@PR27
VL 47K_0402_1%
@PR28
@ PR28
47K_0402_1%

1
1 2

1
PQ3
TP0610K-T1-E3_SOT23-3
@PH2
@ PH2
100K_0603_1%_TH11-4H104FT VL

B++ 3 1 +VSBP

2
0.22U_1206_25V7K

0.1U_0603_25V7K

@PR30
@ PR30
1

8
9.09K_0402_1% @PD7
@ PD7
1

1
PC16

PC17

PR29 1 2 5 LL4148_LL34-2

P
100K_0402_1% +
O 7 2 1
@ @ TM_REF1 6
2

G
3 3

PR31 PU3B
2

1
VL 22K_0402_1% LM393DG_SO8

4
1 2 @ PC18
@PC18 @ PR32
@PR32
0.22U_0603_16V7K 22.1K_0402_1%

2
2

PR33
100K_0402_1%

PR34
1

0_0402_5% D
1 2 2 PQ4
41 SPOK G 2N7002W-T/R7_SOT323-3
0.1U_0402_16V7K

S
3
1

PC19

@
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 40 of 50
A B C D
 5 4 3 2 1

ISL6237_B+
ISL6237_B+

PL12 B++ PL13 PR35

FBMA-L11-322513-151LMA50T_1210 FBMA-L11-322513-151LMA50T_1210 0_0805_5%
1 2 1 2 1 2
D
B+ D
470P_0402_50V7K

470P_0402_50V7K

470P_0402_50V7K

470P_0402_50V7K

2200P_0402_50V7K

2200P_0402_50V7K
4.7U_1206_25V6K

4.7U_1206_25V6K
1

1
PC145

PC146

PC147

PC148

4.7U_1206_25V6K

4.7U_1206_25V6K
1

5
6
7
8
PC20

PC21

PC22
2

8
7
6
5

1
PC25
VL

PC23

PC24
1U_0603_10V6K
2

2
PQ6

2
2
PQ5 PC26 AO4466_SO8

2
AO4466_SO8 0.1U_0603_25V7K

4.7U_0805_6.3V6K
4

1
PC27
4

PC28
1
+5VALWP

3
2
1
PL4

1
2
3
PL3 8.2UH_PCMB063T-8R2MS_4.5A_20%

7
8.2UH_PCMB063T-8R2MS_4.5A_20% PC29 2 1
1 2 1U_0603_10V6K

LDO
VIN

VCC
+3VALWP 33 19 1 2
TP PVCC

5
6
7
8

1
4.7_1206_5%
1

8
7
6
5

PR39
DH3 26 15 DH5
PR36 PR37 UGATE2 UGATE1 PR40 2.2_0603_5% PQ8
4.7_1206_5% PQ7 2 1 BST3A 24 17 BST5A 2 1 AO4712_SO8
BOOT2 BOOT1
2

1 AO4712_SO8 2.2_0603_5%

2
2

63.4K_0402_1%
PR38 PC32 4

2
PC30 + 0_0402_5% 4 PC31 0.1U_0603_25V7K

2
680P_0402_50V7K
330U_D3L_6.3VM_R25M 0.1U_0603_25V7K

1
1

PR41
LX3 25 16 LX5 1
1

2 PHASE2 PHASE1

PC34
PC33

3
2
1

2
C 680P_0402_50V7K + PC35 C

1
2
3
DL3 23 18 DL5 150U_D2E_6.3VM_R18

1
LGATE2 LGATE1
2
2

10K_0402_1%
PGND 22

2
FB3 30 OUT2

PR43
@ PR42
10K_0402_1% 10
OUT1
VL 32
1

REFIN2

1
11 FB5
2VREF_ISL6237 FB1

1 2 1 REF
PC36 0.22U_0603_10V7K
BYP 9
8 LDOREFIN
+3.3VALWP Ipeak=8.444A ; Imax=5.91A @ PR44 0_0402_5%
29 2 1 VL
Choke DCRmax=60m ohm, DCRtyp=54m ohm SKIP
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) PR45 0_0402_5%
1 2
Vlimit=(5E-06 * 330K)/10=165mV 20 28
PD8 PR46 NC POK2
Ilimit=165mV/18m ~ 165mV/15m
GLZ5.1B_LL34-2 100K_0402_1%
=9.167A ~ 11A 1 2 1 2 4 13 SPOK 40
Iocp=Ilimit+Delta I/2 VS EN_LDO POK1 PR48
2
200K_0402_5%

330K_0402_1%
=10.134A ~ 11.967A
2

B B
PR47

14 12 ILM1 2 1
EN1 ILIM1
Delta I=1.934A (Freq=300KHz) PC37
0.22U_0603_25V7K
1

27 31 ILIM2 2 1

GND
TON
1

EN2 ILIM2
1

NC
2

0_0402_5%
PD12 PR49
1SS355_SOD323-2 VL @ PR50
2
PU4 330K_0402_1%

21
PR51

0_0402_5% ISL6237IRZ-T_QFN32_5X5
2
2

PR52
1

1
1U_0603_10V6K
806K_0603_1%
2VREF_ISL6237 1

PR54 @ PR55 PR53

+5VALWP Ipeak=8.444A ; Imax=5.91A
1

2
PC143

0_0402_5% 47K_0402_5% 0_0402_5%

2 1 1 2
2VREF_ISL6237 2
Choke DCRmax=60m ohm, DCRtyp=54m ohm
1

Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)

0.047U_0603_16V7K

22,40 MAINPWON
Vlimit=(5E-06 * 330K)/10=165mV
1

PC38

Ilimit=165mV/18m ~ 165mV/15m
2

=9.167A ~ 11A
1

@ PC39 Iocp=Ilimit+Delta I/2

3

0.047U_0402_16V7K
2

=10.147A ~ 11.980A
Delta I=1.96A (Freq=400KHz)
2 PQ35
A A
TP0610K-T1-E3_SOT23-3
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 41 of 50
5 4 3 2 1
 A B C D

B+
PQ9 PQ10
SI4835BDY-T1-E3_SO8 SI4835BDY-T1-E3_SO8 PR56
VIN 8 3 3 8 0.015_2512_1%
7 2 2 7 PJ11
6 1 1 6 1 4 2 1 CHG_B+
2 1

1
5 5

2
2200P_0402_25V7K
4.7U_1206_25V6K

4.7U_1206_25V6K
2 3 JUMP_43X118 PR57
PR58 CHGEN# PC40 100K_0402_1%

2
0.01U_0402_25V7K
3.3_1210_5% 0.01U_0402_25V7K

1
100K_0402_1%

PC42

PC43

PC44

2
1
PC46 PC48

1
2

5
6
7
8

1
2
3
1 1

PC45

PR59
0.1U_0402_16V7K PU5 0.1U_0805_25V7K
1 2 1 28 PVCC 1 2 PQ12
CHGEN PVCC

1
SI4835BDY-T1-E3_SO8

1
PR174 PR61 /BATDRV 4

2
3.3_1210_5% PC47 @PC49
@PC49 2.2_0603_5% PQ11
0.1U_0603_25V7K 0.1U_0603_25V7K 27 BTST 1 2 4 AO4466_SO8

2
BTST

2
2
PR60
340K_0402_1% ACN 2 26 DH_CHG
ACN HIDRV
1

ACP 3

3
2
1

5
6
7
8
PC50 ACP PR62

1
2.2U_0805_25V6K ACDRV 4 25 LX_CHG PL5 0.02_2512_1%
2

ACDET ACDRV PH PD10 10UH_PCMB104T-100MS_6A_20%

5 ACDET
2 1 1 2 1 2 1 4
BATT+

10U_1206_25V6M
Place close to back to back MOS

10U_1206_25V6M
LL4148_LL34-2 PC51

REGN
2 3

2
0.1U_0603_25V7K PR64

5
6
7
8

PC53
24751_VREF PR63 4.7_1206_5%

PC52
CELLS GND 3 Cell 54.9K_0402_1% ACSET 6 ACSET
24

2
REGN
VREF 4 Cell
1
2

1
PC54 PQ13
@ PR65
@PR65 1U_0603_10V6K 4 AO4466_SO8

1
100K_0402_1% PR66 PC56 PC55

2
2

0_0402_5% 0.47U_0603_16V7K 680P_0402_50V7K

1 2 1 2 7
1

2
PR67 ACOP DL_CHG
23

3
2
1
340K_0402_1% LODRV
CELLS
1

PGND 22
@ PQ14 OVPSET 8 PC57
OVPSET
1

2 D 2N7002W-T/R7_SOT323-3 0.1U_0402_16V7K 2

2 3S/4S# 31 1 2
G 9 21 ACOFF 31
AGND LEARN
2

S
3

1
PR68
54.9K_0402_1% PC58 @PC59
@PC59
24751_VREF CELLS 0.1U_0603_25V7K 0.1U_0603_25V7K
Cells selector 20

2
CELLS
1

24751_VREF 10
PQ15 VREF
3

1
SI2301BDS-T1-E3_SOT23-3 PC60
1U_0603_10V6K
PR69 19 SE_CHG+

2
SRP
1

100K_0402_1%
CP Point Setting 1 2PQ15_GATE
2 PR70 11 VDAC SRN 18 SE_CHG-
100K_0402_1%
CP point=Iadapter*85% BAT 17
1

1
90W adapter PC62 VADJ 12
0.1U_0603_25V7K VADJ PC61
Vacset=3.3*(100K/(64.9K+100K))=2.001V
2

ACSET 0.1U_0603_25V7K

2
CP Point=(Vacset/Vvdac)*(0.1/PR56)=4.04A TP 29 Icharge Setting
ACGOOD# 13 ACGOOD ICHG setting PR71 For 2200mA, Icharge=0.8C=0.8*2*2.2=3.52A
65W adapter R=(100K*100K)/(100K+100K)=50K 17.4K_0402_1% For 2400mA, Icharge=0.8C=0.8*2.4*2=3.84A
VMB 16 SRSET 2 1 Icharge=(Vsrset/Vdac)*(0.1/PR62)
Vacset=3.3*(50K/(50K+64.9K))=1.436V /BATDRV 14
SRSET IREF 31 IREF=((100k/(100K+17.4K))/3.3)*(0.1/0.02)=Icharge
BATDRV

1
PR72
IREF=0.7748*Icharge

1
CP POINT=(1.436V/3.3V)*(0.1/0.015)=2.901A 10_0603_5% PR73
1

15 1 2 100K_0402_1% @PC63
@PC63
IADAPT 0.01U_0402_25V7K

2
VS PR74 BQ24751ARHDR_QFN28_5X5 24751_VREF
Input OVP : 22.3V

2
3 3

LI-4S :18.0V----BATT-OVP=2.001V 340K_0402_1%

1
Input UVP : 17.26V
2

2
0.01U_0402_25V7K

BATT-OVP=0.1112*VMB PC64
Fsw : 300KHz 100P_0402_50V8J @ PR75
@PR75

2
LI-3S :13.5V----BATT-OVP=1.5012V 100K_0402_1%
1

PC65

24751_VREF 24751_VREF ADP_I 31 @PR176

@ PR176
1

BATT-OVP=0.1112*VMB 0_0402_5% 24751_VREF

1
200K_0402_1%
PR76 1 2
2

1
100K_0402_1%

Per cell=3.5V 499K_0402_1% ACIN 23,31,32,39

1

1
PR180

PQ15_GATE

1
D
PR179

PR78
2
8

PR77 PU1B 887K_0402_1% ACGOOD# 2 @ PQ16

1
10K_0402_1% LM358DT_SO8 D PQ17 G 2N7002W-T/R7_SOT323-3
5
P

+ PQ36 SI2301BDS-T1-E3_SOT23-3 PR80

1 2 7 0 2 S
2

3
31 BATT_OVP 6 PC163 G SSM3K7002F_SC59-3 0_0402_5%
-
1
G

S
0.1U_0402_16V7K REGN VADJ

D
S 3 1 1 2
3
1

24751_VREF
0.01U_0402_25V7K

ACOFF 1 2 2
4

PR79 G

1
PC66

105K_0402_1%

G
S
3

2
1

2
340K_0402_1%

221K_0402_1%
PQ37 PR82
2

1
PR181

SSM3K7002F_SC59-3 100K_0402_1% PC144 PR81

2

PR84
@PR177
@ PR177 1000P_0402_50V7K 100K_0402_1%

2
PR83 4.3K_0402_5%

2
64.9K_0402_1%
2

1
24751_VREF 1 2 ACSET CHGEN#

2
1
D
1

1
PQ19 D
2
31 CALIBRATE# G 2N7002W-T/R7_SOT323-3 2 PQ18
PR85
31 FSTCHG 2N7002W-T/R7_SOT323-3
S G

3
100K_0402_1% S

3
1

4 4
2

PR86
100K_0402_1%
1

D
31 65W/90W# 2 Charger ADJ Calibrate# PR78 PR84
2

G
PQ20 S
3

2N7002W-T/R7_SOT323-3 4.0V L @ @ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
4.1V L 887K 221K SCHEMATIC,LA-4201P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
CP setting 4.2V H @ @
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 42 of 50
A B C D
 A B C D

PC68

1
PC67 1U_0402_6.3V6K
1U_0402_6.3V6K

2
PR87 PR88
2.2_0603_1% 2.2_0603_1%
1
+5VALW 2 1 1 2 +5VALW 1

1
PC70 PC69
0.1U_0603_25V7K 0.1U_0603_25V7K

2
PJ12
JUMP_43X118 PR89 PR90
2 2 10_0603_1% 10_0603_1%
1 1
B+ ISL6228_B+ ISL6228_B+ 2 1 2 1 ISL6228_B+

22K_0402_1%

2
1000P_0402_50V7K
2
PR92

PR91
18.2K_0402_1%

1
PC72 PR93 PC71

PC73
1000P_0402_50V7K 3.3K_0402_5% PR94 1000P_0402_50V7K

1
2 1 1 2 57.6K_0402_1%

2
1
PR95

1
45.3K_0402_1%
FB_1.05V 2 1 FB_1.05V-1 29

PGOOD1

FSET1

VIN1

VCC1

VCC2

VIN2

FSET2
GND_T
PR98 PC74

2
PR96 3.3K_0402_5% 1000P_0402_50V7K
11.8K_0402_1% 8 28 PR97 2 1 1 2
2
6228_1.05VO1 FB1 PGOOD2 22.6K_0402_1% 2
1 2

PR99

1
45.3K_0402_1%
ISL6228_B+ 9 27 FB_1.8V-1 1 2 FB_1.8V
VO1 FB2
4.7U_1206_25V6K

4.7U_1206_25V6K

PR100
1

1
PC76

PC77

10K_0402_1%
8
7
6
5

PC75 OCSET_1.05V 10 26 6228_1.8VO2 1 2

0.015U_0402_16V7K OCSET1 VO2
2

1 2 PQ21
AO4466_SO8
Vref=0.6V
2

PR101 4 1.05V_EN 11 25 OCSET_1.8V

11.8K_0402_1% EN1 PU6 OCSET2
PR103
PL6 ISL6228HRTZ-T_QFN28_4X4 0_0402_5% SYSON 30,31,37,44 ISL6228_B+
+1.05VSP 1UH_MSCDRI-104R-1R0N-F_11A_30% 1 2
1

1
2
3

1 2 LX_1.05V 12 24
PHASE1 EN2 @ PC78
@PC78
1

4.7U_1206_25V6K

4.7U_1206_25V6K
0.01U_0402_25V7K PC82

5
6
7
8

1
PC81

PC79
1 2 0.022U_0402_16V7K
8
7
6
5

1 PR104 1 2
4.7_1206_5% PQ22 UG_1.05V 13 23
D
D
D
D

2
PC80 + FDS6670AS_NL_SO8 UGATE1 PHASE2
2

2
330U_D2E_2.5VM PR105
PR106 4 PQ23 10K_0402_1%
2 2.2_0603_5% AO4466_SO8
G 4
1

PC83 2 1 2 1BST_1.05V
14 BOOT1 UGATE2 22 UG_1.8V
680P_0402_50V7K PL7

1
S
S
S

LGATE1

LGATE2
PC84 1UH_MSCDRI-104R-1R0N-F_11A_30%
PGND1

PGND2

BOOT2
PVCC1

PVCC2
2

3
2
1
3 3

0.1U_0402_16V7K LX_1.8V 1 2
1
2
3

+1.8VP

1
5
6
7
8
PR108

FDS6670AS_NL_SO8
DCR 6m ohm(max) Cout ESR=15m ohm 4.7_1206_5% 1

D
D
D
D
15

16

17

18

19

20

21
<BOM Structure>

PQ24
+ PC88
+1.05VSP OCP Seting is same as ICL50

2
PR109 PC87 330U_4V_M
Vo=Vref*((PR80+PR82)/PR80) 2.2_0603_5% 0.1U_0402_16V7K 4 G

1
BST_1.8V 1 PC89 2
Ipeak=14.02A, Imax=9.81A +5VALW 2 1 2
680P_0402_50V7K
Iocp=14.02*1.2=16.824A +5VALW
2

S
S
S

2
Csen=L/(Rocset*DCR) PC85 PC86

3
2
1
1U_0402_6.3V6K 1U_0402_6.3V6K
0.015U=1U/(Rocset*6m) Rocset=11.111K~11.8K
1

Iocp=(Rocset*10uA)/DCR
Iocp=(11K*10uA)/(6m ohm*1.3) =15.1A DCR 6m ohm(max) Cout ESR=15m ohm
LG_1.05V LG_1.8V
Vo=0.6*((PR87+PR83)/PR83)=1.8V
1.8VP Ipeak=11.93A, Imax=8.351A
Csen=L/(Rocset*DCR)=1uF/(Rocset*6m ohm)=0.022uF
=>Rocset=7.575K, Choose 10K because of thermal factor
PR110 Iocp=(Rocset*10uA)/DCR=(10K*10uA)/(0.006*1.3)=12.82A
0_0402_5%
2 1 1.05V_EN
33 VS_ON
1

@ PC90
@PC90
0.01U_0402_25V7K
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 43 of 50
A B C D
 5 4 3 2 1

D
@PR178
@ PR178 D
0_0402_5%
1 2
31,37 SBPWR_EN
PJ13

4.7U_1206_25V6K
JUMP_43X118

PR111 8
PQ26
1
51117_B+ 2 2 1 1 B+
G2 D2

PC91
143K_0402_1% 7 2
PR112 S2/D1 D2
1 2 6 S2/D1 G1 3
0_0402_5% 5 4

2
S2/D1 S1
1 2
30,31,37,43 SYSON AO4932_SO8

PR113 PC93 PL8

0_0603_1% 0.1U_0603_25V7K 2.2UH_MSCDRI-74A-2R2M-E_6.5A_20%

15

14
1

1
@PC94
@PC94
PU7 BST_1..5V 1 2BST_1..5V-1 1 2 1 2 +1.5VP

EN_PSV

TP

VBST
0.1U_0402_16V7K

2
2 13 DH_1..5V
TON DRVH
3 12 LX_1..5V 1
VOUT LL
VFB=0.75V + PC95
4 V5FILT TRIP 11 +5VALW 330U_D2E_2.5VM
5 VFB V5DRV 10
2
6 9 DL_1.5V DL_1.5V
PGOOD DRVL

PGND
PR114

GND

1
17.8K_0402_1%
0_0603_1%

PR115
1 2 @ PC96
@PC96 PC97
C +5VALW 47P_0402_50V8J TPS51117RGYR_QFN14_3.5x3.5 4.7U_0805_10V6K C

2
1 2
1

2
PC98
1U_0603_10V6K
2

PR116
10.5K_0402_1%
1 2
1

PR117
10K_0402_1%
2

VFB=0.75V
Vo=VFB*(1+PR87/PR88)=0.75*(1+10K/10K)=1.5V
Ton=19*e-12*143000(((2/3)*Vo+100mV)/19)+50ns
=2.645e-7 us
=>Vo/Vin=D=Ton/Ts =>Ts=3.35us
Fsw=298KHz

B Cout ESR=15m ohm B

Ipeak=4.71A, Imax=3.297A, Iocp=5.652A

Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=2.107A
=>1/2DeltaI=1.053A
Vtrip=Rtrip*10uA=17.8K*10uA=0.178V
Iocpmin=Vtrip/Rdsonmax*1.2+1.053A
=0.178/(0.027*1.2)+1.053=5.493A+1.053A=6.546A
Iocpmax=(0.178/(0.021*1.1))+1.053A=7.705A+1.053A
=8.758A
Iocp=6.546A~8.758A

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 44 of 50
5 4 3 2 1
 5 4 3 2 1

D D

+1.8V

+3VALW

1
PJ14

1
JUMP_43X79
+5VALW
2

1
2 PU8
1 6 +3VALW

1
VIN VCNTL PJ15
C JUMP_43X79 C
2 GND NC 5
2

2
PM@PC105

1
PC99 3 7 PC100 1U_0603_6.3V6M

2
4.7U_0805_6.3V6K PR118 REFEN NC 1U_0603_6.3V6M
1

2
1K_0402_1% 4 8
VOUT NC

6
2 GND 9

1
5 PM@PC102

VCNTL
VIN 4.7U_0805_6.3V6K
RT9173DPSP_SO8 7 POK
4

2
VOUT

0.1U_0402_16V7K
PR119 PQ27
+0.9VSP
1

1
0_0402_5% 2N7002W-T/R7_SOT323-3 D PM@PR124 3
VOUT
+2.5VSP
PC101
33,37 SUSP 1 2 2 PR120 0_0402_5%

1
G 1K_0402_1% 2 30,31,33,37 SUSP# 1 2 8 EN FB 2
1

1
S PC104

GND
3

PC103 10U_0805_6.3V6M 9 PM@PR122 PM@PC107

2

2
VIN

1
0.1U_0402_16V7K 2.15K_0402_1% 0.01U_0402_25V7K
2

1
PM@PC116 PM@PC106

2
0.1U_0402_16V7K PM@PU11 22U_0805_6.3V6M

2
APL5915KAI-TRL_SO8

2
1
PM@PR123
1K_0402_1%

2
B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 45 of 50
5 4 3 2 1
 5 4 3 2 1

+5VS

B+
CPU_VID6 5 CPU_B+

2
CPU_VID5 5 PR125 PL9
1_0603_5% FBMA-L18-453215-900LMA90T_1812
CPU_VID4 5 2 1
31,33 VR_ON

2200P_0402_50V7K
10U_1206_25V6M

10U_1206_25V6M
CPU_VID3 5 1
PR126

1
PC112

PC113
499_0402_1% + PC115
D CPU_VID2 5 D

PC114
8,23 PM_DPRSLPVR 1 2 PC110 PC149 PC150 220U_25V_M
CPU_VID1 5 PC109 2.2U_0603_6.3V6K 470P_0402_50V7K 470P_0402_50V7K

2
5
PR127 0_0402_5% 0.022U_0402_16V7K 2

2
5,8,22 H_DPRSTP# 1 2 CPU_VID0 5
PR128 0_0402_5%
1 2 PQ29

1
PR130 0_0402_5%

PR131 0_0402_5%

PR132 0_0402_5%

PR133 0_0402_5%
16 CLK_ENABLE#

PR129 0_0402_5%

PR135 0_0402_5%

PR136 0_0402_5%

PR137 0_0402_5%
4 SI7686DP-T1-E3_SO8
PR134 0_0402_5%
+3VS 1 2
+3VS

3
2
1
1
1U_0603_6.3V6M
PR138 PC119 PL10

PC118
1.91K_0402_1%
2.2_0603_5% 0.22U_0603_10V7K 0.36UH_FDU1040D-R36M_26A_20%
+CPU_CORE
1
BOOT_CPU1 1 2 1 2 2 1

2
2

PR140

5
6
7
8

1
10K_0402_1%
6.8_1206_5%

3.65K_0805_1%
PR139

5
6
7
8

1
PR142

PR143

PR144
499_0402_1%

49

48

47

46

45

44

43

42

41

40

39

38

37
UGATE_CPU1 PR145
2

1_0402_5%

3V3

CLK_EN#

DPRSTP#

VID6

VID5

VID4

VID3

VID2

VID1

VID0
GND

DPRSLPVR

VR_ON
1

@ PR146
@PR146

1 2

2
680P_0402_50V7K
1 36 4 PQ31 0_0603_5%

2
8,16,23 VGATE PGOOD BOOT1 AO4456_SO8
4 1 2

PC120
5 PSI# PR147
1 20_0402_5% 2 35 VSUM PC121
PSI# UGATE1 PQ30 1 2

2
31 PGD_IN 1@
@PR148
PR148 2 3 34 PHASE_CPU1 AO4456_SO8 VCC_PRM

3
2
1
PMON PHASE1 ISEN1

3
2
1
0_0402_5% 1 PR149
2 147K_0402_1% 4 33 0.22U_0603_10V7K
RBIAS PGND1
VR_TT# 5 32 LGATE_CPU1 CPU_B+
VR_TT# LGATE1

2200P_0402_50V7K
5
C C
6 NTC PVCC 31

10U_1206_25V6M

10U_1206_25V6M
1

1
7 PU10 30 LGATE_CPU2
SOFT LGATE2

PC122

PC123

PC124
ISL6262ACRZ-T_QFN48_7X7 PQ32 PC151
PC125 8 29 SI7686DP-T1-E3_SO8 470P_0402_50V7K

2
0.022U_0603_25V7K OCSET PGND2
4
1 2 9 28 PHASE_CPU2
VW PHASE2
PR151 13K_0402_1% 10 27 UGATE_CPU2-1 PL11
COMP UGATE2 0.36UH_FDU1040D-R36M_26A_20%
1 2

3
2
1
11 26 BOOT_CPU2
1 2 1 2 2 1
FB BOOT2 PR152
1 2

1
6.8_1206_5%
PC126 1000P_0402_50V7K 2.2_0603_5% PC127
DROOP

12 FB2 NC 25

1
VDIFF

ISEN2

ISEN1
VSUM

10K_0402_1%
PR154
VSEN

3.65K_0805_1%
PR153 6.81K_0402_1% 0.22U_0603_10V7K
GND

VDD
RTN

DFB

5
6
7
8

5
6
7
8

1
VIN

PR155
VO

1 2

PR157
PQ33 PQ34
1 2 AO4456_SO8 AO4456_SO8 PR156
13

14

15

16

17

18

19

20

21

22

23

24

1 2
1_0402_5%

2
PC128 1000P_0402_50V7K @ PR159
@PR159

2
680P_0402_50V7K
PC129
ISEN1 4 4 0_0603_5%
ISEN2 1 2

2
2

0_0402_5%

1K_0402_1%

PR160 97.6K_0402_1% PC130 470P_0402_50V7K 1 2 +5VS

1
@ PR161

1 2 2 1 PR158 1_0603_5% VSUM

1
PR162

1 2

3
2
1

3
2
1
PC133 220P_0402_50V7K PC131
1 2 1U_0402_6.3V4Z PC132
1

0.22U_0603_10V7K
2

VCC_PRM
PR163 PR164 ISEN2
255_0402_1% PC134 1000P_0402_50V7K 10_0603_5%
1 2 1 2 1 2 CPU_B+
B B
1

1 2 PC135
PR165 1K_0402_1% 0.1U_0603_25V7K
PR166
2

0_0402_5% PC136 820P_0402_50V7K

5 VCCSENSE 1 2 1 2
VSUM
1

PR167
1

20_0402_5% @PC137
@PC137 PC138
+CPU_CORE 1 2 0.022U_0603_50V7K 0.01U_0603_50V7K PR168
2

PR169 2.61K_0402_1%
2

0_0402_5%
5 VSSSENSE 1 2
2
1
11K_0402_1%

PC139 180P_0402_50V8J
2

PR171

1 2
2

PR170
20_0402_5% 1 2 1 2 PH3
10KB_0603_5%_ERTJ1VR103J
2

PR172 1K_0402_1% PR173 4.42K_0402_1%

1

VCC_PRM
PC140
0.1U_0402_16V7K
1 2

2 1
2

PC141 0.22U_0402_6.3V6K
PC142
A 0.22U_0603_10V7K A
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 46 of 50
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 2

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

D ISL6237 can't shutdown while battery ISL6237 can't shutdown while battery D

1 only. only. 0.1 41 Add PQ35 SB906100210 TP0610K. 20071031 EVT

Because we can cost down and B+ has another one.

2 Delete PD1 0.2 39 Delete PD1 SCSB540C080 (S SCH DIO B540C-13-F SMC) 20071115 DVT

3 3/5V exit on battery mode shutdown. To prevent 3/5V exit on battery mode shutdown. 0.3 41 Add SC100001K00 (S DIO 1SS355 SOD323 T/R-5K 20071211 DVT

Because PD11 has over temperature issue in JAQ60,

4 PD11 has over temp. issue. we change it to a 10A diode. 0.3 39 Change PD11 from SCSB540C080 to SCS00002F00 . 20071211 DVT

Add snubber in 3/5V by

5 EMI request. Add snubber in 3/5V by EMI request. 0.3 41 Add PR36 and PR39 to SD001470B80 20071211 DVT

6 Down size. Down size. by sourcer request. 0.3 46 Change PC136 from SE025821K80 to SE000003W00 20071211 DVT

7 Down size. Down size. by sourcer request. 0.3 46 Change PC120 and PC129 from SE024681J80 to SE074681K80 20071211 DVT

C 8 Down size. Down size. by sourcer request. 0.3 43 Change PC72 and PC74 from SE068102J80 to SE074102K80 20071211 DVT C

9 2nd source trial run TI controller. 2nd source trial run TI controller. 0.3 41 Add PC143 SE080105K80 20071211 DVT

Add snubber in 3/5V by

10 EMI request. Add snubber in 3/5V by EMI request. 0.3 41 Add PC33 and PC34 SE074681K80 20071211 DVT

11 To meet Jeta SPEC. To meet Jeta SPEC. 0.3 42 Add PC144 SE074102K80 20071211 DVT

Change PR41 from SD034619280(S RES 1/16W 61.9K 0402 1%)

12 Increase +5VALWP HW requirement. 0.4 41 to SD03463K280(S RES 1/16W 63.4K 0402 1%) 20080123 PVT

change PR94 from SD034604280(S RES 1/16W 60.4K 0402 1%)

13 Increase +5VALWP HW requirement. 0.4 43 to SD034576280(S RES 1/16W 57.6K 0402 1%) 20080123 PVT

Change PR116 from SD034100280(S RES 1/16W 10K 0402 1%)

14 Increase +5VALWP HW requirement. 0.4 44 to SD034105280(S RES 1/16W 10.5K 0402 1%) 20080123 PVT

41,42, Change PR37, PR40, PR61, PR106, PR109, PR138, PR152 from
15 Add EMI solution. For EMI requirement. 0.4 43,46 SD013000080(S RES 1/10W 0 +-5% 0603) to SD013220B80
(S RES 1/10W 2.2 +-5% 0603)
20080123 PVT
B B
Add PR64, PR104 and PR108 SD001470B80(S RES 1/4W 4.7
16 Add EMI solution. For EMI requirement. 0.4 43 +-5% 1206) 20080123 PVT

Add PC55, PC83 and PC89 SE074681K80(S CER CAP 680P 50V
17 Add EMI solution. For EMI requirement. 0.4 43 K X7R 0402) 20080123 PVT

Add PC145, PC146, PC147, PC148 SE074471K80

18 Add EMI solution. For EMI requirement. 0.4 41 (S CER CAP 470P 50V K X7R 0402) 20080123 PVT

Add PL12, PL13 SM010016410 (S SUPPRE_ KC FBMA-

19 Add EMI solution. For EMI requirement. 0.4 41 L11-322513-151LMA50T) 20080123 PVT

Change PQ26 from SB000002W80 S TR AO4916 2N SO8 to

20 AO4916 will be EOL. AO4916 will be EOL. 0.5 44 SB0000BG00 S TR AO4932_SO8 20080201 PVT

21 Thermal shutdown issue. Change OTP setting from 92C to 96C. 0.6 40 Change PR19 and PR22 to SD034133280(S RES 13.3K 0402 1%) 20080214 PVT

Add PC149,PC150,PC151 SE074471K80(S CER CAP 470P X7R

22 EMI request. EMI request. 0.6 46 0402) 20080214 PVT

A A

23

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 47 of 50
5 4 3 2 1
 5 4 3 2 1

11/28---------------------------------------
A --> B Change List Page 12, Add R536, R537 0_0402 with BOM Structure PM@
Page 30, Change U14 to G577NSR91U
12/13------------------------------------- Page 34, Change R438, R439, R441, R442 to 0_0603 (BOM Error)
Page 12, Mount R83, C179, C188 Page 35, Change R473, R467 to 2.2K_0402_5%
Change R91 BOM structure to @ Change R9, R11, R26, R28 to 0_0603 (BOM Error)
Page 19, Mount D21, D22, D23
Page 20, Change U40, U41 BOM structure to @ 11/27-------------------------------------
12/12-------------------------------------- Page 19, Change D5 to RB491D_SC59-3 accordig to Module design
D
Page 19, Change C430, C422, C406 with BOM structure GM@ Page 25, Update JSATA2(HDD) PCB footprint to OCTEK_SAT-22SU1G_22P_NR-T D

Page 20, Add R548, R549 2.2K_0402 with BOM structure @ Page 33, C313 change to 1U_0402_6.3V6K
Change R542, R543 BOM structure to PM@ Page 37, Mount R189, Q17 for +1.8V dischange circuit.
Change Q3, Q5, Q46, Q47 to BSH111
Page 28, Change T1 to SP050003T10 11/22--------------------------------------
Page 34, Change C603, C604 location and BOM structure to JAL90@ Page 26, Add R535 22_0402
Page 35, Change R449 to 43K_0402_1% Page 31, Add R534 0_0402 for +RTCVCC
Page 27, Add R550 with BOM structure @
Page 49, Add option component for C430, C422, C402, C429, C421, C405 11/19--------------------------------------
Del C419, C428, C432, C513, C214 (Option Component) Rev A
12/10--------------------------------------- Page 8, R482, R480 Pull down (CLK_DREF_96M#/CLK_DREF_SSC#)
Page 19, Add R544, R545 0_0402 with BOM structure JAL90@ Page 12, L32, L10, C505, C513, C263, C214 BOM Structure change to GM@
Page 20, Add U40, U41 SN74CBTD3306CPWR_TSSOP8 with BOM structure JAL90@ Add C513, C214 0_0402 (PM@) for Option Component (Page 49)
Page 35, Change R486, R477, R485, R476 to 56.2_0603 1% Page 23, Unmount R341
Page 38, Add R546, R547 10_0402_5% with BOM structure @ Mount R342
Update MCH and ICH part number. Page 28, Update R521, R522, R523, R524, R525, R526, R527, R528, R529, R530 function field.
U31 --> SA00001ZO30 (PM) Page 29, SWAP function of JMINI1 and JMINI2 (JMINI1 for Robson2, JMINI2 for WLAN)
SA00001P930 (GM) Delete C355 0.1U_0402
U9 --> SA00002AN10 (ICH9) Add R531 0_0402
C C
12/07--------------------------------------- Page 34, Add R533 0_0402 for ALC888VB DMIC_CLK
Page 12, Add C606, 220U_D2_4VM_R15 with BOM Structure GM@
Change C435 to 220uF_D2 with BOM Structure @ 11/14-------------------------------
Page 17, Update JMXM1 PCBfoot to QUASA_CA0481-230N00_230P-T Rev B
Page 20, Add R542, R543 4.7K_0402 with BOM Structure JAL90@ Page 7, 8, 9, 10, 11, 12, 13 change U31 BOM Structure from GM@ to JAL90GM@
Update Power Schematics Page 8, R102 BOM Structure change from GM@ to JAL90GM@
12/06---------------------------------------- Page 10, C210, C218, C222, C228, C208, C215, C220, C223 add BOM Structure PM@
Page 4, Add R541 10K_0402 with BOM Structure @ Page 49, Add C210, C218, C222, C228, C208, C215, C220, C223 option component BOM Structure JAL90GM@
Page 17, Add R534 0_0402 with BOM Structure PM@ Add U31 Cantiga-GL, LED1 with BOM Structure JAW50@
Change D30, R516 BOM Structure to @ Page 12, R396, C498 BOM Structure change from GM@ to JAL90GM@
Page 31, Add R540 100K_0402 with BOM structure JAW50@ R395 BOM Structure change from PM@ to GLPM@.
Change R186 BOM Structure JAL90@ Page 17, R331, R333 BOM Structure change from GM@ to JAL90GM@
Page 38, Add R533 10K_0402 with BOM Structure JAL90@ Page 19, R322, R327, R329 BOM Structure change from GM@ to JAL90GM@
Add C605 0.1U_0402 with BOM Strcture @ U28 add BOM Structure JAL90@
Change Q35 to 2N7002DW-T/R7_SOT363-6 Add R518, R519, R520 0_0402_5% for JAW50 CRT signal
12/05-------------------------------------- Page 20, R51, R52, Q4, R344, R336, C439, C440, R332, U30, R67, R72, Q3, Q5, D6, F2, C443,
Page 16, Update U15 to ICS9LPRS387BKLFT (SA000020H10) R351, R354, R358, R364, R365, R367, R372, R373, D19, C427, C431, U27,
Page 31, Delete R534 D20, R305, R306, 307, R308, R309, R310 add BOM Structure JAL90@
Page 34, Delete R533 Page 22, R408, R409, R410, R411 change BOM Structure from GM@ to JAL90GM@
B B
Page 38, Update JDOCK1 CIS Symbol to JAE_SP07-10207-19_68P-T Page 23, R38, R53, R40, R54, R55, R34, U5 change BOM Structure from GM@ to JAL90GM@
12/04--------------------------------------- Page 24, R160, R162 BOM Structure change from PM@ to GLPM@
Page 16, 17, 19 Delete Q23, Q37, Q38 2N7002DW-T/R7_SOT363-6 R159, R161 BOM Structure change from GM@ to GLPM@
Add Q48, Q49, Q50, Q51, Q52, Q53 2N7002_SOT23 Page 28, Add R521, R522, R523, R524, R525, R526, R527, R528, R529, R530 0_0402_5% for JAW50
Page 22, Add 10K_0402 with BOM Structure JAW50@ U1 add BOM Structure JAL90@
Change R61 BOM Structure to JAL90@ Page 29, C343, C352, C342, C344, C312, C355 add BOM Structure JAL90@
Page 31, Change R215 to 8.2K_0402 Page 32, Q15, LED1 add BOM Structure JAL90@
Page 34, Add C603, C604 220P_0402_50V8J with BOM structure @ Page 33, R512, C592, IR1, C593 add BOM Structure JAL90@
11/30---------------------------------------- R252 change BOM Structure from PM@ to GLPM@
Page 18, C368 change to 680P_0402_50V7K R250 change BOM Structure from GM@ to JAL90GM@
Page 20, D20 Change to CH751H-40PT_SOD323-2 Page 34, C583, C582, R445, C535, R442,R439 change BOM Structure from @ to 268@
Delete Q4 R490, R506 change BOM Structure from 268@ to @
Add Q46, Q47 2N7002_SOT23 with BOM Structure JAL90@ R441, R438 add BOM Structure 888VC@
Page 26, Delete R532, Q46 Page 35, R485, R476, R457, R460, R440, R444, R434, U39, R263, R255, R257, R261, C356, C353,
Add R538, R539 0_0402 with BOM Structure @ C354, U21, R265, C358, U22, C357, Q43 add BOM Structure JAL90@
Change D31 with BOm Structure @ Page 37, C272, C266, U11, C274, C273, R192, Q14, C278, R191 add BOM Structure PM@
Change U34 PN to SA00001W910 Page 38, R282, R284, Q35, R273 add BOM Structure JAL90@
Page 31 Change EC_SMB_CK2/DA2 Pull High to +3VS Rev A
A Page 32, Add SW4 with BOM Structure JAW50@ Page 37, Change R262 from 100K_0402 to 10K_0402 for Power Require(for 2.5V LDO). A

Change SW1 BOM Structure to JAL90@

Change JP2 Pin3/Pin4 to EC_SMB_CK2/DA2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 48 of 50
5 4 3 2 1
 5 4 3 2 1

B --> C Change List C --> C2 Change List

0220------------------- 0319-------------------
Page 6, Change C98 BOM structure to @ Page 20, Add R574 0 ohm with BOM Structure JAL90@
Page 32, Add R570 0 ohm with BOM Structure JAL9050@
0218--------------- Add R571 0 ohm with BOM Structure KAL20@
Page 20, Add R569 with BOM structure @ Add Q37 AO3413 with BOM Structure KAL20@
Page 23, R34, R38, R40, R53, R54, R55 change BOM structure to @ Add R575, R576 10K with BOM Structure KAL20@
D
Page 31, Change R215 to 18K Add Q54 2N7002DW with BOM Structure KAL20@ D
Update Power Schematics Update Power Schematics
Update U31 PN to SA00002JT50(GM)/SA00002JJ50(PM)
0213-----------------------------------
Page 11, Delete R113
Add J1 JUMP_43X79 with BOM structure @
Page 31, R558, R559 0 ohm with BOM structure @
C2 --> PreMP Change List
R560, R561 4.7K with BOM structure @ 0704----------------------
Page 32, R562, R563 0 ohm with BOM Structure @ Page 20, Change R51, R52, R67, R72, R542, R543, R574 BOM structure to JAL90PM@
R564, R565 0 ohm Page 37, Change U11 BOM structure to JAL90PM@
Page 38, Delete C619 Page 50, Add U11 SI4800BDY-T1-E3_SO8 withe BOM structure JAW50PM@
Add R566, R567, R568 0_0603 with BOM Structure JAL90@ Change U31 BOM Structure to JAW50GL@
0204---------------------------------- 0624-----------------------
Page 12, Change L31 to MBK1608301YZF_0603 with BOM structure GM@ Page 37, Change U12, U20, U23, U32 to SI4800BDY
Change R163 to 0_0805_5% 0610-----------------------
Page 23, Change BOM Structure of U5 to @ Page 23, Change R388 BOM structure to EM@
Page 27, Change BOM Structure of R555 and R550 to @ 0528--------------------------
Page 33, Change R217 to 31.6K_0402_1% Add ABO@ for Bluetooth/NewCard/CardReader option
Change C313 to 1U_0603_10V6K R222, C316, C317, C332, Q24, C308, C325, R235, Q26
C Page 34, Change R503 to FBMA-L10-160808-301LMT_0603 U14, U16, Q25, C310, C298, C283, C307, C292, C294, C304, C303, C281, C282, R220, C487, C480 C
01/31--------------------------------- C524, C525, C526, C527, C529, C530, C532, C533, C534, C543, C544, C545, C546, C544, C545
Page 23, Delete U10 C547, C548, C549, D26, R427, R428, R429, R430, R435, R436, R443, R452, R453, R535, U34
01/29--------------------------------- Page 23, Change R417 BOM structure to EM@
Page 23, Change R152 BOM Structure to @ Change R416 BOM Sturcture to ABO@
01/24-------------------------------- Page 31, Change R215 BOM structure to ABO@
Page 4, Change U8 to SA00001Z700 (EMC1402) Page 32, Change R570 BOM structure to JAL90@
Page 33, Change C338 to SE076104K80 Page 50, Add R215 with BOM structure EM@
Page 35, Mount C584 0523---------------------------
01/23--------------------------------- Page 4, Mount R541
Page 38 Delete F3, R558~560, C609~614 Page 32, Change R266, R268 Bom Structure to JAL90@
01/22------------------------------------- Page 50, Add R266 2.49K_0402_1% with BOM Structure JAW50@
Page 11, Delete R79 Add R268 1.69K_0402_1% with BOM Structure JAW50@
Change J1 Symbol to JUMP_43X79 Change JAW50 U31 PN to SA00002Q830
Page 33, Add R557 10K (Check) 0514-------(For JAW50 Analog MIC, EMI Requirement)
Change R245 BOM Structure with @ Page 34 change R439, R442 to FBMA-L11-160808-700LMT(SM010004010) with BOM structure 268@
Page 38, Add C609~614, R558~560 (Check) 0513-------(For Acer Lab P193WAx DVI Detect)
C607,608, 615~619 (Check) Page 20, Change R51, R52, R67 and R72 BOM structure to PM@
01/17------------------------------------- Page 50, Add R51, R52, R67 and R72 4.7K_0402 with BOM Structure JAL90GM@
B Page 11, Add R79 0_0805 0429-------(For PC Beep sound, volume down) B

Update Power Schematics Page 34, Change R496 to 1.3K

01/16------------------------------------ 0422------------------
Page 11, Delete R79 0_0805 Update U9 PN to SA00002JH70
Add J1 JUMP_43X79 Update U31 PN to SA00002JJA0/SA00002JTB0
Page 16, Change C296, R301 to 27P_0402 0410-------------------
Page 19, Change L17, L19, L21 BOM structure to GM@ Page 30, Add R577 0_0603 with BOM structure @
Page 23, Mount U29, R339 Add R578 0_0603
Add U10 with BOM structure @ (Co-lay with U5) 0407-------------------
Change R340 Bom structure to @ Page 20, change R574 BOM structure to PM@
Change U5 to MX25L4005AMC-12G_SO8 (SA00002A900) Page 31, change R550, R555, R561 BOM structure to JAL90GM@
Page 27, Change U26, C420 BOM structure to @ Change R215 to 33K
Change R550 to 0_0402 Page 32, change R266,R268 to 4.99K 1%
Add R555 0_0402 change R267 to 2.49K 1%
Page 32, Change R269 to 240_0402_5%, R267 to 453_0402_1% change R269 to 1.69K 1%
Change R268 pin1 connect to +5VALW Page 50, change JAL90 PCB P/N to DAZ04700100
Page 33, Change R217 to 18K_0402_1% with BOM structure PM@
Page 35, Add R551,R552, R553, R554 75_0603_1% with BOM structure JAL90@
Add D32 PJDLC05_SOT23-3
A A
Page 38, Add F3 3A_15VDC_SMD2920P300TF/15
Page 49, Add R551,R552, R553, R554 1K_0603_1% with BOM structure 268@
Add L17, L19, L21 0_0805 with BOM structure PM@
Update U38 (ALC268-VB1-GR ) PN:SA00001GD10 for JAW50
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 49 of 50
5 4 3 2 1
 5 4 3 2 1

PCB IC
ZZZ LA4201MB Rev0: DA600007400 U31 MCH
CRT 2 1
LA4201MB Rev1: DA600007410 R93 PM@ 0_0402_5%
PM@
LA4201MB with Small Board Rev1: DAZ04700100 C429 C421 C405 2 1
D 1 1 1 R104 PM@ 0_0402_5% D
PCB JAL90 LA-4201P LS-4201P/4202P/4204P/4205P/4207P/4208P CANTIGA ES_FCBGA1329
CANTIGA PM: SA00002JJA0 PM@ 2 PM@ 2 PM@ 2 2 1
15P_0402_50V8J R105 PM@ 0_0402_5%
15P_0402_50V8J 15P_0402_50V8J
U31 2 1
R114 PM@ 0_0402_5%
C406 C430 C422
JAW50GL@ 1 1 1 2 1
R115 PM@ 0_0402_5%
PM@ 2 PM@ 2 PM@ 2
CANTIGA ES_FCBGA1329 12P_0402_50V8J 2 1
CANTIGA GL: SA00002Q830 12P_0402_50V8J 12P_0402_50V8J R116 PM@ 0_0402_5%

15P_0402_50V8J: SE071150J80 2 1
R119 PM@ 0_0402_5%
U25 12P_0402_50V8J: SE071120J80

8102E@

2 1
RTL8102E-GR_QFN64P_9X9 L17 PM@ 0_0805_5%
RTL8102E-GR: SA00001YY00 2 1
0_0402_5%: SD028000080
L19 PM@ 0_0805_5%

2 1
U38 L21 PM@ 0_0805_5%
C C
GM45-HDMI
888VB@ 0_0805_5%: SD002000080 C210 C218
1 1

ALC888S-VB_LQFP48_7x7 2 2
ALC888S-VB: SA000026V10 JAL90GM@ JAL90GM@
0.1U_0402_16V7K 0.1U_0402_16V7K

U38 C222 C228

AUDIO 1 1

268@ 2 2
JAL90GM@ JAL90GM@
0.1U_0402_16V7K 0.1U_0402_16V7K
ALC268-GR_LQFP48_9X9 2 1
ALC268-VB1-GR : SA00001GD10 R551 JAW50@ 1K_0603_1%
2 1 C208 C215
R552 JAW50@ 1K_0603_1% 1 1
2 1
R553 JAW50@ 1K_0603_1% 2 2
2 1 JAL90GM@ JAL90GM@
R554 JAW50@ 1K_0603_1% 0.1U_0402_16V7K 0.1U_0402_16V7K
JAW50 Discrete 1K_0603_1%: SD014100180 C220 C223
1 1
U11
B 2 2 B
JAL90GM@ JAL90GM@
JAW50PM@ HDMI/DVI DDC Pull-High 0.1U_0402_16V7K 0.1U_0402_16V7K

SI4800BDY-T1-E3_SO8
0.1U_0402_16V7K: SE076104K80
SI4800BDY-T1-E3_SO8 : SB548000310 2 1
R51 JAL90GM@ 4.7K_0402_5%
2 1
R52 JAL90GM@ 4.7K_0402_5%
2 1 JAW50 LED
R67 JAL90GM@ 4.7K_0402_5%
2 1
R72 JAL90GM@ 4.7K_0402_5%
LED1
4.7K_0603_5%: SD028470180
JAW50@

HT-297DQ/GQ_AMB/YG_0603
KAW00 2 1
R268 JAW50@ 1.69K_0402_1%
2 1 1.69K_0402_1%: SD00000JB80
R215 EM@ 0_0402_5%
2 1
0_0402_5%: SD028000080 R266 JAW50@ 2.49K_0402_1%
A 2.49K_0402_1%: SD034249180 A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 50 of 50
5 4 3 2 1