Homework Problems for Basic Electronic Circuits (기초전자회로)

lectured by Professor Won Y. Yang

Chapter 5 MOSFETs
HW172E-051: E5.3(5점), Ex5.9(5점), Ex5.11(5점), E5.6(10점), E5.8(5점), P5.52a(10점), P5.52b(10
점), Ex6.1(10점), P6.6(15점)
HW172E-052: E6.3(15점), P6.23(10점),
P6.30(20점), P6.108(20점), P6.112(30점)

E5.3(30) Design of an NMOS circuit

Consider the NMOS circuit of Fig. 5.21 where the device parameters of the NMOS are VtN =0.8V,
kN =3.2mA/V2, and λ=0.

VDD=2.5V (a)(5) Determine the values of RD and RS so that the NMOS

kN=3.2mA/V2 operates at I D =0.4mA and VD =+0.5V.
RD Vt N = 0.8V
VD 1
ig=0 ID
M1
VG=0
VS 2

RS

VSS=-2.5V
Figure 5.21

(b)(5) With the values of RD and RS determined in (a), analyze the circuit to find I D and VD .

%Sedra05e03.m
kN=3.2e-3; Vt=0.8; % Device parameters
VDD=2.5; VSS=-2.5; RDb=5e3; RSb=3e3; % Circuit parameters
VGG=0; RG=0;
[VGb,VSb,VDb,VGSb,VDSb,IDb,modeb]= ...
FET_DC_analysis([VDD VSS],V??,RDb,RSb,kN,?t);

(c)(15) With RD =10kΩ and RS =2.1kΩ, analyze the circuit to find I D and VD in three ways: one by
using the MATLAB function ‘FET_DC_analysis()’, another one by directly solving a set of
nonlinear KCL equations in v=[v D v S], and the other through PSpice simulation.
(c1)(3) Complete and run the following MATLAB script “Sedra05e03c1.m”.
%Sedra05e03c1.m
RDc=10e3; RSc=2.1e3;
[VGc,VSc,VDc,VGSc,VDSc,IDc,modec]= ...
FET_DC_analysis([VDD VSS],VGG,RDc,R??,k?,Vt);

(c2)(7) Complete the following set of KCL equations in v=[v D v S] at the two nodes 1 and 2 of
the circuit.
VDD − v ( )
− i D ( v=
) 0 ; VDD − R D − v( =
) 0 (E5.3.5a)
v ( ) −VSS
i D ( v) − = 0 ; i D ( v) − =
v( ) + 0 (E5.3.5b)
RS
 Then complete and run the following MATLAB script “Sedra05e03c2.m”. If you don’t have
an m-file of MATLAB function ‘iD_NMOS_at_vDS_vGS()’ implementing the v-i relations
(Eqs. (5.16)&(5.17)) of a MOSFET, you need to make one and save it in a path belonging to
the path list that can be searched by MATLAB. Determine the operation mode of the NMOS
M1. Why is that?
%Sedra05e03c2.m
% To solve a set of KCL equatons.
iD=@(v)iD_NMOS_at_vDS_vGS(v(1)-v(2),-v(2),kN,Vt);
eq = @(v)[V??-RDc*iD(v)-v(?); % with v=[vD vS]
RSc*??(v)-v(2)+VSS]; % Eq.(E5.3.5)
options=optimset('Display','off');
v0=[0 -Vt]; % Initial guess
v=fsolve(eq,v0,options); ID=(VDD-v(1))/RDc
fprintf('\n Solution using fsolve: VD=%5.2f, VS=%5.2f, ID=%9.2e
(with vGD=%5.2f and Vt=%5.2f)\n',v(1),v(2),ID,-v(1),Vt)
function iD=iD_NMOS_at_vDS_vGS(vDS,vGS,Kp,Vt,lambda)
if nargin<5, lambda=0; end
vGD=vGS-vDS; ON=(vGS>Vt)&(vDS>0); SAT=(vGD<=Vt)&ON;
TRI=(vGD>Vt)&ON;
iD = Kp*(1+lambda*vDS).*((vGS-Vt).^2/2.*SAT + ...
((vGS-Vt).*vDS-vDS.^2/2).*TRI); % Eqs.(5.16),(5.17)
iD = max(iD,0);

(c3)(5) Referring to the PSpice schematic of Fig. E5.3.1 and/or opening the downloaded OrCAD
project file “Sedra05e03.opj”, perform the PSpice simulation to find VD, VS, and ID.

(d)(5) We can run the following script “Sedra05e03d.m” to draw the i D -v DS characteristic curves of
the NMOS M1 for v GS =1.3V and 1.66V as shown in Fig. E5.3.2. Write the equations for the
load lines, draw the load lines, and mark the Q-points for (b) and (c).
VDD − −v DS − VSS −v DS
=iD = for (b) and i D for (c) (E5.3.6a,b)

What is the red-dashed curve?

Figure E5.3.1 PSpice schematic Figure E5.3.2 i D-v DS characteristic curves and load lines
 %Sedra05e03d.m
iD=@(vDS,vGS)iD_NMOS_at_vDS_vGS(vDS,vGS,kN,Vt);
vDSs=[0:0.01:VDD-VSS];
plot(vDSs,[iD(vDSs,VGSb); iD(vDSs,VGSc)].', vDSs,kN/2*vDSs.^2,':')
hold on, plot(vDSs,(VDD-VSS-vDSs)/(RDb+RSb),'r', VDSb,IDb,'mo')
plot(vDSs,(VDD-VSS-vDSs)/(RDc+RSc),'r', VDSc,IDc,'mo')
axis([vDSs([1 end]) 0 1.2e-3]), grid on

Ex5.9(5) Diode-Connected Transistor

Consider the NMOS circuit of Fig. E5.9 where the device parameters of the NMOSs are VtN =0.5V,
k N =1.6mA/V2, and λ=0.

VDD=1.8V (a) Determine the values of RD1 and RD2 such that vD1 =1V
and M2 operates at the edge of saturation.
kN=1.6mA/V2
V = 0.5V
RD2 t N RD1
D1
D2 vD1
ID2 ID1
G2
M2 M1
G1
S2 S1
Figure E5.9

Ex5.11(10) Exercise 5.11

Consider the NMOS circuit of Fig. 5.23.1 where the device parameters of the NMOS M1 are
VtN =1V, k N =0.5mA/V2, and λ=0.
(a)(5) Analyze the circuit to find VD,Q and ID,Q. You can complete and run
VDD=+5V the following MATLAB script “Sedra05ex11.m”.
VBB= RD= %Sedra05ex11.m
+2V 10kΩ VDD=5; VBB=2; RB=0; RD=????; RS=0;
kN=0.?e-?; Vt=1;
VD [VGQ,VSQ,VDQ,VGSQ,VDSQ,IDQ,mode]= ...
ig=0 ID FET_DC_analysis(VDD,VBB,RB,RD,RS,kN,Vt);
M1
VG kN=0.5mA/V2
Vt N = 1V
VS=0

Figure 5.23.1
(b)(5) To see the Q-point (VD,Q =VDS,Q, ID,Q) on the corresponding i D -v DS characteristic curve of
the NMOS M1, complete and run the following MATLAB script “Sedra05ex11b.m”.
%Sedra05ex11b.m
VDD=5; Kp=0.5e-3; Vt=1;
vDSs=[0:1e-3:VDD]; vOVs=0:0.25:1.25;
clf, hold on
for i=1:length(vOVs)
vGS = Vt+vOVs(i); iDs=iD_NMOS_at_vDS_vGS(vDSs,vGS,Kp,Vt);
plot(vDSs,iDs), grid on
text(VDD/2,max(iDs),num2str(vGS,'v_{GS}=%5.2fV'))
end
plot(vDSs,Kp*vDSs.^2/2,'k:')
plot(vDSs,(VDD-????)/RD,'r', V??Q,I?Q,'mo')
 Figure 5.23.2 The i D -v DS characteristic curves and a load line

E5.6(15) Example 5.6

Find the drain current ID in the circuit of Fig. 5.24 where the parameters of the NMOS are
VtN =1V and k N =1mA/V2.
(a)(5) Assuming that the NMOS operates in the triode mode, analyze the circuit to check the
validity of the assumption.
VDD=+10V

RD= kN=1mA/V2
RG1= 8kΩ Vt N = 1V
10MΩ
ID VD
ig=0
M1
VG
VS
RG2=
10MΩ RS=
6kΩ

Figure 5.24

(b)(5) If the assumption of triode mode has turned out to be invalid, assume that the NMOS
operates in the saturation mode and analyze the circuit to check the validity of the
assumption.
(c)(5) Complete and run the following MATLAB script “Sedra05e06.m” to find ID, VD, and VS.
%Sedra05e06.m
VDD=10; R1=10e6; R2=10e6; RD=6e3; RS=6e3; Kp=1e-3; Vt=?;
[VGQ,VSQ,VDQ,VGSQ,VDSQ,IDQ,mode]=...
FET_DC_analysis(VDD,R1,R2,RD,RS,Kp,??);
E5.7(15) Example 5.7
Find the drain current ID in the circuit of Fig. 5.25 where the parameters of the PMOS are VtP =-
1V and k P =1mA/V2.
(a)(5) Assuming that the PMOS operates in the saturation mode,
VSS=+5V analyze the circuit to check the validity of the assumption
two times, once with RD =7.9kΩ and once with RD =8.1kΩ.
kP=1mA/V2
R1= Vt P = -1V
2MΩ VS
ID
ig=0
M1
VG
R2= VD
3MΩ RD

Figure 5.25

(b)(5) For RD =8.1kΩ, assuming that M1 is in triode, write the KCL equation at node D in ID or
VSD and solve it.
(5)
(c) Complete and run the following MATLAB script “Sedra05e07.m” to find ID and VD with
RD =7.9kΩ and RD =8.1kΩ.
%Sedra05e07.m
Kp=????; Vt=-1; % Device parameters
VSS=5; R1=2e6; R2=3e6; RS=0; % Circuit parameters
RDs=[7.9e3 8.1e3];
for i=1:length(RDs)
[VGQ,VSQ,VDQ,VSGQ,VSDQ,IDQ,mode]= ...
FET_PMOS_DC_analysis(VSS,R1,R2,RS,RDs(i),??,Vt);
end

E5.8(15) Example 5.8

Consider the circuit of Fig. 5.26 where the NMOS and PMOS are
+2.5V
kN=1mA/V2 matched with k N =k P =1mA/V2 and VtN =-VtP =1V, and λ=0.
igP=0 Vt N = 1V
MP kP=1mA/V2 (a)(5) For v I =0V, analyze the circuit to find I DP, I DN, and v o.
VGP- Vt P = -1V (b)(5) For v I =+2.5V, analyze the circuit to find I DP, I DN, and v o.
VDG,P
+ IDP
vI vo
-
VGD,N IDN
VGN+
MN
igN=0
-2.5V
Figure 5.26
(5)
(c) Complete and run the following MATLAB script “Sedra05e08.m” to find the values of I DP,
I DN, and v o for v I =-2.5V, 0, and +2.5 when R L =1kΩ and 10kΩ.
%Sedra05e08.m
VSP=2.5; VSN=-2.5; VSS=[VSP VSN]; RL=1e3;
KN=1e-3; KP=1e-3; KNP=[KN KP]; VtN=1; VtP=-1; VtNP=[VtN VtP];
lambda=0; Kg=1;
vis=[-2.5 0 2.5]; % Value(s) of the input voltage vI
[iDPs,iDNs,vos]=FET2_complementary(vis,RL,VSS,K??,??NP,lambda)
[VIL,VIH,VOL,VOH,Vm,VIT1,VOT1,VIT2,VOT2,VLH,NML,NMH,PDavg]=
CMOS_inverter(KNP,VtNP,VDD,Kg);
 Table E5.8
vI I DP I DN vo
-2.5V 0A 1.97V
R L =1kΩ 0V 11mA 0V
+2.5V 0A 20mA
-2.5V 2mA 0A
R L =10kΩ 0V 11mA 0V
+2.5V 0A -2.44V

VDD P5.52(10+10) Consider the two circuits shown in Figs. P5.52(a) and (b)
VGG =5V where the NMOS transistors have Vt =1V, k N =2mA/V2, and
=2.5V kN=2mA/V2 λ=0V-1.
D1 Vt = 1V
+ (a1)(5) For the circuit of Fig. P5.52(a), find I D , v 1 , and v 2 .
(a2)(5) Complete and run the following MATLAB script
M1 vDS1 “Sedra05p52a.m” to find the values of I D , v 1 , and v 2 .
G1
S1
D2 v1
ID +
G2
M2 vDS2

S2 v2
R S=
1kΩ

VSS=
-5V
Figure 5.52(a)

%Sedra05p52a.m
k=2e-3; Vt=1; VDD=10; VSS=-5; VG1=5; VG2=0; RS=1e3;
iD=@(vGS,vDS)iD_NMOS_at_vDS_vGS(vDS,vGS,k,Vt);
eq=@(v)[iD(VG1-v(?),VDD-v(1))-iD(VG2-v(2),v(1)-v(?));
v(?)-VSS-RS*iD(VG2-v(?),v(1)-v(2))]; % KCL at S1,S2
v0=[0 0]; v=fsolve(eq,v0), ID=iD(VG1-v(1),VDD-v(1))
(b1)(5) For the circuit of Fig. P5.52(b), find I D , v 1 , and v 2 .
VDD=
10V (b2)(5) Complete and run the following MATLAB scripts
“Sedra05p52b.m” to find the values of I D , v 1 , and v 2 .
2
RD= kN=2mA/V
1kΩ Vt = 1V
D1
v1
+
G1 M1 vDS1
S1
v2
D2 +
G2 M2 vDS2

S2 v3
R S=
1kΩ

Figure 5.52(b)
 %Sedra05p52b.m
k=0.4e-3; Vt=1; VDD=10; RD=1e3; RS=1e3;
iD=@(vGS,vDS)iD_NMOS_at_vDS_vGS(vDS,vGS,k,Vt);
eq=@(v)[VDD-v(?)-RD*iD(v(1)-v(?),v(1)-v(2));
iD(v(1)-v(2),v(?)-v(2))-iD(v(2)-v(3),v(?)-v(3));
v(?)-RS*iD(v(2)-v(3),v(2)-v(?))]; % KCL at D1,S1,S2
v0=[0 0 0]; v=fsolve(eq,v0), ID=iD(v(1)-v(2),v(?)-v(2))
-------------------------------------------------------------------------------------------------------------------------
Ex6.1(5) Exercise 6.1 (Exercise 5.16 in the 6th ed.)
Consider the amplifier of Fig. 6.2(a) where VDD = 1.8V, RD = 17.5kΩ,
VDD=1.8V kn' (W/L) =4mA/V2, and Vt = 0.4V. Determine the end points A and B
of the saturation-region segment of the VTC. Also, determine VDS,C
at v GS,C=VDD.
RD=
iD 17.5kΩ %Sedra06ex01.m
kN=4mA/V2 % To solve Exercise 6.1 of Sedra (7th ed.)
D
Vt = 0.4V clear, clf
G + Vt=0.4; kN=4e-3; VDD=1.8; RD=17.5e3; Kg=2;
M1 % Plot the VTC curve and find the ABC points
vGS
+ vo=vDS subplot(121)
S [vOs,iDs,vIs]=
VTC_NMOS_amplifier(k?,V?,RD,VDD,[],Kg);
axis([0 VDD 0 VDD+0.1]); hold on
fprintf(' vIs vOs iDs\n');
Figure 6.2(a)
disp([vIs vOs iDs])

P6.6(5) Consider the amplifier of Fig. 6.4(a) where VDD = 5V, RD =24kΩ, kn' (W/L) =1mA/V2, and Vt = 1V.
To find the answers to the following questions, you can complete and run the following MATLAB
script “Sedra06p06.m”.
(a) Find the coordinates of the two end points of the saturation-region segment of the VTC, that
is, points A and B on the sketch of VTC like Fig. 6.4(b).
(b) If the amplifier is biased to operate with an overdrive voltage VOV = 0.5V, find the coordinates
of the bias point Q on the transfer characteristic. Also, find the values of I D and the incremental
voltage gain Av at the bias point.
(c) For the situation in (b), and disregarding the distortion caused by the MOSFET’s square-law
characteristic, what is the largest amplitude of a sine-wave voltage signal that can be applied
at the input while the NMOS remains in saturation? What is the amplitude of the output voltage
signal that results? What gain value does the combination of these amplitudes imply? By what
percentage does this gain value differ from the incremental gain value calculated above? Why
is there a difference?

%Sedra06p06.m
clear, clf
kN=1e-3; Vt=1; VDD=5; RD=24e3; Kg=2;
[vDS,iD,vGS]=VTC_NMOS_amplifier(kN,??,RD,VDD,[],Kg); % To find A,B,C
xlabel('v_{GS}'); ylabel('v_D');
format long; [vGS vDS iD], format short
Vov=0.5; Av=-kN*RD*Vov, vGS_o=Vov+Vt;
vGSs = [2*vGS_o-vGS(2) vGS_o vGS(2)];
[vDSs,iDs]=VTC_NMOS_amplifier(??,Vt,RD,VDD,vGSs); vDS_o=vDSs(2);
hold on, plot(vGS_o,vDS_o,'mx','Markersize',7); grid on
string=['(' num2str(vGS_o,'%5.2f') ',' num2str(vDSs(2),'%5.2f') ')'];
text(vGSs(2),vDSs(2),string)
Av1=(vDSs(3)-vDSs(1))/(vGSs(3)-vGSs(1))
 VDD=5V

RD=
iD 24kΩ
kN=1mA/V2D
Vt = 1V
G +
M1
vGS
+ vo=vDS
S

Figure 6.2(a)

E6.3(15) Example 5.10 of the 6th ed.

kN=0.25mA/V2 VDD
Vt N = 1.5V
VA=50V RD
RG
vO
iD
iG=0
M1
vi vGS RL vvO=
DS

Rin
Figure 5.39 (a)

(a)(3) DC analysis to get the operating (bias) point.

%Sedra06e03a.m
kN=0.25e-3; Vt=1.5; VA=50;
VDD=15; RG=1e7; RD=1e4; RS=0; RL=1e4;
IDs=roots([kN*RD^2/2 -(1+kN*RD*(VDD-Vt)) kN*(VDD-??)^2/2])
VGSs=VDD-RD*IDs, format short e; ID=IDs(find(VGSs>=Vt))
VGS=VDD-RD*ID;
(b)(10) Small-signal analysis
To perform the small-signal analysis, we replace the NMOS with its small-signal model to
obtain the AC equivalent where the coupling capacitors have been replaced by short circuits
and the DC voltage source VDD has also been replaced by a short circuit to ground.
%Sedra06e03b.m
gm=kN*(VGS-??), ro=??/ID
Rp=parallel_comb([RG ro RD RL]), Av=Rp*(1/RG-gm) % Eq.(E6.3.10)
% Another way to find gm and ro
FET_DC_analysis(VDD,'RG',RD,RS,kN,Vt);
(c)(2) Find the maximum allowable amplitude of a sinusoidal signal vgs without distortion.
P6.23(10) (5.48) Consider the amplifier of Fig. 6.10 where VDD = 10V, VGS = 4V, RD =3.6kΩ, k N =1mA/V2,
and Vt = 2V.
(a) Find ID and VDS .
VDD=10V %Sedra06p23a.m
kN=1mA/V2 VDD=10; VGS=4; Rs=0; RD=3.6e3; RS=0; RL=inf;
Vt N = 2V RD= kN=1e-3; Vt=2;
iD 3.6kΩ [VD,ID]=VTC_NMOS_amplifier(kN,Vt,RD,VDD,V??)
D (b) Find the value of gm at the bias point.
G +
M1
+ +
vgs S vo=vDS
vGS (c) With λ=0V-1, find the voltage gain Av =vds /vgs .
VGS
=4V
Figure 6.10

How about using the MATLAB function ‘FET_CS_analysis()’ by typing the following
statement in the MATLAB Command window?
>>FET_CS_analysis(VDD,Rs,VGS,0,RD,RS,RL,kN,Vt);
(d) With λ=0.01V-1, find ro at the bias point and calculate the voltage gain Av =vds /vgs .
Apply KCL at node D to write a node equation to be solved for vDS or iD and solve it to find
new values of VD or ID.
kN
VDD − ( − Vt ) 2 (1 + λ )= (P6.23.3a)
2
k
= N( − Vt ) 2 {1 + λ (VDD − iD )} (P6.23.3b)
2

%Sedra06p23d.m
lambda=0.01; VA=1/lambda;
eqa=@(vDS)VDD-vDS-RD*kN/2*(VGS-V?)^2*(1+lambda*vDS);%Eq.(P6.23.3a)
vDS0=VGS; VDS1=fsolve(eqa,vDS0)
eqb=@(iD)iD-kN/2*(V??-Vt)^2*(1+lambda*(VDD-RD*iD)); %Eq.(P6.23.3b)
iD0=0; ID1b=fsolve(eqb,iD0)
ID1=(VDD-VDS1)/RD
gm1=kN*(VGS-Vt)*(1+lambda*VDS1) % Eq.(6.40)
ro1=(VA+VDS1)/abs(ID1) % Eq.(6.37)
How about using the MATLAB function ‘FET_CS_analysis()’ by typing the following
statement in the MATLAB Command window?
>>FET_CS_analysis(VDD,Rs,VGS,0,RD,RS,RL,kN,Vt,VA);

P6.30(30) Consider the amplifier of Fig. P6.30.

kN=4mA/V2 VDD=15V
Vt N = 1V
R 1= RD=
10MΩ 16kΩ
D
Cs
G CL
M1 ID
VG +
R s= VGS- S RL=
200kΩ R 2= 16kΩ
vs RS= CS
5MΩ
Ri 7kΩ

Figure P6.30
 (a)(5+5) Assuming that the NMOS M1 has Vt =1V and kn = kn' (W/L) =4mA/V2, verify that the
bias circuit establishes I D =0.5mA and VS =3.5V by writing a KCL equation (in I D or V S )
at node S (on the assumption that M1 operates in the saturation mode) and checking if the
equation is satisfied by the values I D and VS . Then check if v GS ≥V t and v GD <V t for the
validity of the assumption.
For additional points, complete and run the following MATLAB script to get the values
of V G , VS , V D , and I D in two ways, one by solving Eq. (P6.30.1) and the other by using the
MATLAB function ‘FET_DC_analysis()’.
%Sedra06p30a.m
VDD=15; Rs=2e5; R1=10e6; R2=5e6; RD=16e3; RS=7e3; RL=16e3;
kN=4e-3; Vt=1;
VG=R2/(R1+R2)*VDD;
eq=@(iD)iD-k?/2*(VG-RS*iD-?t)^2;
iD0=0; IDs=fsolve(eq,iD0); ID=IDs(find(VG-RS*IDs>=0))
VD=VDD-RD*ID;
if VG-VD<Vt, fprintf('M1 is in saturation.');
else fprintf('M1 is in triode and you must redo the analysis.');
end
FET_DC_analysis(VDD,R1,R2,RD,RS,kN,Vt); % not considering VA

(b)(5+5) Find gm, ro, Ri, Av =vo /vgs , and Gv =vo/vs where λ=1/VA =0.01V-1.
To recompute the value of ID considering the Early effect with λ=0.01V-1, write an
equation to be solved for iD and solve it to find ID.
kN
iD = (VG − iD − Vt ) 2 {1 + λ (VDD − iD − iD )} (P6.30.3)
2
For additional points, perform the PSpice simulation.
%Sedra06p30b.m
lambda=0.01; VA=1/lambda;
eq=@(iD)iD-kN/2*(V?-RS*?D-Vt)^2*(1+lambda*(VDD-(RD+RS)*?D));
iD0=0; ID1=fsolve(eq,iD0)
VD1=VDD-RD*I??; VS1=RS*ID1; VDS1=VD1-VS1;
gm1=kN*(?G-VS1-Vt)*(1+lambda*VDS1) % Eq.(6.40)
ro1=(VA+VDS1)/abs(ID1) % Eq.(6.37)
% (1+lambda*VDS1)/lambda/abs(ID1)
Av1=-gm1*parallel_comb([RD RL ro1]) % Eq.(6.91)

kN=4mA/V2
Vt N = 1V

(a) PSpice schematic Figure P6.30.1 (b) Simulation results

 (c)(5) Draw a small-signal equivalent circuit for the amplifier and find R i, A v =vo /vgs , and Gv =vo /vs
with λ=0V-1.
(d)(5) Referring to the PSpice schematic in Fig. P6.30.1(a), perform the simulation (with the
Analysis type of Time Domain (Transient) for t = 0~2ms) to get i s (t) and vo (t) for
v s =50sin(2000πt)[mV] like Fig. P6.30.1(b). From the PSpice simulation results, find R i and
Gv =vo /vs. Fill Table P6.30 with the values of R i and Gv obtained so far.

Table P6.30
Book solution MATLAB PSpice
Ri 3.33MΩ
Gv –14.5

VDD=5V P6.108(15) (P5.80) Consider the CS amplifier of Fig.

kN=11.1mA/V 2
P6.108 where the NMOS has kn =11.1mA/V2,
Vt N = 0.7V RD= Vt =0.7V, and VA =50V.
VA=100V R 1=
300kΩ 5kΩ (a)(5) Neglecting the Early effect, find ID, VGS, and
Cs
D VD.
G CL (b)(5) Considering the Early effect with λ=1/VA
M ID
1
VG + =0.02V-1, find ID, VS, VD, gm, ro, Av, and Gv. To
R s= VGS- S RL=
120kΩ recompute the value of ID considering the Early
R 2=
vs 200kΩ RS= CS 5kΩ effect with λ=0.01V-1, write an equation to be
Ri 2kΩ solved for iD and solve it to find ID.
kN
iD = (VG − iD − Vt ) 2 {1 + λ (VDD − iD − iD )}
Figure P6.108 2

%Sedra06p108_1b.m
VDD=5; R1=3e5; R2=2e5; RD=5e3; RS=2e3;
Rs=120e3; RL=5e3; kN=11.1e-3; Vt=0.7; VA=50; lambda=1/VA;
VG=R2/(R1+R2)*VDD;
eq=@(iD)iD-k?/2*(VG-RS*i?-V?t)^2*(1+??????*(VDD-(RD+RS)*i?));
iD0=0; ID1=fsolve(eq,iD0)
VD1=VDD-RD*ID1; VS1=RS*ID1; VDS1=VD1-VS1;
gm1=kN*(VG-VS1-V?)*(1+lambda*VDS1) % Eq.(6.40)
ro1=(VA+VDS1)/???(ID1) % Eq.(6.37)
% (1+lambda*VDS1)/lambda/abs(ID1)
Av1=-gm1*parallel_comb([RD RL ro1]) % Eq.(6.91)

(c)(5) Letting vsig be a sinusoid with a peak amplitude v̂sig , find the maximum allowable value of
v̂sig for which the NMOS remains in saturation so that no distortion in vo can be incurred.
Find the corresponding amplitude of vo.
P6.112(40) (P5.82) Consider the circuit of Fig. P6.112 where VDD =5V, VSS=-5V, kn = kn' (W/L) =5mA/V2,
VA= 40V, and Vt = 0.8V.
(a)(2) Neglecting the Early effect, find the values of RG , RS , and
VDD=5V RD (the largest possible value) so that the input resistance
kN=5mA/V 2 at the gate is 10MΩ and the NMOS can remain in
Vt N = 0.8V
RD saturation with ID,Q =0.4mA while a maximum signal
swing of ±0.8V at the drain with VD,Q =0V is possible.
D Y
Cs C L
G
X M1 ID
VG +
VGS
- S Z
RG CS
RS

VSS=-5V
Figure P6.112

(b)(3) Find the values of gm and ro at the bias point.

%Sedra06p112b.m
VDD=5; VSS=-5; R1=Inf; R2=1e7; RD=12.5e3; RS=9.5e3;
kN=5e-3; Vt=0.8; VA=40;
FET_DC_analysis([VDD V??],R1,R2,RD,[0 ??],k?,Vt);
FET_DC_analysis([V?? VSS],R1,R?,RD,[? RS],kN,V?,V?); % consider VA

kN =5mA/V2
Vt N = 0.8V
VA = 40V

(a1) PSpice schematic to measure Ri and Gv

(b1) Simulation results for vs (t)=sin(2000πt)[μV]

(a2) PSpice schematic to measure Ro (b2) Simulation results for vT (t)=sin(2000πt)[mV]

Figure P6.112.1 PSpice simulation

(c)(10) With terminal Z grounded, terminal X connected to a signal source having a resistance of
1MΩ, and terminal Y connected to a load resistance of 10kΩ, find the input/output resistances
and the overall voltage gain Gv . Referring to the PSpice schematics shown in Fig. P6.112.1,
perform the Pspice simulation (with the Analysis type of ‘Time Domain (Transient)’ for
t = 0~2ms) to measure the input/output resistances and voltage gain Gv .
%Sedra06p112c.m
Rs=1e6; RL=1e4;
FET_CS_analysis([V?? VSS],Rs,R?,R2,RD,[? R?],RL,k?,Vt,VA);
(d)(10) With terminal Y grounded, find the voltage gain from X to Z open-circuited. Also, find the
input/output resistances of the source follower. Referring to the PSpice schematics shown in
Fig. P6.112.2, perform the Pspice simulation (with the Analysis type of ‘Time Domain
(Transient)’ for t = 0~2ms) to measure the input/output resistances and voltage gain Gv .
%Sedra06p112d.m
disp('(d) CD amplifier')
Rs=0; RL=1e8;
FET_CD_analysis([VDD V??],Rs,R1,R?,[? R?],RS,RL,kN,V?,VA);

kN =5mA/V2
Vt N = 0.8V
VA = 40V

(a1) PSpice schematic to measure Ri and Gv (b1) Simulation results for vs (t)=sin(2000πt)[μV]

(a2) PSpice schematic to measure Ro (b2) Simulation results for vT (t)=sin(2000πt)[mV]

Figure P6.112.2

(e)(10) With terminal X grounded and terminal Z/Y as input/output terminals, find the input/output
resistances and the voltage gain where the effect of ro is neglected for simplicity. Then, with
terminal Z connected to a current source of 50μA having a resistance of 100kΩ, find the
amplitude of v Y. Referring to Fig. P6.112.3, perform the Pspice simulation to check the validity
of your solution.
%Sedra06p112e.m
disp('(e) CG amplifier')
Rs=100e3; RL=???; Vsm=Rs*50e-6;
[VGQ,VSQ,VDQ,IDQ,Av,Ri,Ro,gm,ro,Vom,vsmax]= ...
FET_CG_analysis([VDD VSS],Rs,R?,R2,RD,RS,R?,k?,Vt,VA,Vsm);
 kN =5mA/V2
Vt N = 0.8V
VA = 40V

(a1) PSpice schematic to measure Ri and Gv

(b1) Simulation results for is (t)=50sin(2000πt)[μA]

Figure P6.112.3

kN =5mA/V2
Vt N = 0.8V
VA = 40V

(a2) PSpice schematic to measure Ro with RS(RSc) AC short-circuited

(b2) Simulation results for v T (t)=sin(2000πt)[mV]

Figure P6.112.3 (continued)

If you see a nonnegligible difference between the MATLAB/PSpice values of Ro, how about
using ‘FET_CG_analysis()’ as
>>FET_CG_analysis([VDD VSS],Rs,R1,R?,RD,[? R?],RL,kN,Vt,VA,Vsm);
 kN =5mA/V2
Vt N = 0.8V
VA = 40V

(a3) PSpice schematic to measure Ro with RS(RSc) not AC short-circuited

(b3) Simulation results for v T (t)=sin(2000πt)[mV]

Figure P6.112.3 (continued)

(f)(5) Fill Table P6.112 with the values of R o and Gv obtained so far and those found in the solution
manual.
Table P6.112
Book solution MATLAB PSpice
Ri - 3.33MΩ
CS Gv –9.6 –9.73
Ro - 11145Ω
Ri - 10MΩ
CD Gv –0.946 0.9464
Ro 473Ω 466Ω
Ri - 520 Ω
CG Gv 0.6/5=0.12 0.118
R o with RS AC
short-circuited - 11145Ω
Chapter 15 CMOS Digital Logic Circuits
E15.2(5) Example 15.2 (Example 14.1 in the 6th ed.)
Consider the MOS inverter of Fig. E15.2(a) (Fig. 14.2(a) in the 6th ed.).
vo

kN =4.5mA/V2
Vt N = 0.5V
VA = ∞ V
VDD= 1.8V

iD RD= 25kΩ
D
G +
M
vI=vGS vO=vDS
S

vi

(a) An NMOS inverter (b) VTC

Figure E15.2 Resistor-loaded NMOS inverter

(a) Assuming λ=0 to neglect the Early effect, express the inverter parameters VOH , VOL , VIL, VIH ,
and VM in terms of VDD, Vt , and kn RD =1/Vx .
(b) Find the value of Vx =1/kn RD that results in VM =VDD/2.
(c) With VDD =1.8V, Vt =0.5V, and Vx set to the value found in (b), find the numerical values for
all parameters and for the noise margins.
(d) For kn' =300μA/V2 and W/L=1.5, find the required value of RD .
(e) Run the following MATLAB script “Sedrea15e02.m” to plot the VTC of the inverter like Fig.
E15.2(b) and find the low/high noise margins. Fill Table E15.4 with those values.

%Sedra15e02.m
% Solve Example 15.2(c) of "Microelectronic Circuits" by Sedra/Smith.
clear, clf
VDD=1.8; Vt=0.5; kN=???e-4; % MOSFET inverter parameters
% Set the design parameter Vx=1/kN/RD so that VM=VDD/2.
VM=VDD/2; Vx=(VM-Vt)^2/2/(VDD-VM); % Eq.(15.13)/(14.7) in p1244/p1175
RD=1/Vx/kN; Kg=2; % See p1174 for the definition of design parameter Vx
[VIL,VIH,VOL,VOH,VM,VIC,VOC,NML,NMH,PD]=MOSFET_inverter(k?,V?,RD,VDD,Kg);

Table E15.2
VOH VOL VIL VIH VM NML NMH
Book solution 1.8V 0.12V 0.59V 1.06V 0.9V 0.47V 0.74V
MATLAB
E14.2(5) The Saturated NMOS-Load Inverter. (Example 14.2 in the 6th ed.)
Consider the inverter of Fig. E14.2(a) (in the 6th ed.) where Vt1 =Vt2 =Vt.

VGG
=5V

kN1=1.5mA/V2
Vt N 2 = 0.5V
VA 2 = ∞ V
kN2=0.06mA/V2
Vt N 2 = 0.5V
VA 2 = ∞ V
VDD= 1.8V
D2
iD2 +
M2 vDS2
v IG2
S2
D1 vO
iD1 +
G1
M1 vDS1

S1

(a) An NMOS inverter (b) VTC

Figure E14.2 NMOS-loaded NMOS inverter

(a) Assuming that λ1 =λ2 =0 to neglect the Early effect, express the inverter parameters VOH , VOL ,
VIL, VIH , and VM in terms of VDD, Vt , and k r = kn1 / kn 2 .
(b) For VDD =1.8V, Vt =0.5V, (W/L)1 =5, and (W/L)2 =1/5, find numerical values for all parameters
and for the noise margins.
(c) Run the following MATLAB script “Sedrea14e02.m” to plot the VTC of the inverter like Fig.
E14.2(b) and find the values of the inverter parameters VOH , VOL , VIL, VIH , VM , and the noise
margins. Fill Table E15.4 with those values.

%Sedra14e02.m
% Solve Example 15.3(c) of "Microelectronic Circuits" by Sedra.
clear, clf
VDD=1.8; Vt1=???; Vt2=0.5; k1=5*3e-4; k2=3e-4/5; Kg=1;
subplot(121) % See Fig. 14.11(d)
[VIL,VIH,VOL,VOH,VM,VIC,VOC,NML,NMH,PDavg]= ...
MOSFET2_inverter([k? k2],[Vt1 Vt?],VDD,Kg);
vIs = [VIL:0.1:VIC VM VIC VIH VOH];
subplot(122) % See Fig. 14.11(c)
[vOs,iDs]=MOSFET2_inverter_iD_vI([k1 k?],[Vt? Vt2],VDD,vIs,Kg);
subplot(121), plot(vIs,vOs,'g.')

Table E14.2
VOH VOL VIL VIH VM NML NMH
Book solution 1.3V 0.04V 0.5V 0.75V 0.63V 0.46V 0.55V
MATLAB
E15.4(5) Example 15.4 (Example 14.4 in the 6th ed.)
Consider a CMOS inverter of Fig. E15.4(a) with VDD=1.8V, Vtn =-Vtp =0.5V, VA=5V, and kn =kP =
4.5×10-4 [A/V2].

kP =15mA/V2
Vt P = -0.5V
VAP = ∞ V
kN =4.5mA/V2
Vt N = 0.5V
VAN= ∞ V

VDD= 1.8V
+
v +
-SGP
MP vDSP
iDP-
vI iDP=iD=i vO=vDSN
iDN
+
+ MN vDSN
vGSN
- -

(a) An NMOS inverter (b) VTC

Figure E15.4 CMOS inverter

(b) Run the following MATLAB script “Sedrea15e04.m” to plot the VTC of the inverter like Fig.
E15.4(b) and find the values of the inverter parameters VOH , VOL , VIL, VIH , VM , and the noise
margins. Fill Table E15.4 with those values.

%Sedra15e04.m
clear, clf
VDD=1.8; VtN=???; VtP=????; kN=???e-4; kP=kN; VA=5;
subplot(221)
vIs=[0:0.05:VDD]; Kg=1;
[vOs,iDs]=CMOS_inverter_iD_vI([kN k?],[Vt? VtP],VDD,VA,vIs,Kg);
subplot(222)
CMOS_inverter([kN kP],[VtN VtP],VDD,VA);
plot(vIs,vOs,'m:')

Table E15.4
VOH VOL VIL VIH VM NML NMH
Book solution 1.8V 0V 0.8V 1V 0.9V 0.7V 0.7V
MATLAB