Received 22 March 2016; revised 13 July 2016; accepted 23 July 2016.

Date of publication 3 August 2016; date of current version 6 June 2018.

Digital Object Identifier 10.1109/TETC.2016.2597542

Analytical Model for Resistivity and Mean Free Path

in On-Chip Interconnects with Rough Surfaces
SOMESH KUMAR, (Student Member, IEEE) AND ROHIT SHARMA , (Senior Member, IEEE)
The authors are with the Department of Electrical Engineering, Indian Institute of Technology Ropar, Nangal Road, Rupnagar 140001, India
CORRESPONDING AUTHOR: R. SHARMA (rohit@iitrpr.ac.in)

ABSTRACT Planar copper interconnects suffer from surface roughness that results in performance degra-
dation. This paper presents a novel analytical model for calculation effective resistivity and mean free path in
on-chip copper interconnects. The closed form expressions are obtained from a generalized surface and grain
boundary scattering approach that is combined with Mandelbrot-Weierstrass (MW) fractal function. It is
observed that resistivity increases while mean free path reduces significantly for rough on-chip interconnects
when compared with that of smooth lines. Current and future technology nodes i.e., 45 nm, 22 nm, 13 nm
and 7 nm are considered for our analysis. The analytical models are validated against industry standard field
solvers Ansys Q3D Extractor and previous data available in literature that exhibit excellent accuracy. Finally,
we also present computational overhead in terms of simulation time, matrix size, number of tetrahedrons and
memory for different values of roughness and technology nodes.
INDEX TERMS On-chip interconnects, surface roughness, fractals, resistivity, mean free path, resistance,
current density

I. INTRODUCTION and overall increase in resistance [10], [11]. Over the past
Reduced device dimensions and increased component den- several years, very limited analysis has been reported on the
sity on the chip has resulted in higher transistor speeds. How- role of surface roughness in determining the overall intercon-
ever, the same has led to increased interconnect delay and nect performance. Therefore, it is imperative to develop com-
losses [1]. Conventional copper (Cu) based planar intercon- pact analytical models that can give physical insights about
nects suffer from lower data-rates [2] and higher delay than the effect of rough surface profiles on various interconnect
required to keep pace with continuous transistor scaling. As performance metrics [12]. A first step towards this is to
we traverse through lower technology nodes, increase in develop closed form expressions of local resistivity, effective
resistivity becomes a major issue for on-chip interconnects resistivity and mean free path in rough interconnects lines.
[3]. This increase in Cu resistivity is primarily due to electron We also need to understand computational overheads associ-
scattering resulting from the surface and grain boundary [4], ated with analyzing rough on-chip interconnect structures.
[5]. Resistivity further increases when any critical intercon- The central theme of this paper revolves around answering
nect dimension decreases below the electron mean free path some of these important points.
of copper i.e., 39 nm [6]. In the past, planar Cu interconnects In this paper, we present a novel analytical model for compu-
have been considered to have homogeneous smooth surfaces. tation of local resistivity, effective resistivity and mean free
However, contrary to this belief, Cu suffers from surface path of on-chip Cu interconnects with rough surfaces. The
roughness that can adversely affect the interconnect perfor- rough surface profile has been modeled using the well-known
mance [7], [8]. Roughness may be intentionally or uninten- Mandelbrot-Weierstrass (MW) function [13]. In our analysis,
tionally introduced during fabrication processes to increase we have considered two categories of on-chip interconnects
the adhesion between the dielectric and conductor surfaces i.e., local/intermediate and global interconnects. Further, we
[9]. This, in turn leads to increase in the conductor losses. have considered various current and future technology nodes
Also, it is seen that scattering phenomena is higher at rough such as 45 nm, 22 nm, 13 nm and 7 nm [14]. Resistivity and
surfaces of Cu lines, which leads to size effects that result in mean free path of rough Cu on-chipinterconnect line are mod-
higher effective resistivity, lower effective mean free path eled considering size effects. It is seen that size effect is more
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 Kumar and Sharma: Analytical Model for Resistivity and Mean Free Path in On-Chip Interconnects with Rough Surfaces
critical for future technology nodes when width or thickness is
lower than the mean free path of Cu. The increase in resistivity
is due to reduced electron relaxation time (z) [15] and is given
by the following relationship:

0
z¼ ; (1)
n
where, v is the velocity of electrons at the surface and l0 is
their effective mean free path. As given in (1), the effective
mean free path is less than bulk mean free path (MFP) due to
the decrease in relaxation time at lower technology nodes
(sub-40 nm) [15, 16]. In addition, rough surfaces result in
further reduction in the effective cross-sectional area and
relaxation time [17]. Our proposed expressions for local
resistivity, effective resistivity and mean free path consider
these size effects. Our proposed expressions for effective
resistivity are compared with data available in the literature
that exhibit excellent accuracy. Interconnect resistance is
then calculated from the effective resistivity and validated
using simulations performed on industry standard EM solver,
Ansys Q3D Extractor with an overall accuracy of 6 per-
cent. In our analysis, we also present the relation between
local resistivity (LR) and line dimensions. Based on our mod-
els, it is seen that resistivity increases while MFP reduces
with technology scaling and extent of roughness. Also, it is
seen that LR varies according to surface profile of conductor
line and is higher at the narrower cross sections where rough-
ness peaks or valleys are maximum. For local/intermediate
interconnects at 13 nm technology node, effective resistivity
increase by 2.5x when we consider maximum permissible
surface roughness. Similarly, for global interconnects at 13
nm node, line resistivity due to surface roughness increases
by 2.4x when compared to smooth surfaces. The MFP due to
rough surfaces decreases by 29 percent for local/intermediate
and by 26 percent for global interconnects as compared to
smooth lines. These effects get further aggravated when we
move to 7 nm technology node. Interconnect resistance p.u.l.
increases by nearly 9x for 7 nm local/intermediate intercon-
nect for maximum value of roughness. Finally, we present
the computation overhead for simulating of rough intercon-
nect structures. Our results shows that simulation time, mem-
ory, matrix size and number of tetrahedron increases by 2.8x,
2.3x, 2.4x and 3.1x, respectively due to horizontal surface
profile variation for local/intermediate on-chip Cu intercon-
nects at 7 nm node.
The remaining part of this paper is organized as follows:
Section II, describes the brief summary of the work that has
been done on modeling of surface profiles in Cu sheets and
various approaches employed in calculating equivalent para-
sitics for rough metal sheets. Section III, presents the standard
3-line ITRS interconnect structure and surface profile function
used for analysis. In Section IV, we present the proposed mod-
els for calculating local resistivity, effective resistivity and
MFP. Section V presents the results highlighting the effect of
roughness on the resistivity, resistance and mean free path of
on-chip local/intermediate and global interconnects. Verifica-
tion of our analytical results with simulation data obtained
234
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using Ansys Q3D Extractor and available literature has been
presented in this section. Computational complexity for rough
on-chip interconnects is also presented in Section V. Impor-
tant conclusion are summarized in Section VI.
II. BACKGROUND WORK
Surface roughness in Cu interconnects is primarily due to the
material characteristics and is introduced during the various
fabrication steps like chemical mechanical polishing and
chemical etching. The roughness of a surface is accounted in
terms of the vertical deviations on that surface [18] and is
characterized in terms of various statistical parameters such
as RMS height, correlation length and autocorrelation func-
tion [9]. Authors in [19] have numerically modeled the effect
of square and triangular shaped rough surfaces on conductor
losses. Small perturbation method and numerical method of
moments are developed to find the effect of surface rough-
ness on absorption at microwave frequencies. In [20], a broad
methodology that includes different modeling techniques,
dependent on frequency and conductor geometry, for analy-
sis of resistive losses is introduced. There are different types
of analytical and empirical methods available in the literature
to describe the profile of rough surfaces [21]. Power series
and Fast Fourier Transform methods are classically used for
modeling the profile of rough surfaces [22], [23]. Computa-
tion of roughness profile function using atomic force micros-
copy has been reported in [24]. In the available literature,
most of the reported work is on modeling the rough surface
profile that is dependent only on the RMS value and not on
the horizontal profile variation. These models are approxi-
mate and fail to provide physical insights into the effects of
surface roughness. In particular, the Mandelbrot–Weierstrass
function, which uses the concept of self-similar fractals, is
well suited to model the profile of rough surfaces in copper
interconnects due to its inherent advantages over other classi-
cal methods [25]. The MW function contains spatial informa-
tion as well as information on profile deviation. We can find
average or RMS value of the roughness using this MW
approach [26]. In this approach, the surface roughness is
described by a fractal dimension, D, which is scale indepen-
dent [27]. Later, in our analysis, we shall be using the MW
function to model the rough surface of on-chip interconnects.
Authors in [28], [44] have investigated the reduction of
thermal conductivity in Cu and tungsten nanowires structures
due to edge roughness. The Nabha model proposed by
authors in [29] gives the effect of roughness on resistivity
and temperature coefficient of thin copper films. The authors
report that electrical conduction is dependent on the thick-
ness of the metal film and the electron MFP ( 40 nm).
In that, as the thickness approaches the electron mean free
path, the resistivity increases [30]. This further aggravates
when the thickness is lower than the electron MFP, which
can be a serious issue in on-chip interconnects at lower tech-
nology nodes. Authors in [31], [32] have introduced a correc-
tion factor which is applied to find the resistivity for various
roughness profiles. All the previous literature is limited to
VOLUME 6, NO. 2, APRIL-JUNE 2018
 Kumar and Sharma: Analytical Model for Resistivity and Mean Free Path in On-Chip Interconnects with Rough Surfaces
FIGURE 1. (a) Standard 3 line interconnect structure given by
ITRS and (b) roughness distribution function plot for different
fractal dimension, D. N ¼ 6.
find the roughness effects on resistivity and mean free path
for thin metal sheets. Further, to the best of our knowledge,
closed form expressions for resistivity and mean free path in
high-speed on-chip Cu interconnects with rough surfaces has
not been reported in the available literature. Unlike previous
literature, we propose a compact analytical model for local
and effective resistivity and mean free path estimation in cop-
per interconnects with rough surfaces that gives physical
insights on the dependence of these parameters on surface
profile. We also present a computational complexity analysis
of on-chip rough surface interconnects to estimate the extra
effort required for simulation.
III. BASIC INTERCONNECT STRUCTURE AND SURFACE
PROFILE
Conventionally, rough surfaces are random in nature and
various statistical parameters such as RMS value, surface
heights, slopes and curvature are used to define their rough-
ness [33]. Rough surfaces in interconnects exhibit the feature
of self-similarly and self-affinity, by which same appeara-
nces of the surfaces are seen under various degrees of
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magnification. Due to this property, higher amount of rough-
ness is seen when we decrease the length scale. So, these sta-
tistical parameters strongly depend on the resolution and
scan length of the instrument used to measure the roughness
and hence are not unique for a particular surface [34]. The
fractal approach is used to define the natural rough surface
because this approach is instrument independent and is scale
invariant [34] and provide the roughness extent by a number
called fractal dimension, D, which is unique for a particular
surface. Fractal Brownian model (Fbm) is most useful model
for defining natural surfaces. It is nonstationary & stochastic
in nature and is non-differential everywhere. Fbm is approxi-
mated by MW fractal function. MW fractal function satisfies
the property of continuity, non-differentiability, self-affinity.
It can therefore be used to characterize the natural rough sur-
faces of interconnects. MW fractal function is based on
power laws and fractal dimension, D, and RMS height, h,
can be used to define microscopic roughness [35]. Therefore,
it is most appropriate to use the MW function for modeling
the rough surfaces in IC interconnects. The MW function
that defines the roughness profile is given by:
"sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi#
2Dð2  DÞ X N 1
f ðxÞ ¼ h 2N
ðD  1Þn sin ðK0 bn x þ fn Þ:
1  ðD  1Þ n¼0
(2)
Here, h is the RMS height of the profile and f(x) is the
roughness distribution function. K0 is the spatial frequency, b
is the frequency multiplier and its value is greater than 1, fn
is the phase of the rough profile and N is the number of spa-
tial frequency components on the surface or number of tones.
Typically, D lies between 1 and 2 with fractal value for
smooth surface being 1.
Maximum practical value of D in Cu interconnects is 1.6,
beyond which surface roughness is not expected due to pro-
cess control [36], [37]. Roughness dependent parameters i.e.,
D, h can be calculated directly from AFM and a realistic pro-
file of roughness can be obtained from this MW function.
For model development, we have assumed roughness on the
all the four surfaces of the Cu 3-line structure, as shown in
Figure 1(a). Typical interconnect dimensions as per ITRS
projections are given in Table 1. Width of line is w, thickness
is t, height from the reference ground is h, and spacing
between the two interconnect lines is s. Each surface of cop-
per line have different values of RMS height and fractal
dimension, D. Thus, roughness distribution function is differ-
ent on each surface. Figure 1(b), shows the roughness distri-
bution function for different values of D. It is clearly seen
that as fractal dimension, D, increases from 1.0 to 1.6, the
roughness increases accordingly.
A set of data points is generated in Matlab using the MW
function for each surface that defines its roughness. We then
use a Visual Basic (VB) script to create any geometry or shape
in HFSS simulator for validation of our analytical models [1],
[9]. The advantage of this methodology is that it is applicable
for any surface profile and any interconnect structure.
235
 Kumar and Sharma: Analytical Model for Resistivity and Mean Free Path in On-Chip Interconnects with Rough Surfaces

TABLE 1. Typical Interconnect Parameters.

On-Chip Interconnects [ITRS 2013]

Technology
node Local/Intermediate Global
Parameters 45 nm 22 nm 13 nm 7 nm 45 nm 22 nm 13 nm 7 nm
Pitch (w þ s) 90 nm 44 nm 27 nm 13 nm 135.5 nm 64 nm 40 nm 20 nm
Width (w) 45 nm 22 nm 13 nm 7 nm 67.5 nm 32 nm 20 nm 10 nm
Thickness (t) 81 nm 44 nm 26 nm 15.4 nm 155.25 nm 80 nm 46.8 nm 24 nm
Aspect Ratio (AR) 1.8 2.0 2.0 2.20 2.3 2.5 2.34 2.40
Spacing (s) 45 nm 22 nm 14 nm 6 nm 68 nm 32 nm 20 nm 10 nm
Height from ground (h) 77 nm 45 nm 27 nm 12 nm 148.5 nm 76.8 nm 35 nm 20 nm
Dielectric (er) 2.9 2.55 2.15 1.65 2.9 2.55 2.15 1.65

IV. PROPOSED MODEL at the metal-dielectric interface at side wall surfaces and w is
In this section, we present our proposed model to find the the width of interconnect.
resistivity and MFP of on-chip interconnects considering sur- Mayadas-Shatzkes (M-S) model [39], [40] derives the
face roughness. expression for resistivity considering grain boundary scatter-
ing, which is given by:
A. RESISTIVITY "    2
rbulk 1
0 x
0 x
Resistivity in Cu interconnects depends on surface scattering rg ¼  þ
and grain boundary scattering of electrons as well as the 3 3 2d ð1  xÞ d ð1  xÞ
 3   (5)
impurities present on the surface and bulk of the interconnect
0 x dð1  xÞ 1
line. Surface roughness in deeply scaled Cu interconnects   ln 1 þ ;
d ð1  xÞ
0 x
gives rise to size effects because vertical height of roughness
becomes comparable to critical dimensions of the intercon- where, d is average grain size and x is reflection coefficient.
nect line. Fuchs-Sondheimer (F-S) model to find the resistiv- Note that, the total effective Cu resistivity increases with
ity considering surface scattering along the upper and lower both surface and grain boundary scattering, and can be calcu-
surface is given by [38]: lated as [41]:
 Z 1 h
3
rupper=lower ¼ rbulk 1  dqðq  q3 Þ rs ¼ rbulk þ ðrupper=lower  rbulk Þ þ ðrsidewall  rbulk Þ
4ðt=
0 Þ 0 (6)
   #1 þ ðrg  rbulk Þ ;
2 1  p1 p2 eðt=q
0 Þ 1  eðt=q
0 Þ  ðp1 þ p2 Þð1  eðt=q
0 Þ Þ2
 :
ð1  p1 p2 e2ðt=q
0 Þ Þ where, rs is the effective interconnect line resistivity for
(3) smooth surfaces.
Here, rupper/lower is the resistivity of Cu interconnect consid- We now calculate the effect of roughness on this effective
ering scattering only on upper and lower surfaces. p1 and p2 are resistivity. Every interconnect surface, as shown in Figure 2,
the specularity parameters used to describe the surface scatter- has different values of rms height, specularity parameter and
ing at the metal-dielectric interface on upper and lower surfaces fractal dimension. Therefore, roughness distribution function
and their values lie 0 to 1 [38]. l0 is the bulk mean free path cal- or surface profile is different for each surface.
culated using the Fermi free electron model, t is interconnect Due to upper and lower surface profiles, the thickness of
thickness, rbulk is bulk resistivity of copper and the constant q the line varies at each point along the length of wire. Also,
is dependent on the scattering angle (u) and is given as q ¼ due to sidewall roughness, the width of interconnect varies at
cos u [38]. Note that this equation considers the surface scatter- each point along its length. The modified thickness and width
ing but it does not take into account the effect of roughness. are given by:
Similarly to (3), resistivity considering surface scattering
along the sidewall surfaces of the on-chip interconnect is
given by:
 Z 1
3
rsidewall ¼ rbulk 1  dqðq  q3 Þ
4ðw=
0 Þ 0
   #
2 1
2 1 p3 p4 ew=q

ð 0 Þ 1  eðw=q
0 ÞÞ  ðp þ p Þ 1  eðw=q
0ÞÞ
3 4
 :
ð1  p3 p4 e2ðw=q
0 Þ Þ
(4)
Here, rsidewall is the resistivity of Cu interconnect consider-
ing scattering only on sidewall surfaces, p3 and p4 are the
specularity parameters used to describe the surface scattering FIGURE 2. Cu interconnect with unique profile functions.

236 VOLUME 6, NO. 2, APRIL-JUNE 2018

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 Kumar and Sharma: Analytical Model for Resistivity and Mean Free Path in On-Chip Interconnects with Rough Surfaces

t 0 ¼ t þ f1 ðxÞ þ f2 ðxÞ; (7a) LR is maximum wherever interconnect cross section is mini-

0 mum. LRupper/lower across the width of the interconnect line
w ¼ w þ f3 ðyÞ þ f4 ðyÞ: (7b)
due to rough upper and a lower surface is given by:
Here, f1(x), f2(x), f3(y) and f4(y) are the rough surface profile   0  
tr
MW functions for upper, lower and both side wall surfaces, LRupper=lower ¼ r 1 rbulk þ upper=lower
t0  rbulk :
bulk
respectively.
Substituting (7) in (3) and (4), we get the resistivity due to  
þ rg  rbulk :
roughness in upper/lower and sidewalls, respectively as
given below: (13a)
 Z 1
3 Similarly, LRupper/lower across the width of the interconnect
r0upper=lower ¼ rbulk 1  0
dqðq  q3 Þ
4ðt =
0 Þ 0 line due to rough sidewall surfaces is given by:



2 31 
2 1  p1 p2 eðt =q
0 Þ 1  eðt =q
0Þ  ðp1 þ p2Þ 1  eðt =q
0Þ
0 0 0
h
wr0  i
7 LRsidewall ¼ r 1 rbulk þ  r
 5 bulk :
sidewall
0
ð1  p1 p2 e2ðt0 =q
0 ÞÞ bulk w

  (13b)
(8) þ rg  rbulk :
 Z 1
3
r0sidewall ¼ rbulk 1  dqðq  q3 Þ
4ðw0 =
0 Þ 0 B. MEAN FREE PATH



2 31
2 1  p3 p4 eðw =q
0 Þ 1  eðw =q
0 Þ  ðp3 þ p4 Þ 1  eðw =q
0 Þ 7
0 0 0 The ratio of effective MFP to bulk MFP in Cu interconnects
 5 : considering rough surfaces from can be derived from (11),
ð1  p3 p4 e2ðw0 =q
0 Þ Þ
which is given as:


(9)
0s ¼  
0 
;
The average resistivity of Cu interconnects considering 1 þ
r
0  1 þ
r
0  1 þ

0g  1
upper=lower sidewall
upper/lower (rrupper/lower) and sidewall (rrsidewall) rough sur-
faces is given by integration of (8) and (9) over the width (14)
and thickness, respectively [29], which is given by: where, lrupper/lower
is the effective MFP of Cu interconnects
" Z !# considering roughness only on upper and lower surfaces,
1 w t  r0upper=lower while lrsidewall is the effective MFP considering roughness
rupper=lower ¼
r
dx (10a) only on sidewall surfaces. lrupper/lower and lrsidewall are calcu-
w 0 t0
lated using (10) and is given by:
 Z t  
1 w  r0sidewall
rupper=lower ¼  
1

rsidewall ¼
r
dy : (10b) R
(14a)
t 0 w0 1 w
dx t
w 0 t 0 
0
upper=lower
The total effective resistivity (rrough) due to rough surfaces
is given by: 1
h
rsidewall ¼    ; (14b)
R
rrough 0 ¼ rbulk þ ðrrupper=lower  rbulk Þ þ ðrrsidewall  rbulk Þ 1 t
0 dy
w
w0 
0sidewall
t
þ ðrg  rbulk Þ :
where, l0 upper/lower is obtained by replacing t with t0 whereas
(11a) l0 sidewall is obtained by replacing w with w0 . We now have a
There is a linear relationship between resistivity and tem- self-consistent model that incorporates the surface profile
perature [42], [43], which is given as: function and can compute resistivity, resistance, LR and
MFP for any interconnect structure.
rrough 0 ðT Þ ¼ ½1 þ aðT  T0 Þrrough 0 : (11b)
V. RESULTS AND ANALYSIS
Here, a is the temperature coefficient of resistance, T0 is Based on our proposed model, the effect of surface rough-
0
the room temperature and rrough is the effective resistivity at ness on resistivity, mean free path and resistance in Cu inter-
room temperature. connect are presented in this section. Our analytical results
The interconnect line resistance p.u.l. can be computed for resistance are compared with previous data and data
using standard expression and is given by: obtained using EM solver, Ansys Q3D Extractor for the
rrough 0 interconnect structure shown in Figure 1.
Rp:u:l: ¼ : (12)
tw
A. MODEL VALIDATION
Local resistivity defines the resistivity at any point in a Cu To verify the veracity of our proposed model, the effective
interconnect line whose cross-section varies with the profile resistivity computed using our proposed model are compared
of the surface. The integral part of (10) is called local resistiv- with existing data which is shown in Figure 3. In [39],
ity (LR) [43] that varies according to its cross-sectional area. authors have calculated the effective resistivity as a function

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 Kumar and Sharma: Analytical Model for Resistivity and Mean Free Path in On-Chip Interconnects with Rough Surfaces

FIGURE 3. Resistivity comparison using our proposed model and

[39]. T ¼ 300 K. Average grain size is considered equal to w [39].
The value of p, x, rms value and D are obtained from [39]. Aspect
ratio considered here is 2.0. p1 ¼ p2 ¼ p3 ¼ p4 ¼ p, N ¼ 6.

of line edge roughness, specularity parameters and grain

reflectivity, x. The input parameters used in our model are
equated with that of [39]. First we calculate the effective
resistivity with no surface scattering, i.e., h ¼ 0, p ¼ 0.95,
x ¼ 0.40 and D ¼ 1.0. These values indicate that electron
scattering is a result of mostly due to grain boundary reflec-
tion. Extending the analysis further, the effective resistivity
is plotted for D ¼ 1.01, h ¼ 2.4 nm, p ¼ 0.95, and x ¼ 0.40.
The added roughness increases resistivity by 18 percent for
10 nm width with aspect ratio of 2. FS-MS resistivity model
for smooth line is also compared with our models which
shows that our model is more accurate than FS-MS resistivity
model owing to consideration of sidewall as well as upper
and lower surface scattering. For all cases, results obtained

FIGURE 5. Local resistivity of 7 nm local/Intermediate line as a

FIGURE 4. Resistance for different technology nodes and differ-
ent values of D. (a) 7 nm technology node (b) 22 nm technology
node. p1 ¼ p2 ¼ p3 ¼ p4 ¼ 0.6, x ¼ 0.1, T ¼ 300K, N ¼ 6.
function of width for different RMS value of roughness (a) D ¼
1.1 and (b) D ¼ 1.6. T ¼ 300K. p1 ¼ p2 ¼ p3 ¼ p4 ¼ 0.6, x ¼ 0.1, N ¼
6.
from our model show excellent agreement (i.e., < 4 percent
error) with available data, as shown in Figure 3.
Figure 4 shows the plot of resistance p.u.l. for 7 nm and 22
nm technology nodes for both local/intermediate and global

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 Kumar and Sharma: Analytical Model for Resistivity and Mean Free Path in On-Chip Interconnects with Rough Surfaces

lines. Here, the resistance calculated using our proposed

model is compared with simulation data obtained using
industry standard EM solver Q3D Extractor that exhibits an
overall accuracy of 5 percent. For local/intermediate and
global interconnects at 7 nm technology node, resistance p.u.
l. increase by 9x and 6x respectively when we consider maxi-
mum permissible surface roughness. From Figure 4(b), it is
shown that for local/intermediate and global line at 22 nm
line resistance increases by 10 and 7 percent for global inter-
connects as compared to smooth line.

B. RESISTIVITY AND MEAN FREE PATH

The local resistivity (LR) across the width and thickness of
Cu interconnect line is computed using (13). Figure 5(a),
shows the variation of resistivity locally across the width of
the interconnect line. In Figure 5(a), we consider the rough-
ness D ¼ 1.1 for top and bottom surface of 7 nm line with
different RMS values. It is clear that as RMS roughness is
increased the LR increases. At the wider sections of the line,
local resistivity decreases due to size effect. In this figure,
maximum peaks in LR are seen at the narrow sections of line
which is due to reduction in thickness. Figure 5(b) shows LR
as a function of width for D ¼ 1.6. It is seen that as fractal
value increases from 1.1 to 1.6, its roughness increases and
accordingly LR also varies. The peaks are shown at the nar-
row sections of the copper line where thickness is minimum.
Similarly, Figure 6 shows the LR across the thickness of
the copper interconnect line. From Figure 6(a), it is clear that
as RMS value of roughness increases, LR also increases and
maximum peaks are shown at narrow sections of line. When
value of fractal dimension D increases from 1.1 to 1.6, LR
further increases. Figure 6(b) shows the LR as a function of
thickness for D ¼ 1.6. From this plot, it is seen that with
increasing the value of D, the LR varies with higher peaks.
In Figure 7, the effective resistivity of Cu interconnect
lines as a function of their critical dimensions is shown.
Figure 7(a). shows the effective resistivity of local/intermedi-
ate lines as a function of technology nodes ranging from
45 nm to 7 nm for different extent of roughness. From this
figure, it is evident that surface roughness adds a significant
contribution to the total resistivity of the interconnect. Effec-
tive resistivity of local/intermediate interconnect increases by
17 percent for 22 nm technology node and it further increases
when we move to lower technology nodes. At 7 nm technol-
ogy node, resistivity further increases by 80 percent when we
increase the rms value of roughness for top, bottom and side
wall surfaces, which is shown in Figure 7(a). For global
interconnect lines, resistivity increases by 5x for 7 nm tech-
nology node, which is shown in Figure 7(b). The temperature
dependent resistivity for local/intermediate interconnects is
shown in Figure 7(c). Typical temperature range is from 25o
C to 85o C, which is a standard temperature range for nano- FIGURE 6. Local resistivity of 7 nm local/Intermediate line as a
meter-scale application processors. As expected from (11b), function of thickness for different RMS value of roughness
the resistivity increases for increasing temperature. However, (a) D ¼ 1.1 and (b) D ¼ 1.6. T ¼ 300K, p1 ¼ p2 ¼ p3 ¼ p4 ¼ 0.6,
effect of surface roughness on resistivity is not dependent on x ¼ 0.1, N ¼ 6.
temperature.

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 Kumar and Sharma: Analytical Model for Resistivity and Mean Free Path in On-Chip Interconnects with Rough Surfaces
FIGURE 7. Effective resistivity for different technology nodes and
different values of D. (a) Local/intermediate interconnects, T ¼
300K (b) Global interconnects, T ¼ 300K (c) Local/intermediate
interconnects at different temperatures. h1 is rms value of rough-
ness for top surface, h2 is rms value of roughness for bottom
surface and h3, h4 are rms value for side wall surfaces. p1 ¼ p2 ¼
p3 ¼ p4 ¼ 0.6, x ¼ 0.1, a ¼ 3.9e-3, N ¼ 6.
240
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FIGURE 8. Effective mean free path for different technology
nodes and different values of D. (a) Local/intermediate intercon-
nects (b) Global Interconnect. T ¼ 300K. h1 is rms value of rough-
ness for top surface, h2 is rms value of roughness for bottom
surface and h3, h4 are rms value for side wall surfaces. p1 ¼ p2 ¼
p3 ¼ p4 ¼ 0.6, x ¼ 0.1, N ¼ 6.
From (14), effective mean free path for a Cu line is cal-
culated for both local/intermediate and global intercon-
nects. When technology scales down the effective MFP
decreases due to surface and grain boundary scattering.
Surafce scattering and grain boundary scattering effect is
more prounced when any dimension reaches below the
bulk MFP. Due to decrease in MFP, the effective resistiv-
ity increases. For 22 nm local/intermediate interconnects,
the effective MFP for smooth surface is 22.73 nm which
decreases marginally to 21.3 nm for rough surfaces in case
of local/intermediate lines. However, for 7 nm technology
node, effective MFP decreases significantly (by 80 per-
cent), as shown in Figure 8(a). From this analysis, it is
clear that as technology scales down, MFP as a function
of roughness decreases exponentially. Similarly, observa-
tions are noted in Figure 8(b) for 7 nm global intercon-
nects with MFP reducing by 67 percent.
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 Kumar and Sharma: Analytical Model for Resistivity and Mean Free Path in On-Chip Interconnects with Rough Surfaces
FIGURE 9. 3D view of mesh generated in HFSS. (a) Case 1
(Smooth line, D ¼ 1.0) (b) Case 2 (Only top and bottom surface
rough, D ¼ 1.1) (c) Case 3 (all four surfaces rough, D ¼ 1.1) (d)
Case 4 (all four surface rough, D ¼ 1.6). T ¼ 300K, N ¼ 6.
From the analysis reported in this section, it is clear that sur-
face roughness will be a major performance limiting factor for
lower technology nodes towards the end of the roadmap.
C. COMPUTATION COMPLEXITY
In this section, we now analyze the computational effort
required to perform simulations for rough on-chip Cu inter-
connect lines. Four cases are considered: Case 1 (D ¼ 1.0,
h1 ¼ h2 ¼ h3 ¼ h4 ¼ 0), Case 2 (D ¼ 1.1, h1 ¼ h2 ¼ 1.4
nm, h3 ¼ h4 ¼ 0), Case 3 (D ¼ 1.1, h1 ¼ h2 ¼ 1.4 nm,
h3 ¼ h4 ¼ 1.15 nm), Case 4 (smooth line, D ¼ 1.6, h1 ¼
h2 ¼ 1.4 nm, h3 ¼ h4 ¼ 1.15 nm). Here, we discuss the fac-
tors that involved in creating HFSS models and simulations.
Figure 9, shows the finite element method (FEM) mesh gen-
erated for all the four cases. From Figure 9, it is clearly seen
FIGURE 10. 3D view of volume current density generated in HFSS
(a) Case 1 (Smooth line, D ¼ 1.0) (b) Case 2 (Only top and bottom
surfaces are rough, D ¼ 1.1) (c) Case 3 (all four surfaces are
rough, D ¼ 1.1) (d) Case 4 (all four surfaces are rough, D ¼ 1.6).
T ¼ 300K, N ¼ 6.
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FIGURE 11. Bar plot for all the four cases for 7nm local/Intermedi-
ate interconnect line. (a) Matrix Size (b) Memory.
that mesh becomes very dense when we move from lesser
roughness (case 1) to higher roughness (case 4).
Figure 10 shows the current distribution in local/
intermediate interconnects at 7 nm technology node.
From Figure 10, it is clearly seen that roughness peaks
and valleys act as discontinuities. The current density and
electric field decreases due to increasing roughness, as
shown in cases 1 to 4.
Figures 11 and 12 highlight the important factors that define
computational power involved in simulation of HFSS models
for smooth and rough interconnects. For solving any structure
in HFSS and Q3D solver, tetrahedral mesh is generated. From
Figure 9, it is clear that meshing becomes very dense at the
rough surfaces which lead to higher complexity, computa-
tional power and simulation time than smooth surfaces. The
simulations reported here are performed on a Linux based Intel
FIGURE 12. Bar plot for all the four cases for 7nm local/Intermedi-
ate interconnect line. (a) Simulation Time (b) Number of
Tetrahedrons.
241
 Kumar and Sharma: Analytical Model for Resistivity and Mean Free Path in On-Chip Interconnects with Rough Surfaces
Xeon system with 32 GB RAM and 12 cores distributed across
two physical processors. Figure 11 shows the comparison of
matrix size and memory required for simulation for all four
cases. It is clearly seen that matrix size and memory
increases with roughness. Figure 12 shows the number of
tetrahedrons and simulation time required for simulation
of all four cases. Number of tetrahedrons and simulation
time increases with roughness. Ones the solution is con-
verged, the RAM usage, matrix size and number of tetra-
hedrons remains constant. It is clear from Figures 11 and
12, that computational complexity, power and simulation
time increase with increase in extent of roughness.
VI. CONCLUSION
In this paper, we have presented a novel analytical model to
calculate resistivity and mean free path for on-chip copper
interconnects with rough surfaces. Our analytical results are
compared with data using industry standard EM solver as
well as available literature that exhibit excellent accuracy.
Based on our models, we highlight the effect of surface
roughness on local resistivity, effective resistivity, line resis-
tance and mean free path. Our results show that the effect of
surface roughness is much severe for lower technology
nodes. We also compare the computational complexity in
term of mesh sizing and current density, which increase with
extent of roughness. We present the computation overhead
i.e., time, matrix size, number of tetrahedrons and memory
required for simulation of rough interconnect structures.
To best of our knowledge, such an analysis has not been
reported in the available literature. The authors feel that accu-
rate performance benchmarking for planar interconnects can
be done using our models. Planar Cu interconnects form the
backbone of data and clock transmission in both 2D and 3D
chips and interposers. It is felt that our proposed model
would aid designers in accurately estimating interconnect
performance for these applications.
ACKNOWLEDGMENTS
This work was supported by the Department of Science and
Technology, Government of India (No. SB/FTP/ETA-40/
2013). The author would also like to thank Mr. Atul Kumar
Nishad for his valuable comments and suggestions. This
work is supported in part by the Department of Science and
Technology, Government of India under Grant No. SB/FTP/
ETA-40/2013.
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