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Chapter 4 - Global and Detailed Placement PDF
Chapter 4 - Global and Detailed Placement PDF
Original Authors:
Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 1
Chapter 4 – Global and Detailed Placement
© KLMH
4.1 Introduction
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 2
4.1 Introduction
© KLMH
System Specification
Partitioning
Architectural Design
ENTITY test is
port a: in bit;
end ENTITY test;
Functional Design Chip Planning
and Logic Design
Physical Design
Clock Tree Synthesis
Physical Verification
DRC and Signoff
LVS Signal Routing
ERC
Fabrication
Timing Closure
Chip
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 3
4.1 Introduction
© KLMH
a Linear Placement
c
b
g h a c b g h d f e
d
f
e
VDD
h e d a
h e d a
GND
g f c b
g f c b
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 4
4.1 Introduction
© KLMH
Global Detailed
Placement Placement
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 5
4.2 Optimization Objectives
© KLMH
Total Number of Wire Signal
Wirelength Cut Nets Congestion Delay
© KLMH
e h a k f h
j
i d c e
c l
f l i
b
b j
k g a g
d
© KLMH
Wirelength estimation for a given placement
Sait, S. M., Youssef, H.: VLSI Physical Design Automation, World Scientific
(HPWL) (clique)
4
8
5
5 3 6 3 8
3 6
3 3
4 4
HPWL = 9 Clique Length = Chain Length = 12 Star Length = 15
(2/p)e cliquedM(e) = 14.5
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 8
4.2 Optimization Objectives – Total Wirelength
© KLMH
Wirelength estimation for a given placement (cont‘d.)
Sait, S. M., Youssef, H.: VLSI Physical Design Automation, World Scientific
spanning minimum arborescence tree (STST)
tree (RMST) tree (RSMT) model (RSA)
5 3
3 6 4
+5
1 1
3 2
3 3 +2
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 9
4.2 Optimization Objectives – Total Wirelength
© KLMH
Wirelength estimation for a given placement (cont‘d.)
6 h 5 LHPWL w h
1
3 w
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 10
4.2 Optimization Objectives – Total Wirelength
© KLMH
Total wirelength with net weights (weighted wirelength)
L( P ) w(net ) L(net )
netP
where w(net) is the weight of net, and L(net) is the estimated wirelength of net.
a1 c
Example: a
c1
Nets Weights d1
N1 = (a1, b1, d2) w(N1) = 2 d f1 f
N2 = (c1, d1, f1) w(N2) = 4 d2
f2
N3 = (e1, f2) w(N3) = 1
b
b1 e1
e
L( P ) w(net ) L(net ) 2 7 4 4 1 3 33
netP
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 11
4.2 Optimization Objectives – Number of Cut Nets
© KLMH
Cut sizes of a placement
L( P ) ψ
vV P
P (v ) ψ
hH P
P ( h)
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 12
4.2 Optimization Objectives – Number of Cut Nets
© KLMH
Cut sizes of a placement
Example:
Nets a1 c
a
N1 = (a1, b1, d2) c1
N2 = (c1, d1, f1) h2
d1
N3 = (e1, f2) d f1 f
d2
h1 f2
b
Cut values for each global cutline b1 e1
ψP(v1) = 1 ψP(v2) = 2 e
ψP(h1) = 3 ψP(h2) = 2 v1 v2
Total number of crossings in P
ψP(v1) + ψP(v2) + ψP(h1) + ψP(h2) = 1 + 2 + 3 + 2 = 8
Cut sizes
X(P) = max(ψP(v1),ψP(v2)) = max(1,2) = 2
Y(P) = max(ψP(h1),ψP(h2)) = max(3,2) = 3
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 13
4.2 Optimization Objectives – Wire Congestion
© KLMH
Routing congestion of a placement
Ratio of demand for routing tracks to the supply of available routing tracks
Estimated by the number of nets that pass through the boundaries of individual
routing regions
SB CH SB CH
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 14
4.2 Optimization Objectives – Wire Congestion
© KLMH
Routing congestion of a placement
Formally, the local wire density φP(e) of an edge e between two neighboring
grid cells is
η P ( e)
φ P ( e)
σ P ( e)
where P(e) is the estimated number of nets that cross e and
σP(e) is the maximum number of nets that can cross e
If φP(e) > 1, then too many nets are estimated to cross e, making P more likely
to be unroutable.
The wire density of P is ( P) maxφ P (e)
eE
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 15
4.2 Optimization Objectives – Wire Congestion
© KLMH
Wire Density of a placement
v3 v6
c
ηP(h1) = 1 ηP(v1) = 1 a
ηP(h2) = 2 ηP(v2) = 0 h5
h4 h6
ηP(h3) = 0 ηP(v3) = 0
v2 d v5 f
ηP(h4) = 1 ηP(v4) = 0
ηP(h5) = 1 ηP(v5) = 2 h1 h3
b
ηP(h6) = 0 ηP(v6) = 0 h2
e
v1 v4
Maximum: ηP(e) = 2
η P (e) 2
( P) Routable
σ P (e) 3
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 16
4.2 Optimization Objectives – Signal Delay
© KLMH
Circuit timing of a placement
Static timing analysis using actual arrival time (AAT) and required arrival time
(RAT)
AAT(v) represents the latest transition time at a given node v
measured from the beginning of the clock cycle
RAT(v) represents the time by which the latest transition at v must complete
in order for the circuit to operate correctly within a given clock cycle.
For correct operation of the chip with respect to setup (maximum path delay)
constraints, it is required that AAT(v) ≤ RAT(v).
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 17
Global Placement
© KLMH
4.1 Introduction
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 18
Global Placement
© KLMH
Partitioning-based algorithms:
The netlist and the layout are divided into smaller sub-netlists and sub-regions,
respectively
Process is repeated until each sub-netlist and sub-region is small enough
to be handled optimally
Detailed placement often performed by optimal solvers, facilitating a natural
transition from global placement to detailed placement
Example: min-cut placement
Analytic techniques:
Model the placement problem using an objective (cost) function,
which can be optimized via numerical analysis
Examples: quadratic placement and force-directed placement
Stochastic algorithms:
Randomized moves that allow hill-climbing are used to optimize the cost
function
Example: simulated annealing
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 19
Global Placement
© KLMH
Partitioning-based Analytic Stochastic
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 20
4.3.1 Min-Cut Placement
© KLMH
Uses partitioning algorithms to divide (1) the netlist and (2) the layout region
into smaller sub-netlists and sub-regions
Conceptually, each sub-region is assigned a portion of the original netlist
Each cut heuristically minimizes the number of cut nets using, for example,
Kernighan-Lin (KL) algorithm
Fiduccia-Mattheyses (FM) algorithm
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 21
4.3.1 Min-Cut Placement
© KLMH
Alternating cutline directions Repeating cutline directions
2a
4a 4c 4a 3a 4e
3a 3b 2a
4b 4d 4b 3b 4f
1 1
4e 4g 4c 3c 4g
3c 3d 2b
4f 4h 4d 3d 4h
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 22
4.3.1 Min-Cut Placement
© KLMH
Input: netlist Netlist, layout area LA, minimum number of cells per region cells_min
Output: placement P
P=Ø
regions = ASSIGN(Netlist,LA) // assign netlist to layout area
while (regions != Ø) // while regions still not placed
region = FIRST_ELEMENT(regions) // first element in regions
REMOVE(regions, region) // remove first element of regions
if (region contains more than cell_min cells)
(sr1,sr2) = BISECT(region) // divide region into two subregions
// sr1 and sr2, obtaining the sub-
// netlists and sub-areas
ADD_TO_END(regions,sr1) // add sr1 to the end of regions
ADD_TO_END(regions,sr2) // add sr2 to the end of regions
else
PLACE(region) // place region
ADD(P,region) // add region to P
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 23
4.3.1 Min-Cut Placement – Example
© KLMH
Given: cut1
1
4
2
5 6
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 24
4.3.1cut1 Min-Cut-Platzierung: Beispiel
1
4
© KLMH
2
5 6
3
1 4 1 4 5
2 5 2 3 6
3 6 0 0
0 0 KL Algorithm
cut1 cut1
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 25
1 4 5
© KLMH
2 3 6
0 0
cut1
Horizontal cut cut2L: T={1,4}, B={2,0} Horizontal cut cut2R: T={3,5}, B={6,0}
1 4 3 5
cut2L cut2R
2 0 0 6
cut3TL cut3TR 1 4 5 3
1 4 5 3
0 2 6 0
cut3BL cut3BR 2 6
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 26
4.3.1 Min-Cut Placement – Terminal Propagation
© KLMH
TR
2
2 2 3 3
4
3
1 1 4 1 4
BR
Terminal Propagation
External connections are represented by artificial connection points
on the cutline
Dummy nodes in hypergraphs
x TR
p‘ 2 4
2 2 4
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 27
4.3.1 Min-Cut Placement
© KLMH
Advantages:
Reasonably fast
Objective function can be adjusted, e.g., to perform timing-driven placement
Hierarchical strategy applicable to large circuits
Disadvantages:
Randomized, chaotic algorithms – small changes in input lead to large changes
in output
Optimizing one cutline at a time may result in routing congestion elsewhere
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 28
4.3.2 Analytic Placement – Quadratic Placement
© KLMH
Objective function is quadratic; sum of (weighted) squared Euclidean distance
represents placement objective function
L( P )
1 n
2 i , j 1
cij xi x j 2
yi y j 2
where n is the total number of cells, and c(i,j) is the connection cost between cells i and j.
Only two-point-connections
Minimize objective function by equating its derivative to zero
which reduces to solving a system of linear equations
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 29
4.3.2 Analytic Placement – Quadratic Placement
© KLMH
Similar to Least-Mean-Square Method (root mean square)
Build error function with analytic form: E ( a, b) i
a x b y i 2
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 30
4.3.2 Analytic Placement – Quadratic Placement
© KLMH
L( P )
1 n
2 i , j 1
cij xi x j 2
yi y j 2
where n is the total number of cells, and c(i,j) is the connection cost between cells i and j.
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 31
4.3.2 Analytic Placement – Quadratic Placement
© KLMH
L( P )
1 n
2 i , j 1
cij xi x j 2
yi y j 2
where n is the total number of cells, and c(i,j) is the connection cost between cells i and j.
Lx ( P) L y ( P )
AX bx 0 AY b y 0
X Y
where A is a matrix with A[i][j] = -c(i,j) when i ≠ j,
and A[i][i] = the sum of incident connection weights of cell i.
X is a vector of all the x-coordinates of the non-fixed cells, and bx is a vector
with bx[i] = the sum of x-coordinates of all fixed cells attached to i.
Y is a vector of all the y-coordinates of the non-fixed cells, and by is a vector
with by[i] = the sum of y-coordinates of all fixed cells attached to i.
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 32
4.3.2 Analytic Placement – Quadratic Placement
© KLMH
L( P )
1 n
2 i , j 1
cij xi x j 2
yi y j 2
where n is the total number of cells, and c(i,j) is the connection cost between cells i and j.
Lx ( P) L y ( P )
AX bx 0 AY b y 0
X Y
System of linear equations for which iterative numerical methods can be used
to find a solution
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 33
4.3.2 Analytic Placement – Quadratic Placement
© KLMH
Mechanical analogy: mass-spring system
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 34
4.3.2 Analytic Placement – Quadratic Placement
© KLMH
Second stage of quadratic placers: cells are spread out to remove overlaps
Methods:
Adding fake nets that pull cells away from dense regions toward anchors
Geometric sorting and scaling
Repulsion forces, etc.
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 35
4.3.2 Analytic Placement – Quadratic Placement
© KLMH
Advantages:
Captures the placement problem concisely in mathematical terms
Leverages efficient algorithms from numerical analysis and available software
Can be applied to large circuits without netlist clustering (flat)
Stability: small changes in the input do not lead to large changes in the output
Disadvantages:
Connections to fixed objects are necessary: I/O pads, pins of fixed macros, etc.
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 36
4.3.2 Analytic Placement – Force-directed Placement
© KLMH
Cells and wires are modeled using the mechanical analogy of a mass-spring
system, i.e., masses connected to Hooke’s-Law springs
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 37
4.3.2 Analytic Placement – Force-directed Placement
© KLMH
Given two connected cells a and b, the attraction force Fab exerted on a by b is
Fab c(a, b) (b a )
where
c(a,b) is the connection weight (priority) between cells a and b, and
(b a ) is the vector difference of the positions of a and b in the Euclidean plane
Fi F
c (i , j ) 0
ij
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 38
4.3.2 Analytic Placement – Force-directed Placement
© KLMH
Zero-Force-Target (ZFT) position of cell i
a
i
d b
ZFT Position c
© KLMH
Basic force-directed placement
c(i, j ) ( x 0j xi0 ) 0
c (i , j ) 0
c(i, j ) ( y 0j yi0 ) 0
c (i , j ) 0
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 40
4.3.2 Analytic Placement – Force-directed Placement
© KLMH
Example: ZFT position
Given:
Circuit with NAND gate 1 and four I/O pads on a 3 x 3 grid
Pad positions: In1 (2,2), In2 (0,2), In3 (0,0), Out (2,0)
Weighted connections: c(a,In1) = 8, c(a,In2) = 10, c(a,In3) = 2, c(a,Out) = 2
Task: find the ZFT position of cell a
In2 In1
In1
2
In2 1 Out
1
In3
In3 Out
0 1 2
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 41
4.3.2 Analytic Placement – Force-directed Placement
© KLMH
Example: ZFT position
Given:
Circuit with NAND gate 1 and four I/O pads on a 3 x 3 grid
Pad positions: In1 (2,2), In2 (0,2), In3 (0,0), Out (2,0)
Solution:
c(a, j) x
c(i, j ) 0
0
j
c(a, In1) xIn1 c(a, In2) xIn2 c(a, In3) xIn3 c(a, Out) xOut 8 2 10 0 2 0 2 2 20
xa0 0.9
c(a, j)
c(i, j ) 0
c(a, In1) c(a, In2) c(a, In3) c(a, Out) 8 10 2 2 22
c(a, j) y
c ( i , j ) 0
0
j
c(a, In1) yIn1 c(a, In2) yIn2 c(a, In3) yIn3 c(a, Out) yOut 8 2 10 2 2 0 2 0 36
ya0 1.6
c(a, j)
c ( i , j ) 0
c(a, In1) c(a, In2) c(a, In3) c(a, Out) 8 10 2 2 22
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 42
4.3.2 Analytic Placement – Force-directed Placement
© KLMH
Example: ZFT position
Given:
Circuit with NAND gate 1 and four I/O pads on a 3 x 3 grid
Pad positions: In1 (2,2), In2 (0,2), In3 (0,0), Out (2,0)
Solution:
In2 a In1
In3 Out
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 43
4.3.2 Analytic Placement – Force-directed Placement
© KLMH
Input: set of all cells V
Output: placement P
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 44
4.3.2 Analytic Placement – Force-directed Placement
© KLMH
Finding a valid location for a cell with an occupied ZFT position
(p: incoming cell, q: cell in p‘s ZFT position)
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 45
4.3.2 Analytic Placement – Force-directed Placement (Example)
© KLMH
Given:
Nets Weight
N1 = (b1, b3) c(N1) = 2 b1 b2 b3
N2 = (b2, b3) c(N2) = 1
0 1 2
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 46
4.3.2 Analytic Placement – Force-directed Placement (Example)
© KLMH
Given:
Nets Weight
N1 = (b1, b3) c(N1) = 2 b1 b2 b3
N2 = (b2, b3) c(N2) = 1
0 1 2
L(P)
Incoming ZFT position Cell q before L(P) / placement
cell p of cell p move after move
b3
c(b , j) x
c(b3 , j ) 0
3
0
j
2 0 1 1 b1 L(P) = 5 L(P) = 5 b33 b22 b11
xb0 0
3
c(b , j)
c(b3 , j ) 0
3
2 1
No swapping of b3 and b1
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 47
4.3.2 Analytic Placement – Force-directed Placement (Example)
© KLMH
Given:
Nets Weight
N1 = (b1, b3) c(N1) = 2 b1 b2 b3
N2 = (b2, b3) c(N2) = 1
0 1 2
L(P)
Incoming ZFT position Cell q before L(P) / placement
cell p of cell p move after move
b3
c(b , j) x
c(b3 , j ) 0
3
0
j
2 0 1 1 b1 L(P) = 5 L(P) = 5 b33 b22 b11
xb0 0
3
c(b , j)
c(b3 , j ) 0
3
2 1
No swapping of b3 and b1
c(b , j) x2
0
j
c (b2 , j ) 0 1 2
xb0 2
b2 2
c(b , j)
c (b2 , j ) 0
2
1 b3 L(P) = 5 L(P) = 3 b1 b3 b2
Swapping of b2 and b3
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 48
4.3.2 Analytic Placement – Force-directed Placement
© KLMH
Advantages:
Conceptually simple, easy to implement
Primarily intended for global placement, but can also be adapted to detailed
placement
Disadvantages:
Does not scale to large placement instances
Is not very effective in spreading cells in densest regions
Poor trade-off between solution quality and runtime
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 49
4.3.3 Simulated Annealing
© KLMH
Cost
Time
Analogous to the physical annealing process
Melt metal and then slowly cool it
Result: energy-minimal crystal structure
Modification of an initial configuration (placement) by moving/exchanging
of randomly selected cells
Accept the new placement if it improves the objective function
If no improvement: Move/exchange is accepted with temperature-dependent
(i.e., decreasing) probability
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 50
4.3.3 Simulated Annealing – Algorithm
© KLMH
Input: set of all cells V
Output: placement P
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 51
4.3.3 Simulated Annealing
© KLMH
Advantages:
Can find global optimum (given sufficient time)
Well-suited for detailed placement
Disadvantages:
Very slow
To achieve high-quality implementation, laborious parameter tuning is necessary
Randomized, chaotic algorithms - small changes in the input
lead to large changes in the output
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 52
4.3.3 Simulated Annealing
© KLMH
Cost
Time
Analogous to the physical annealing process
Melt metal and then slowly cool it
Result: energy-minimal crystal structure
Modification of an initial configuration (placement) by moving/exchanging
of randomly selected cells
Accept the new placement if it improves the objective function
If no improvement: Move/exchange is accepted with temperature-dependent
(i.e., decreasing) probability
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 53
4.3.4 Modern Placement Algorithms
© KLMH
Predominantly analytic algorithms
Solve two challenges: interconnect minimization and cell overlap removal
(spreading)
Two families:
Non-convex
Quadratic placers
optimization placers
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 54
4.3.4 Modern Placement Algorithms
© KLMH
Non-convex
Quadratic placers
optimization placers
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 55
4.3.4 Modern Placement Algorithms
© KLMH
Non-convex
Quadratic placers
optimization placers
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 56
4.3.4 Modern Placement Algorithms
© KLMH
Quadratic Non-convex
Placement optimization placers
© KLMH
4.1 Introduction
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 58
4.4 Legalization and Detailed Placement
© KLMH
Global placement must be legalized
Cell locations typically do not align with power rails
Small cell overlaps due to incremental changes, such as cell resizing or buffer
insertion
Legalization seeks to find legal, non-overlapping placements for all placeable
modules
Legalization can be improved by detailed placement techniques, such as
Swapping neighboring cells to reduce wirelength
Sliding cells to unused space
Software implementations of legalization and detailed placement are often
bundled
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 59
4.4 Legalization and Detailed Placement
© KLMH
Legal positions of standard cells between VDD and GND rails
Power
Rail Standard Cell Row
VDD
GND
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 60
Summary of Chapter 4 – Problem Formulation and Objectives
© KLMH
Row-based standard-cell placement
Cell heights are typically fixed, to fit in rows (but some cells may have double
and quadruple heights)
Legal cell sites facilitate the alignment of routing tracks, connection to power
and ground rails
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 61
Summary of Chapter 4 – Global Placement
© KLMH
Combinatorial optimization techniques: min-cut and simulated annealing
Can perform both global and detailed placement
Reasonably good at small to medium scales
SA is very slow, but can handle a greater variety of constraints
Randomized and chaotic algorithms – small changes at the input can lead
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 62
Summary of Chapter 4 – Legalization and Detailed Placement
© KLMH
Legalization ensures that design rules & constraints are satisfied
All cells are in rows
Cells align with routing tracks
Cells connect to power & ground rails
Additional constraints are often considered, e.g., maximum cell density
Lienig
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 4: Global and Detailed Placement 63