Digital Assignment –I

1. Consider two identical Common Emitter amplifiers are connected in cascade. The
first stage is fed with a source voltage Vsig having a resistance Rsig = 10kΩ. A load
resistance RL = 10kΩ is connected to the collector of the second stage. Each BJT is
biased at IC = 0.25mA and has β = 100 and a very large VA. Each stage utilizes a
collector resistance RC = 10kΩ.

(a) Sketch the equivalent circuit of the two -stage amplifier.

(b) Calculate the voltage transmission from the signal source to the input of the first
stage.
(c) Calculate the voltage gain of the first stage, AV1.
(d) Calculate the voltage gain of the second stage, AV2.
(e) Find the overall voltage gain, Vo2/Vsig.
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2. For the amplifier shown in Fig.B., whose component values are: R1 = 33 kΩ, R2 = 22 kΩ,
RE = 3.9 kΩ, RC = 4.7 kΩ, Rsig = 5 kΩ, RL = 3.6 kΩ, VCC = 5V, β0 =120, ro = 300 kΩ, and
rx = 50Ω. Design the coupling and bypass capacitors for a lower 3-dB frequency of 100
Hz. Design so that the contribution of each of CC1 and CC2 in determining fL is only 5%.
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3. Consider the CE amplifier shown in Fig.B. under the following conditions: R1 = 33
kΩ, R2 = 22 kΩ, RE = 3.9 kΩ, RC = 4.7 kΩ, Rsig = 5 kΩ, RL = 3.6 kΩ, VCC = 5V.
The dc emitter current can be shown to be IE = 0.3mA, at which β0 =120, ro = 300
kΩ and rx = 50Ω. Find the input resistance Rin and the midband gain. If the transistor
is specified to have fT = 700 MHz and Cμ = 1pF, find the upper 3-dB frequency.

4. Consider the low frequency response of the CS amplifier shown in Fig.(a). Let RG =
2 MΩ, RD = 20 kΩ, Rsig = 0.5 MΩ, RL = 10 kΩ, and gm = 3mA/V. Find AM. Also
design the coupling and bypass capacitors to locate the three low frequency poles at
50 Hz, 3Hz and 10Hz. Calculate the fL value?

Fig.(a).

5. Consider the following MOSFET amplifier in Fig.(a). Given Rsig = 100 kΩ, Rin =
100 kΩ, Cgs = 1pF, Cgd = 0.2pF, gm = 3mA/V, ro = 50 kΩ, RD = 8kΩ and RL =
10kΩ. Determine the expected 3-dB upper cut-off frequency fH and the midband
gain.