Computer Science 327 11/02/20

MIPS Processor using Verilog

Project Description:
For this semester long project my partner, Morgan Funk, and I developed a working
software MIPS processor using VHDL code. This project had several stages throughout the
semester. First, we constructed an arithmetic logic unit or ALU which would be used in our
processor to process MIPS commands. It was able to add, subtract, shift, logical and, or, xor, nor,
and more. For the second part of the project we implemented a single-cycle processor that could
run instructions like add, addu, xor, slt, sll, srl, and many other MIPS-like commands. This
processor used a register file, ALU, and memory to run commands in a single cycle
implementation. For the third part of the project we modified the processor to make it a pipelined
processor without hazard detection. This processor needed NoOp instructions in the code to be
able to run correctly before we had our hazard detection for the last part of the project. Our final
processor was pipelined, with hazard detection and forwarding capabilities.

My Contribution:
Morgan and I worked incredibly long hours in the lab on this project (almost 70 hours for
the final part in a 4 week period on top of our other classes). It was the most time consuming
project I’ve had here at Iowa State and to be completely honest it was not a good time. Morgan
and I worked side by side for probably 90% of the work on this project as we brainstormed and
figured out the various parts to get the processor working. Our final high-level schematic of our
signals and modules we created is shown below. Morgan and I split work when we could to have
each person creating an equal number of modules for the processor. For instance, he worked on
the control unit and I created the forwarding unit. We wrote all of our own testing using
commands we created for our processor based on the MIPS assembly language.

Knowledge Gained:
I learned a lot during this process of creating our processor; everything from how
individual registers are used in the overall memory to the difference between a single cycle
processor and a pipelined processor to creating all the components for the ALU. I learned a lot
about multiplexers and how hazard detection works in foreseeing errors in the instructions and
forwarding when necessary. I learned how to read the signal outputs from ModelSim very well to
debug our processor, and how hard this becomes once the processor starts to get larger and larger
(one such signal output is shown below).
Supporting Documents:

High-level schematic:

Signal output showing the registers can be stalled and flushed: