0

1
Ch. 1 Semiconductors 8
1-1 Introduction 9
1-2 Energy Bands for Solids 10
Conduction band 11
Valence band: 11
1-2-1 Conductor Energy Bands 12
1-2-2 Insulator Energy Bands 13
1-2-3 Semiconductor Energy Bands 14
1.3 Intrinsic semiconductors: 15
1.4 Extrinsic semiconductor 17
1.5 Direct and indirect band gap in semiconductors: 18
1.6 Drift current and conductivity 20
1.7 Statistical Distribution of the electron energy: 21
1.8 Intrinsic carrier concentrations: 24
1.9 Energy Bands for intrinsic semiconductor 26
1.10 Atomic structure of Silicon and Germanium 27
1.10.1 Covalent Bond in Silicon and Germanium 27
1.11 Impurity Semiconductors 30
1.11.1 n-type semiconductor 31
1.11.2 p-type semiconductor 32
1.12 Electron and hole Densities in Each Type: 34
Carrier density at a given level in n-type semiconductor:
1.13 Thermistor 38
1.14 Hall effect 39
Objective type questions 43

Ch.2 p-n Junction Semiconductor diodes 49

2-1 Introduction 50
2-2 p-n Junction Formation 50
2.3 diffusion and drift 50
2.4 Built-in potentials and Energy band in pn junction 53
2.5 Semiconductor Diode 56
2.5.1 p-n junction diode under forward bias 57
2.5.2 P-N Junction Energy Bands at equilibrium 59
2.5.3 Energy Bands of p-n junction at forward bias 59
2 .6 p-n junction diode under reverse bias 62
2.6.1 Energy Bands of p-n junction at reverse bias 64
2.6.2 Relations for Energy Bands in semiconductor Diode 66
2.7 Current components of semiconductor diode 69
2.8 Characteristics of of semiconductor diode 71
2.9 Temperatur Effect 73

2
2.10 Diode Resistance and Ideal Diode 74
2.11 Transition an Diffusion capacitance 76
2.12 Load Line Analysis 78
2.13 Other Types of Diodes 82
2.13.1 Varicap/Varactor diode 83
2.13.2 Zener Diode (Zener Effect – Zener breakdown) 85
(1)Avalanch Effect 85
(2) Zener Effect 85
(3) Zener diode as a voltage regulator 87
2.13.3 Tunnel Diodes 89
2.13.4 Schottky Barrier (Hot-carrier) Diodes 90
2.13.5 Gunn Diode 94
(1)Introduction: 94
(2) Gunn Oscillators 95
(3) The First mode is: transit time mode: 97
(4) Limited –space charge accumulation (LSA) mode 97
(5) Quenched –domain mode 98
(6) Delayed(inhibited) mode 99
2.13.6 Photodiode 100
2.13.7 Light emitting diode (LED) 102
2.13.8 Solar cell 103
2.14 Sinusoidal Inputs; Half –Wave Rectifier 106
2.15 Full –Wave Rectification 111
2.15.1 Bridge Network 111
2.15.2 Center-Tapped Transformer 114
2.15.3 Full Wave Rectifier with Capavcitive Filtering 118
2.16 Clamping Circuits 119
2.16.1 Diode clampers 120
(1) Positive Clamper 120
(2) Positive clamper with bias 121
(3) Negative Clamber 122
(4) Negative Clamper With bias 122
2.17 Clipping Circuits 123
2.17.1 Classifications Of Clippers 124
2.17.2 Positive Clipper and Negative Clipper 125
(1) Positive Diode Clipper 125
(2) Negative Diode Clipper 127
2.17.3 Biased Positive Clipper and Biased Negative Clipper 130
2.17.4 Combination Clipper 131
Drawbacks of Series and Shunt Diode Clippers 132

3
Ch.3 Bipolar Junction Transistors (BJT) 133
3.1 Introduction 134
3.2 Transistor Construction 134
3.3 Transistor Operation 136
3.3.1 Active mode 137
Some details 137
3.3.2 Charge Concentration; 139
3.3.3 Current Components 142
3.4 Basic transistor circuit configurations and transistor
Characteristics 145
3.4.1 Common base transistor characteristics (C.B) 146
3.4.2 Common Collector transistor characteristics(C.C) 147
3.4.3 Common emitter transistor characteristics 148
3.4.4 Early Effect 151
3.4.5 Cut-off mode 152
3.4.6 Saturation mode 152
(i)Input resistance (ri): 153
(ii) Output resistance (ro): 153
(iii) Current amplification factor (β ): 154
3.5 Transistor Switches 155
3.6 Transistor amplifiers 156
Gain and Amplification 156
3.7 Biasing and classification of Transistor Amplifier 157
3.7.1 DC Biasing of BJTs: 158
3.7.2 Operating Point 160
3.7.3 Fixed –Bias Circuit 162
3.8 Load-Line Analysis 166
QUESTIONS Questions 172

Ch.4. FET and MOSFETs Transistors 177

4-1 Introduction 178
4.2 Construction and Characteristics of JFETs 180
4.2.1 Symbols 180
4.2.2 Construction 180
4.2.3 Characteristics: 182
4.2.4 Pinch-Off 184
4.3 Current –voltage characteristics 187
4.3.1 Nonsaturation (or Triode) Region: 188
4.3.2 Saturation Region: 188
4.4 When :VGS < 0 V : 189
4.4.1 Voltage-Controlled Resistor 191
4.5 p-Channel Devices 192
4
4.6 Transfer Characteristics 195
4.7 Circuit Configurations for FET 198
4.8 Important Relationships (Analogy between JFET and
BJT): 198
4.9 Thermal Effect 199
4.10 The Metal Oxide Semiconductor Transistor (MOSFET) 200
4.11 The MOS Capacitor 201
4.12 n- Channel Enhanced-Mode MOSFET 205
4.12.1 Basic Construction 205
4.12.2 Basic Operation 208
4.13 Characteristics of Enhanced-Mode MOSFET: 209
4.14 Depletion Type MOSFET 214
4.14.1 Basic Construction 215
4.14.2 Basic Operation and Characteristics 216
4.15 p-Channel Depletion-Type MOSFET 221
4.15.1 Symbols 221
4.16 Biasing the NMOS Field-Effect Transistor 222
4.17 Load Line Analysis 226

Ch.5 Operational Amplifier OP-AMP 229

5-1 Introduction 230
5.2. Symbols and Schematic 231
5.3 Various input and output Forms 232
5.3.1 Single-Ended Input 233
5.3.2 Double-Ended (Differential) Input 234
5.3.3 Double-Ended Output 235
5.4. Kirchhoff‘s Current Law applied to Op-amps 237
5.5 . Input/output Impedance 239
5.6 Common-Mode Operation and Common-Mode Rejection 240
5.6.1 Common-Mode Rejection 240
5.7 Differential and Common Mode Operation 241
5.7.1 Differential Inputs 241
5.7.2 Common Inputs 241
5.7.3 Output Voltage 241
5.7.4 Opposite Polarity Inputs 242
5.7.5 Same Polarity Inputs 242
5.7.6 Common-Mode Rejection 242
5.7.7.Common-Mode Rejection Ratio 243
5.8 Operational Amplifier (Op-Amp) Basics 246
5.8.1 Basic Op-Amp 247
5.8.2 Unity Gain 248
5.8.3 Constant Magnitude Gain 248
5
5.8.4 Virtual Ground 249
5.9 Practical OP-AMP Circuits 250
5.9.1 Inverting Amplifier 250
5.9.2 Noninverting Amplifier 252
5.9.3 Summing Amplifier 254
5.9.4 Integrator 257
5.9.5 Differentiator 262
5.10 OP-AMP Specifications—DC OFFSET Parameters 262
5.10.1 Offset Currents and Voltages 262
5.10.2 Input OFFSET Voltage, VIO 263
5.10.3 Output Offset Voltage Due To Input Offset Current, IIO 265
5.10.4 Total OFFSET Due To VIO and IIO 267

Ch. 6 .Digital Electronics 270

6.1 Analogue Versus Digital 271
6.2 Introduction to Number Systems 272
6.3 Decimal Number System 272
6.4 Binary Number System 273
6.4.1 Advantages 274
6.5 Octal Number System 275
6.6 Hexadecimal Number System 275
6.7 Finding the Decimal Equivalent 276
6. 7.1 Binary-to-Decimal Conversion 276
(1)Addition rule in binary system: 277
(2)subtraction rule in binary system 277
6.7.2 Octal-to-Decimal Conversion 277
6.7.3 Hexadecimal-to-Decimal Conversion 277
6.8 Decimal-to-Binary Conversion 278
6.9 Decimal-to-Octal Conversion 280
6.10 Decimal-to-Hexadecimal Conversion 281
6.11 Binary–Octal and Octal–Binary Conversions 281
6.12 Hex–Binary and Binary–Hex Conversions 282
6.13 Hex–Octal and Octal–Hex Conversions 284
6.14. Introduction to Boolean Algebra 284
6.14.1 Variables, Literals and Terms in Boolean Expressions 286
6.14.2 Equivalent and Complement of Boolean Expressions 286
6.14.3 Dual of a Boolean Expression 287
6.15 Postulates of Boolean Algebra 288
6.16Theorems of Boolean Algebra 288
6.17 Logic Gates 291
6.17.1 OR Gate 291
6.17.2 AND Gate 293
6
6.17.3 NOT Gate 295
6.17.4 EXCLUSIVE-OR Gate 296
6.17.5 NAND Gate 297
6.17.6 NOR Gate 298
6.17.7 EXCLUSIVE-NOR Gate Solved Examples 298
6.18 Minimization by Karnaugh Maps 305
6.18.1 Filling out a Karnaugh Map 306
6.19. Flip-Flop and Introductory Sequential Logic 310
6.19.1 Simple Latches 310
6.19.2 Clocked Flip-flops 312
6.19.3 J-K Flip-Flop (contains Master–Slave Flip-Flops) 315
6.19.4 Toggle Flip-Flop (T Flip-Flop) 317
6.20 Counters and Registers 318
6.20.1 Ripple (Asynchronous) Counter 318
6.20.2 Synchronous Counter 319
6.20.3 Binary Ripple Counter – Operational Basics 319
6.20.4 Synchronous (or Parallel) Counters 322
6.20.5 UP/DOWN Counters 325
6.21 Shift Register 327
6.21.1 Serial-In Serial-Out Shift Register 328
6.21.2 Serial-In Parallel-Out Shift Register 330
6.21.3 Parallel-In Serial-Out Shift Register 332
6.21.4 Parallel-In Parallel-Out Shift Register 332
6.21.5 Bidirectional Shift Register 332
6.21.6 Universal Shift Register 336
6.22 Memories and Processors 336
6.22.1 Memory Terminology 336
6.22.2 Memory Configuration 337
6.22.3 Generalization to Microprocessors 338

References 341

7
Semiconductors

Ch. 1

Semiconductors

8
 Semiconductors

1-3 Introduction
The atom consists of a positively charged nucleus (a proton) and
electrons rotate around the nucleus. The charge on the proton is
positive and equal in magnitude to the charge on the electron.
Therefore the atom as a whole is electrically neutral . The atom
electrical properties (differ according to the material type) depend
on the attraction forces between nucleus and the valence electrons
(electrons in the outer orbit) or depend on the distribution of
energy bands and wide of gaps between these bands. So ,
materials can be classified according to electric conductivity to
three types:

1- Conductors : they permit flow of electric current . For

conductors , it is easy to release their valence electrons.
Examples : cupper , silver , gold ,….etc

2- Insulators: Such materials do not permit flow of electric

current. Examples of insulators: wood , plastics ,…etc.

3- Semiconductors: these materials are between the two last

types from point of view of electric conductivity.

Examples : Silicon , Germanium and some chemical

Compounds.

Semiconductor technique ,sometimes called solid state because

conduction takes place in solid materials and not in gas and liquid states
(see figure 1-1)

9
 Fig. 1-1 Material three cases : solid , liquid and gas

Anyone can ask question: how can charges transfer through solid body?
Shortly answering it is better to imagine the world structure for atom
where electrons rotate at very large interdistance ( with respect to their
volume) around the nucleus. This is very similar word structure. This
means that the solid body is not pure solid where it contains many
spaces.

1-4 Energy Bands for Solids

A useful way to visualize the difference between conductors, insulators

and semiconductors is to plot the available energies for electrons in the
materials. Instead of having discrete energies as in the case of free atoms,
the available energy states form bands. Crucial to the conduction process
is whether or not there are electrons in the conduction band. In insulators
the electrons in the valence band are separated by a large gap from the
conduction band, in conductors like metals the valence band overlaps the
conduction band, and in semiconductors there is a small enough gap
between the valence and conduction bands that thermal or other
excitations can bridge the gap. With such a small gap, the presence of a
small percentage of a doping material can increase conductivity
dramatically.

Question: Define conduction band and valence band ?

Answer:

10
Conduction band:

The conduction band in the range of electron energy, higher than that of
the valence band, sufficient to make the electrons free to accelerate under
the influence of an applied electric field and thus constitutes an electric
current. Semiconductors may cross this conduction band when they are
excited.

Valence band:

The valence band is the highest range of electron energies where

electrons are normally present absolute zero. In semiconductors and
insulators, there is a band gap above the valence band, followed by
conduction band above that. In metals, the conduction band has no energy
gap separating it from the valence band. Semiconductors and insulators
owe their high conductivity to the properties of the balance band in those
materials. It just so happens that the number of electrons is precisely
equal to the number of states available up to the top of the valence band.
There are no available states in the band gap. This means that when an
electric field is applied , the electrons can not increase their energy
because there are no states available to the electrons where they would be
moving faster than they are already going. There is some conductivity in
insulators, however this is due to thermal excitation of some of the
electrons get enough energy to jump the
band gap in one go. Once they are in the conduction band, they can
conduct electricity, as the hole they left behind in the valence band. The
hole is an empty state that allows electrons in the valence band some
degree of freedom.

Figure 1-2 show the energy bands in solids. An important parameter in

the band theory is the Fermi level, the top of the available electron energy
levels at low temperatures. The position of the Fermi level with the
relation to the conduction band is a crucial factor in determining electrical
properties.

11
 Fig. 1-2 Energy bands in solids.

If the electron gains energy it transport to the higher energy level and if it
transferred to a lower energy level it lose energy in the form of photons
which is given by the following equation:

f = E/h

Where f is the frequency , E is the difference of the energy between the

two levels , h is Blanks constant :

h= 6.626 x 10-34 J-sec

1-2-1 Conductor Energy Bands

In terms of the band theory of solids, metals are unique as good

conductors of electricity. This can be seen to be a result of their valence
electrons being essentially free. In the band theory, this is depicted as an
overlap of the valence band and the conduction band so that at least a
fraction of the valence electrons can move through the material. Figure 1-
3 show the conductor energy bands.

12
 Figure 1-3 conductor energy bands.

1-2-2 Insulator Energy Bands

Most solid substances are insulators, and in terms of the band theory of
solids this implies that there is a large forbidden gap between the
energies of the valence electrons and the energy at which the electrons
can move freely through the material (the conduction band).

Glass is an insulating material which may be transparent to visible light

for reasons closely correlated with its nature as an electrical insulator.
The visible light photons do not have enough quantum energy to bridge
the band gap and get the electrons up to an available energy level in the
conduction band. The visible properties of glass can also give some
insight into the effects of "doping" on the properties of solids. A very
small percentage of impurity atoms in the glass can give it color by
providing specific available energy levels which absorb certain colors
of visible light. The ruby mineral (corundum) is aluminum oxide with a
small amount (about 0.05%) of chromium which gives it its
characteristic pink or red color by absorbing green and blue light.

While the doping of insulators can dramatically change their optical

properties, it is not enough to overcome the large band gap to make
them good conductors of electricity. However, the doping of
semiconductors has a much more dramatic effect on their electrical
conductivity and is the basis for solid state electronics. Figure 1-4
insulator energy bands.

13
Fig. 1-4 insulator energy bands.

1-2-3 Semiconductor Energy Bands

For intrinsic semiconductors like silicon and germanium, the Fermi level is essentially
halfway between the valence and conduction bands. Although no conduction occurs at
0 K, at higher temperatures a finite number of electrons can reach the conduction
band and provide some current. In doped semiconductors, extra energy levels are
added.

The increase in conductivity with temperature can be modeled in terms of the Fermi
function, which allows one to calculate the population of the conduction band. Fig.
1-5 semiconductor energy bands.

Fig. 1-5 semiconductor energy bands.

Question : What is intrinsic semiconductor and explain with the help of

energy band diagram as a function of temperature?
Answer:
14
Generally Semiconductors are mainly classified into two groups
1) Intrinsic semiconductor
2) Extrinsic semiconductor

1.3 Intrinsic semiconductors:

Intrinsic semiconductors are those in which impurities are not present and
therefore called pure semiconductors. In these semiconductors few crystal
defects may be present. Fermi level exists exactly at mid way of the
energy gap. When a semiconductor is taken at oK then it behaves as an
insulator and conduction occurs at higher temperature due to thermal
excitation f electrons from the valence band to the conduction band.
Examples: Germanium and Silicon. Figure 1-6 shows the intrinsic
semiconductors at T = 0 K and T > 0 K

Figure 1-6

15
When the energy band gap is sufficiently narrow, some of the electrons
occupying states at the top of the valence band may gain thermal energy
sufficient to transfer to empty states in conduction band and such
electrons can contribute to conductivity of the material. Because the
temperature, at which conductivity becomes appreciable, depends on the
crystal structure, such crystals are properly called intrinsic
semiconductor. The density of conduction electrons in a semiconductor
increases with temperature so that its conductivity also increases. The
Fermi level lies exactly at the middle between the conduction and valence
band in an intrinsic semiconductor ,EF = ½ (Ev + Ec) .
For intrinsic semiconductors at higher temperature continuous thermal
agitation exists, which results in the excitation of electrons from valence
band to conduction band and leaves an equal number of holes in the
valance band. The process is balanced by recombination of electrons in
the conduction band with holes in the valence band. At room temperature,
the intrinsic carrier density is small. Intrinsic carrier density increases
rapidly with temperature. At high temperature, thermal generation can be
dominant process of carrier generation. Because of this thermal effect, the
carrier concentration becomes equal to the background concentration at
the intrinsic temperature. Below intrinsic temperature, the carrier
concentration is relatively temperature independent. Above intrinsic
temperature, it rises exponentially with temperature.

16
 Fig. 1-7 structure of intrinsic silicon crystal

Example 1:

C, Si and Ge have same lattice structure. Why is C insulator while Si and

Ge intrinsic semiconductors?

Solution
The 4 bonding electrons of C, Si or Ge lie, respectively, in the second,
third and fourth orbit. Hence, energy required to take out an electron from
these atoms (i.e., ionisation energy Eg) will be least for Ge, followed by
Si and highest for C. Hence, number of free electrons for conduction in
Ge and Si are significant but negligibly small for C.

1.4 Extrinsic semiconductor

In real crystals, there always exist impurities or defects giving rise to
new energy levels in the band gap. Crystals usually contains some foreign
atoms, which may be present in interstitial or substitutional solid solution.
These atoms have valence electrons, which are bound to their nucleus by
force differing from those binding such electrons in the other atoms. In
terms of band model, this means that there are energy levels present in the
crystal which different in energy. If the electrons occupying this energy
level can contribute to conductivity in a crystal, then such a crystal is
called an extrinsic semiconductor. If the substitution impurity atoms
have five or more valence electrons, they are said to ―donate‖ excess of
electrons to the crystal. It increases the concentration of electrons in the

17
conduction band without generating any extra holes in the valence band.
Since the electron concentration is greater than hole concentration, the
former become the majority carrier. The energy of these levels is usually
somewhat less than the energy level at the bottom of the conduction band,
electrons being the majority carrier, it is called as n-type semiconductor. If the
impurity atoms have three or less valence electrons, they can ―accept‖
electrons. The energy level so called acceptor level is usually slightly higher
than the level at the top of valence band. An electron from the valence band can
be easily excited to this localized level leaving a hole in the valence band. This
itself does not generate any electron in the conduction band. The majority
carriers are holes. These types of extrinsic semiconductors are known as p-type
semiconductors. The band diagram of the different types of semiconductors is
shown in Fig.1-7.
When a semiconductor is doped with donor or acceptor impurities,
impurity energy levels are introduced. A donor level is defined as being
neutral if empty and negative if filled by an electron. The conductivity of
doped semiconductors is then much higher than that observed for intrinsic
semiconductor. The position of the Fermi level depends upon the relative
values of the effective masses of the electron and the hole. If effective mass of
electron is greater then effective mass of hole then, it move downwards, in the
contrary cases, it moves upwards.

Fig. 1-7 Band diagram for (a) n-type semiconductor and (b) p-type
semiconductor

Question: Write short notes on direct and indirect band gap

semiconductors?
Answer:

1.5 Direct and indirect band gap in semiconductors:

To observe electroluminescence it is necessary to select an appropriate
semiconductor material. The most useful materials for this purpose are

18
direct band gap semiconductors in which electrons and holes on either
side of the forbidden energy gap have the same value of crystal
momentum and thus direct recombination is possible. This process is
illustrated in Fig.1-8 with an energy band diagram for a direct band
gap semiconductor. It may be observed that the energy maximum of the
valence band occurs at the same value of electron crystal momentum as
the energy minimum of the conduction band. Hence electron-hole
recombination occurs, the momentum of the electron remains virtually
constant and the energy released, which corresponds to the bandgap
energy Eg, may be emitted as light. This direct transition of an electron
across the energy gap provides an efficient mechanism of photon
emission and the average time the minority carrier remains in agree state
before recombination. Some of the examples of direct band gap
semiconductors GaAs, Ge, InSb, GaSb etc.

Fig.1-8 Direct band gap in semiconductors

In direct band gap semiconductors are those where the maximum and
minimum energies occur at different values of crystal momentum (Fig.1-
9). For electron-hole pair recombination to take place it is essential that
the electron losses momentum such that it has a value of momentum
corresponding the maximum energy of valence band. The conservation of
momentum requires the emission or absorption of a third particle,
phonon. So, the recombination in indirect band gap semiconductors is
relatively. This is reflected by much longer minority carrier life time
together with a greater probability of nonradiative transitions. Some of
the examples are Si.

19
 Fig.1-9 Indirect band gap in semiconductors

1.6 Drift current and conductivity

When an constant external electric field ε is applied to the metal two
terminals , electrons gain acceleration toward the positive terminal
(reverse to the direction of the external field) and as a result of
interactions , electrons drift with rate of constant velocity called drift
speed V and is given by the following relation:

v=μ ε (1)

where μ is the electron mobility measured in square meter per volt

second.

Drift of electrons toward the positive terminal of the solid conductor

which contain the higher positive energy affect the conductor to achieve
current with direction (traditional) reverse the direction of electrons
motion. If N of electrons traverse a wire of length L and has cross-
section area A at a time t , so the current I value is given as follows:

I = N e/t (2)

Where e is the electron charge.

20
And the density of this current( distribution of the current on the cross-
section area) is given by the following relation:

J = I/A = N e/t A (3)

Substitute of t by the value L/V (velocity = distance/time), so:

J= Nev/LA (4)

The value LA in the relation 4 represent the wire volume that contains N
electrons , so:

J=nev (5)

Where n is the density of electrons. Substitute V from relation 1 to

relation 5 , we get:

J = n eμ ε
= σε (6)

Where :

σ =n e μ (7)

σ is called the metal conductivity and its units (Ω meter)-1. Conductivity

is the reverse of resistivity(Ω meter)-1(Ω meter) . relation 6 is the Ohm
law form which states that the conduction current is proportional to the
applied external voltage.

It is to be noted from relation 7 that conduction is proportional to the

density of free electrons n, and for the good conductors , this density is
very high (nearly 1028 electron/m3) while in insulators it equal (107
electron/m3) but in semiconductors its value is between these two values.

1.7 Statistical Distribution of the electron energy:

21
When the conductor temperature rises , its atoms randomly oscillate
around the their crystal structure. As a result, many of the electrons in
outer orbit (of the higher energy) gain additional energy that makes them
in free motion within the atomic structure. With such motion electrons
suffer from interactions with the oscillating atoms , and so they gain
energy or lose from their energy causing two enforcing results : the first
is the increasing in random motions and the other is the difficulty in
determination of electron energy at certain temperature and this makes
statistical solution is necessary for this situation.

Fermi-Dirac distribution function is suitable for the description of

distribution. Fermi-Dirac distribution is given as follows:

f(E) = 1/ {1+exp[(E – EF)/kT]} (8)

where k is the Boltzman constant

T is the temperature measured in absolute value(kelvin) ,

EF is Fermi level of energy or the characteristic energy and its value

depends on the chemical structure of the material and it is measured in
energy units.

For metals , the value of EF (measured in eV) can be determined using

the following relation:

EF = 3.64 x 10-19 n 2/3 (9)

Where n is the number of electrons in cubic meter(electrons density)

and generally , the value of EF is less than 10 eV for most metals.

The Fermi function or, more completely, the Fermi-Dirac distribution

function describes the occupancy of a electronic energy level in a system
of electrons at thermal equilibrium. The occupancy f(E) of an energy
level of energy E at an absolute temperature T in kelvins . This occupancy
function is plotted in the figure versus the energy E−EF in eV (electron
volts). In the second form of the function above, the energy is in eV (that
is, in the form E/q) and the temperature appears as the thermal voltage
kBT/q (approximately 25 mV at 290K). As temperature increases, so does

22
the thermal voltage, accounting for the stretching out of the function
along the energy axis with increasing temperature.

Notice that for an energy level with E = EF and a degeneracy factor g = 1

(see below for a discussion of g), the occupancy is 1/2 regardless of
temperature. The Fermi level EF thus can be referred to as the half-
occupancy level.

We note two important cases :

1-when E > EF this gives f(E) = 0 . This means that no probability for
electron to be exist in any energy level exceeds EF at the zero kelvin
temperature.

2- when E < EF this gives f(E) = 1 . This means that all energy levels less
than EF are occupied with electrons at the zero kelvin temperature.

So, the highest value can electron energy reaches at the zero kelvin
temperature is EF. Fig. 1- 10 displays the effect of temperature on the
distribution probability at room temperature besides two other degrees :
zero kelvin and 2500. Fig. 1-11 shows that all energy levels are filled
with electrons when E < EF .

Fig. 1- 10

23
 Fig. 1-11

1.8 Intrinsic carrier concentrations:

In intrinsic semiconductors, as the temperature is increased electron-hole
pairs will be generated. Hence the electron concentration, ni (Intrinsic
density ), in the conduction band will be equal to the hole concentration,
pi in the valence band(as a result of electrons leave to conduction band).

Generally , for intrinsic semiconductors:

np= ni2 (10)

when an electric field ε is applied to a semiconductor, the density of the

resultant electron current is given as follows:

Jn = n e μn ε (11)

The density of the resultant hole current is given as follows:

Jp = p e μp ε (12)

Where μn , μp are respectively the electron and hole mobility .The total
current density is given as follows:

J = Jn + Jp = ( n μn + p μp ) e ε (13)

24
From equation 6 above where :
J = σε
And comparing with equation 13 we the conductivity relation as follows:

σ = ( n μn + p μ p ) e (14)

for pure intrinsic semiconductor : n = p = ni , so the conductivity for pure

intrinsic semiconductor becomes:

σ = ( μn + μp ) n i e (15)

Example:
A piece of germanium with square cross-section , side length = 1 cm.
applying voltage 1.5 volts across its width . Find the current passing
through the piece knowing that:
-number of free electrons in m3 of germanium =2 x 10192 x 1019
- electron mobility measured in principle units = 0.36
- Hole mobility measured in principle units = 0.17

Solution :
J = σε
Where :
ε = 1.5V/0.25mm = 1.5/ 0.25 x 10-3 V/m

σ = ( μn + μp ) n i e
= (0.36 + 0.17) x 2 x 1019 x 1.6 x 10-19
= 1.696 (Ω m)-1
J = 1.5/ 0.25 x 10-3 x 1.696 = 10176 A/m2
area =10-4 m2 = 1 cm x 1 cm
So the current is:

I = area x J = 10-4 x10176 =1.0176A

ni changes with temperature where square of ni is proportion al with

the cubic of temperature:

ni2 α T3 exp ( -EG0/kT ) (16)

where EG0 energy of the gap zero kelvin.

25
As for germanium , the density changes with temperature as follows:

ni2 = 3.1 x 1032 T3 exp(- 9101/T)

As for silicon , the density changes with temperature as follows:

ni2 = 1.5 x 1033 T3 exp(-14028/T)

As a result of the last two relations and using equation 16 , that the
conductivity in germanium increases by 6% for increasing temperature
one degree, while in silicon it increases 8%, so high temperature may
prevent use of semiconductors .

1.9 Energy Bands for intrinsic semiconductor

Change of electron density in conduction band with temperature,
generally, is according to the following relation:

n = NC exp[-(EC – EF)/kT] (17)

where NC is the effective density for energy levels in conduction band.

Change of hole density in valiance band with temperature is according to

the following relation:

p = Nv exp[-(EF – Ev)/kT] (18)

where Nv is the effective density for energy levels in valiance band.

for pure intrinsic semiconductor : n = p = ni , and using reations 18 , 17 ,

we can write the following relation:

NC exp[-(EC – EF)/kT] = Nv exp[-(EF – Ev)/kT]

To get EF we take ln for both sides of the equation ;

ln(NC/ Nv) = (EC + Ev -2 EF)/kT

so,

EF = (1/2) ( EC + Ev) - (kT/2) ln(NC / Nv) (19)

26
If Nv = NC , then equation 19 becomes:
EF = (1/2) ( EC + Ev) (20)

This means that Fermi level is at the middle of the gap.

1.10 Atomic structure of Silicon and Germanium

Solid state electronics arises from the unique properties of silicon and
germanium, each of which has four valence electrons and which form
crystal lattices in which substituted atoms (dopants) can dramatically
change the electrical properties. Fig.1-12 shows the outer orbit electrons
for both atoms of silicon and germanium.

Fig.1-12

1.10.1 Covalent Bond in Silicon and Germanium

We shall take the most common case of Ge and Si whose lattice structure
is shown in Fig. 1-13. These structures are called the diamond-like
structures. Each atom is surrounded by four nearest neighbours. We know
that Si and Ge have four valence electrons. In its crystalline structure,
every Si or Ge atom tends to share one of its four valences electrons with
each of its four nearest neighbor atoms, and also to take share of one
electron from each such neighbour. These shared electronpairs are
referred to as forming a covalent bond or simply a valence bond. The two
shared electrons can be assumed to shuttle back-and forth between the
associated atoms holding them together strongly.
Fig. 1-14 schematically shows the 2-dimensional representation of Si or
Ge structure shown in Fig.1-13 which overemphasizes the covalent bond.
It shows an idealized picture in which no bonds are broken (all bonds are
intact). Such a situation arises at low temperatures. As the temperature

27
increases, more thermal energy becomes available to these electrons and
some of these electrons may break–away (becoming free electrons
contributing to conduction).

Fig. 1-13

Fig. 1-14 silicon covalent vond

The thermal energy effectively ionizes only a few atoms in the crystalline
lattice and creates a vacancy in the bond as shown in Fig. 1-15(a). The
28
neighborhood, from which the free electron (with charge –q) has come
out leaves a vacancy with an effective charge (+q ). This vacancy with the
effective positive electronic charge is called a hole. The hole behaves as
an apparent free particle with effective positive charge. In intrinsic
semiconductors, the number of free electrons, ne is equal to the number of
holes, nh. Semiconductors possess the unique property in which, apart
from electrons, the holes also move.

Fig. 1-15

Suppose there is a hole at site 1 as shown in Fig. 1-14(a). The movement

of holes can be visualized as shown in Fig. 14.5(b). An electron from the
covalent bond at site 2 may jump to the vacant site 1 (hole). Thus, after
such a jump, the hole is at site 2 and the site 1 has now an electron.
Therefore, apparently, the hole has moved from site 1 to site 2. Note that
the electron originally set free is not involved in this process of hole
motion. The free electron moves completely independently as conduction
electron and gives rise to an electron current, Ie under an applied electric
field. Remember that the motion of hole is only a convenient way of
describing the actual motion of bound electrons, whenever there is an
empty bond anywhere in the crystal. Under the action of an electric field,
these holes move towards negative potential giving the hole current, I h.
29
The total current, I is thus the sum of the electron current Ie and the hole
current Ih:
I = Ie + Ih
It may be noted that apart from the process of generation of conduction
electrons and holes, a simultaneous process of recombination occurs in
which the electrons recombine with the holes. At equilibrium, the rate of
generation is equal to the rate of recombination of charge carriers. The
recombination occurs due to an electron colliding with a hole.

1.11 Impurity Semiconductors

The conductivity of an intrinsic semiconductor depends on its
temperature, but at room temperature its conductivity is very low. As
such, no important electronic devices can be developed using these
semiconductors. Hence there is a necessity of improving their
conductivity. This can be done by making use of impurities. When a
small amount, say, a few parts per million (ppm), of a suitable impurity is
added to the pure semiconductor, the conductivity of the semiconductor is
increased manifold. Such materials are known as extrinsic
semiconductors or impurity semiconductors. The deliberate addition of a
desirable impurity is called doping and the impurity atoms are called
dopants. Such a material is also called a doped semiconductor. The
dopant has to be such that it does not distort the original pure
semiconductor lattice. It occupies only a very few of the original
semiconductor atom sites in the crystal. A necessary condition to attain
this is that the sizes of the dopant and the semiconductor atoms should be
nearly the same.
There are two types of dopants used in doping the tetravalent Si or Ge:

(i) Pentavalent (valency 5); like Arsenic (As), Antimony (Sb),

Phosphorous (P), etc.

(ii) Trivalent (valency 3); like Indium (In), Boron (B), Aluminium (Al),
etc.
We shall now discuss how the doping changes the number of charge
carriers (and hence the conductivity) of semiconductors. Si or Ge belongs
to the fourth group in the Periodic table and, therefore, we choose the
dopant element from nearby fifth or third group, expecting and taking
care that the size of the dopant atom is nearly the same as that of Si or Ge.
Interestingly, the pentavalent and trivalent dopants in Si or Ge give two
entirely different types of semiconductors as discussed below.

30
1.11.1 n-type semiconductor

Suppose we dope Si or Ge with a pentavalent element as shown in Fig. 1-

16. When an atom of +5 valiancy element occupies the position of an
atom in the crystal lattice of Si, four of its electrons bond with the four
silicon neighbours while the fifth remains very weakly bound to its parent
atom. This is because the four electrons participating in bonding are seen
as part of the effective core of the atom by the fifth electron. As a result
the ionization energy required to set this electron free is very small and
even at room temperature it will be free to move in the lattice of the
semiconductor. For example, the energy required is ~ 0.01 eV for
germanium, and 0.05 eV for silicon, to separate this electron from its
atom. This is in contrast to the energy required to jump the forbidden
band (about 0.72 eV for germanium and about 1.1 eV for silicon) at room
temperature in the intrinsic semiconductor. Thus, the pentavalent dopant
is donating one extra electron for conduction and hence is known as
donor impurity. The number of electrons made available for conduction
by dopant atoms depends strongly upon the doping level and is
independent of any increase in ambient temperature. On the other hand,
the number of free electrons (with an equal number of holes) generated
by Si atoms, increases weakly with temperature. In a doped
semiconductor the total number of conduction electrons ne is due to the
electrons contributed by donors and those generated intrinsically, while
the total number of holes nh is only due to the holes from the intrinsic
source. But the rate of recombination of holes would increase due to the
increase in the number of electrons. As a result, the number of holes
would get reduced further. Thus, with proper level of doping the number
of conduction electrons can be made much larger than the number of
holes. Hence in an extrinsic semiconductor doped with pentavalent
impurity, electrons become the majority carriers and holes the minority
carriers. These semiconductors are, therefore, known as n-type
semiconductors. For n-type semiconductors, we have, ne >> nh

31
 Fig. 1-16

1.11.2 p-type semiconductor

This is obtained when Si or Ge is doped with a trivalent impurity like Al,
B, In, etc. The dopant has one valence electron less than Si or Ge and,
therefore, this atom can form covalent bonds with neighboring three Si
atoms but does not have any electron to offer to the fourth Si atom. So the
bond between the fourth neighbor and the trivalent atom has a vacancy or
hole as shown in Fig.1-17. Since the neighboring Si atom in the lattice
wants an electron in place of a hole, an electron in the outer orbit of an
atom in the neighborhood may jump to fill this vacancy, leaving a

32
vacancy or hole at its own site. Thus the hole is available for conduction.
Note that the trivalent foreign atom becomes effectively negatively
charged when it shares fourth electron with neighbouring Si atom.
Therefore, the dopant atom of p-type material can be treated as core of
one negative charge along with its associated hole as shown in Fig. 1-17
(b). It is obvious that one acceptor atom gives one hole. These holes are
in addition to the intrinsically generated holes while the source of
conduction electrons is only intrinsic generation. Thus, for such a
material, the holes are the majority carriers and electrons are minority
carriers. Therefore, extrinsic semiconductors doped with trivalent
impurity are called p-type semiconductors. For p-type semiconductors,
the recombination process will reduce the number (ni)of intrinsically
generated electrons to ne. We have, for p-type semiconductors nh >> ne

Fig.1-17

33
Note that the crystal maintains an overall charge neutrality as the charge
of additional charge carriers is just equal and opposite to that of the
ionized cores in the lattice. In extrinsic semiconductors, because of the
abundance of majority current carriers, the minority carriers produced
thermally have more chance of meeting majority carriers and thus getting
destroyed. Hence, the dopant, by adding a large number of current
carriers of one type, which become the majority carriers, indirectly helps
to reduce the intrinsic concentration of minority carriers. The
semiconductor‘s energy band structure is affected by doping. In the case
of extrinsic semiconductors, additional energy states due to donor
impurities (ED) and acceptor impurities (EA) also exist. In the energy band
diagram of n-type Si semiconductor, the donor energy level ED is slightly
below the bottom EC of the conduction band and electrons from this level
move into the conduction band with very small supply of energy. At
room temperature, most of the donor atoms get ionized but very few
(~10–12) atoms of Si get ionized. So the conduction band will have most
electrons coming from the donor impurities, as shown in Fig. 1-18(a).
Similarly, for p-type semiconductor, the acceptor energy level EA is
slightly above the top EV of the valence band as shown in Fig. 1-18(b).
With very small supply of energy an electron from the valence band can
jump to the level EA and ionize the acceptor negatively. (Alternately, we
can also say that with very small supply of energy the hole from level EA
sinks down into the valence band. Electrons rise up and holes fall down
when they gain external energy.) At room temperature, most of the
acceptor atoms get ionized leaving holes in the valence band. Thus at
room temperature the density of holes in the valence band is
predominantly due to impurity in the extrinsic semiconductor. The
electron and hole concentration in a semiconductor in thermal
equilibrium is given by nenh = ni2

Fig.1-18

34
Though the above description is grossly approximate and hypothetical, it
helps in understanding the difference between metals, insulators and
semiconductors (extrinsic and intrinsic) in a simple manner. The
difference in the resistivity of C, Si and Ge depends upon the energy gap
between their conduction and valence bands. For C (diamond), Si and Ge,
the energy gaps are 5.4 eV, 1.1 eV and 0.7 eV, respectively. Sn also is a
group IV element but it is a metal because the energy gap in its case is 0
eV.

Example.2
Suppose a pure Si crystal has 5 × 1028 atoms m–3. It is doped by 1 ppm
(parts per million) concentration of pentavalent As. Calculate the number
of electrons and holes. Given that ni =1.5 × 1016 m–3.

Solution
Note that thermally generated electrons (ni ~1016 m–3) are negligibly small
as compared to those produced by doping. Therefore, ne ≈ ND.
Since nenh = ni2, The number of holes:

nh = (2.25 × 1032)/(5 ×1022)

~ 4.5 × 109 m–3

1.12 Electron and hole Densities in Each Type:

The computation of the electron and hole densities in semi-conductor is
the most important application of Fermi-Dirac statistics.
Carrier density at a given level in n-type semiconductor:
Consider an extrinsic semiconductor doped with donor atoms give rise to
donor levels close to the conduction band. Let ND be the number of
impurity of atoms, in the unit volume. If in the same volume P number of
holes , so the total positive ionic concentration is (ND + P). In the same
manner for the acceptor impurities , the total negative ionic concentration
is (NA + n). Where :
NA represent the concentration of acceptor impurities , while n represent
the free electrons.
For the crystal to be electrically balanced ( neutral ), the positive
concentration must equals the negative concentration. So:

35
ND + p = NA + n (21)

In the negative type crystal NA = 0 , and also the number of electrons

largely exceeds the number of holes: ( n >> p ) ,
So, from these conditions, relation 21 becomes:

n ND (22)

To cancel confusion between symbols , it is better to follow the

following:
1-In the negative type crystal : we use :
nn to represent the number of electrons.
pn to represent the number of holes.

2-In the positive type crystal : we use :

np to represent the number of electrons.

pp to represent the number of holes.

So, relation 22 becomes:

nn ND (23)

In the negative type crystal , equation 10 above becomes:

nn pn = ni2 (24)

So, from equations (23) ,(24) , the number of holes in the negative type
crystal is:

pn n i 2 / ND (25)

Now , in the positive type crystal , ND = 0 and ( p >> n ) and use these
conditions equation 21 becomes:

pp NA (26)

Also equation 10 can be written as follows:

36
np pp = ni2 (27)

Electron concentration in the positive type crystal is:

np = ni2 / NA (28)

Now , we can calculate Fermi level EF in the negative type crystal and in
the positive type crystal by substituting: (n) in equation 17 is replaced by
ND , and in equation 18 replace p by NA.
So , EF in the negative type crystal can be written as follows:

EF = EC - (kT) ln(NC / ND) (29)

And in the positive type crystal EF can be written as follows:

EF = Ev + (kT) ln(Nv / NA) (30)

Example 3:

Find the germanium resistivity at room temperature if germanium is

doped by donors impurities with ratio (1: 108) supposing that germanium
has: μn =3800 cm2/V.s , μp = 1800 cm2/V.s and
ND = 4.41 x 1014 (atom/cm3) , at room temperature (3000k)
ni = 2.4 x 1013/cm3

Solution:

Resistivity = 1/ σ
σ = ( n μn + p μ p ) e

n = ND = 4.41 x 1014 (atom/cm3)

p= ni2/ ND = (2.4 x 1013) 2 /4.41 x 1014 = 1.42 x 1012 ( hole/cm3)

For p << n , so:

σ = n μn e approximately
= 4.41 x 1014 x 3800 x 1.6 x 10-19
= 0.268 (Ω m)-1
So :
1/ σ = 1/0.268 = 3.72 (Ω m)

37
Example 4:
The following data are given for intrinsic Ge at 300OK.
ni = 2.4 x 10 19m-3 , μe =0.39 m2v -1s-1; μp=0.19 m2v -1s-1,
calculate the resistivity of the sample.

Solution:

Principle: σ = ni e (μe + μp)

r = 1/ σ = 0.448 ohm-cm

Example 5

The electron and hole motilities of Si sample are 0.135 and

0.048 m2v -1s-1 respectively. Density of Si atoms ni = 1.5 x 1016 m-3.
Determine the conductivity of Intrinsic Si at 300 OK. The sample is then
doped with 1023 phosphorous atom/m3.
Determine the equilibrium hole concentration and conductivity.

Solution:

Principle: σi = ni e (μe + μp)

σ = ND μe e

Equilibrium hole concentration

p = ni2/ ND


Answer: 
σi = 0.44 x 10 -3 s
σ= 2.16 x 103 s
p = 2.25 x 109 m-3

1.13 Thermistor

38
Change of the conduction of semiconductors with temperature can be
used to make resistors their resistivity change with temperature. Such
resistors called thermistors. The name is derived from thermal resistor, it
consists , simply, of a piece of intrinsic semiconductor its two terminals
are connected to two conducting wires. It is to be noted that Silicon and
Germanium are not used for this purpose because of their characteristics
are much changed with impurities which are difficult to be exactly
cancelled. Instead of Silicon and Germanium, It is better to use mixing of
metallic oxides like ferrous , Nickel…etc. In contrast to metals
thermistors have negative temperature coefficient(NTC) which means
that resistance of the thermistor decreases with increase of temperature.
Also there are special thermistors with positive temperature coefficients.

1.14 Hall effect

When a magnetic field B is applied perpendicular to a current carrying

conductor or semiconductor, the charge carriers (of the current) suffer a
deflection due to the effect of the applied force f (voltage is developed
across the specimen in a direction perpendicular to both the current and
the magnetic field). This phenomenon is called the Hall effect and the
voltage so developed is called Hall voltage. As shown in figure 1 ,
consider a uniform thick metal strip placed with its length L parallel to
X-axis. Let a current I is passed in the conductor along X-axis and a
magnetic field B is established along X-axis. Due to the magnetic field,
the charge carriers experience a force F perpendicular to X-Z plane (i.e
along Y-axis)
The direction of this force is given by Fleming left hand rule. If the
charge carriers are electrons then they will experience a force in the
negative direction of Y. Hence, they will be accumulated on the back
surface of the strip. Due to this fact the back surface will be charged
negatively while the front surface will be charged positively. Thus, a
transverse potential difference is created. This emf is known as Hall emf.
If the charge carriers are positively charged particles like protons of
holes, the sign of emf is reversed. Thus, the nature of charge carriers can
be found by determining the sign of Hall emf which can be measured by a
potentiometer. Experiments showed that the charge carriers in metals are
electrons while the charge carriers in p-type semiconductors are holes.
Magnetic deflecting force

f= e B v (31)

39
 where e represent the value of charge carrier of the current. B is the
magnetic field perpendicular to the current. L is the conductor length , v
is the rate of electron velocity inside the conductor carrying the current I
v=L/T, T is the time taken by the charge to traverse the length L. actually
the force applied on the electrons passing through the conductor is in
direction reverse to the traditional positive direction of the current.
Under the effect of this force charges tend to be summed on one side of
the piece constructing electrical field across the piece such that the
resulting force of this electric field balance the effecting magnetic force ,
this phenomena known as Hall phenomena discovered by Hall in metals
1879.
This phenomena has many applications , the most ones for
semiconductors are to determines the semiconductor type either positive
or negative and to find some of their characteristics such as
concentration, conductivity and mobility.
If the piece shown in Fig. 1-19 is carrying a current I in the X direction
and the magnetic field B is in the Z direction , the force applied to the
current charges is in the Y.
If the piece is from negative type , the electrons carry the current are
forced to deflect to the side (1) as shown in Fig. 1-19, so this side is
negative with respect to side (2) and voltage difference appears between
the two sides. Such voltage difference is known as Hall voltage and
before balance is reached , the electric field intensity ε result from this
volt gives force balance the magnetic force and this can be written as
follows:

eε=eBv (32)
where v is drift velocity of charges, and Hall voltage equals VH so, the
electric field ε can be written as follows:

40
 Fig.1-19 Hall effect

ε = VH /d (33)

where d is the distance between the two surfaces 1 and 2 (on the Fig.1-
19). From equation 5 :

v= J/ne (34)

Substitute from equations (33) , (34) in equation 32 we get the Hall

voltage as follows:

VH = BJd/ne (35)

The passing current density is:

J=I/ w.d (36)

Where w is the width of the piece and substituting equation 36 in
equation 35 we get:

VH = BI/ ρw (37)

The value ne represent charge density and its symbol is ρ. Equation

sometimes is written as in the form:
41
 VH = B I RH/ w (38)

Where RH called Hall factor which is the reverse of charge density and
its units m3/coulomb (the relation is approximate one because of the
supposition of taking the average drift velocity of charges as constant. If
we take into consideration the randomness of the velocity , the accurate
relation is for Hall coefficient RH = 3 π/ 8ρ :

RH = VH w / BI (39)

If Hall coefficient RH is known , so electron density in the piece can be

measured , and from the polarity of the voltage difference we can know
the type of the current carriers since if the piece from positive type : the
side 1 is positive with respect to side 2 as mentioned above and charge
density at this situation ρ equals ρe where ρ represent hole concentration.
We can find mobility and conductivity if one of them is known and with
the use of equation 7.
Hall phenomena can be used to measure the magnetic fields since it is
possible to measure fields of tenth of gauss.

Example 6
The RH of a specimen is 3.66 x 10-4 m3 c-1. Its resistivity is 8.93 x 10-3
ohm-cm. Find μ and n.

Solution

Principle :
μ = σ RH = RH/ρ

= [1/ (8.93 x 10-3 )][ 3.66 x 10-4 m3 c-1 ]

= 0.4116 m2/Vs

n= 1/ eRH

= 1/ e [3.66 x 10-4 m3 c-1]

n = 1.7 x 1022/m3
42
Objective type questions

1. When the temperature of a semiconductor is increased, the

conductivity of a semiconductor __________.

2. The conductivity of a semiconductor is due to the drifting of

electron and ___________.

3. When the temperature of semiconductor is nearly 0 K, it

behaves as good as____________.

4. The order of energy gap of semiconductor is ___________.

5. The position of Fermi level in intrinsic semiconductor lies

__________.

6. The majority charge carriers are electrons in

_______________.

7. The minority carriers are electrons in _______________.

8. In n-type of semiconductor the Fermi level lies close to

_________.
9. In p-type semiconductor the Fermi level lies close to
___________.

Answers:

1. increases

2. holes

3. insulator

4. 1 eV

43
5. lies midway between conduction and valence bands

6. n-type

7. p-type

8. conduction band

9. valence band

Questions
First: Put T for the true sentences and F for the false ones:
1- Electric conductivity of intrinsic semiconductors increases
with increase of temperature ( )
2- With the increase of the number of impurity atoms in the
semiconductor crystal , the number of charge carriers
increase ( )
3- In insulator materials the energy gap between valiance and
conduction bands is very small ( ).
4- Conduction band in insulator materials is approximately
empty from free electrons at normal temperature ( )
5- When add impurity donor (give electrons) for intrinsic
semiconductor, it makes it negative N-type
Semiconductor ( )
6- The crystal of pure (intrinsic) germanium conduct
electricity at room temperature ( )
7- The crystal of positive semiconductor has positive charge
and positive voltage ( )
8- The crystal of positive semiconductor (p) has positive
charge ( )
9- Electrical resistance for pure (intrinsic) semiconductors
increases with the increase of their temperature ( )
10- semiconductors are the materials that prevent passing of
electrical current when they are intrinsic, while they permit
passing electrical current when they adopted with

44
 impurities ( )

11- In the intrinsic crystal , the number of negative charge

carriers equals the number of positive charge carriers ( )

Secondly : Complete the following sentences

1- Resistance of intrinsic semiconductors decreases………….

2- Resistance of intrinsic semiconductors ………..with increase

of their temperature.

3- The electric charge of the crystal of positive semiconductor

(p) is ……….

4- The energy necessary for electron to transport from valiance

band to conduction band called………….

5-Electric conductivity of semiconductors increases

by…………

Thirdly: Circle the correct answer in following :

1- If one atom of germanium crystal is replaced by aluminum

atom( has three electrons in outer orbit), we get :
 Positive type semiconductor
 pn junction for direct an alternate current
 Negative type semiconductor 
 Crystal which is exactly isolator for electrical current.

2- Electrical current is transferred in negative N-type
Semiconductor by: Holes Positive ions Electrons
 Holes
 Positive ions
 Electrons
Protons

45
3-The crystal of N-type Semiconductor has:

 Negative charges only

 Negative charges more than positive charges
 Negative charges less than positive charges
 Negative charges equal positive charges

4-The hole in P-type Semiconductor is produced by:

 Increase electron
 Decrease electron
 Increase proton
 Decrease proton

5- The crystal of N-type Semiconductor is :


 electrically negative
 electrically neutral
 Electricallypositive
 Electrical isolator

Fourthly : Give interpretation for each of the following:

1- Electrical resistance for intrinsic semiconductors decreases

with increase of temperature.

2- Adding impurity atoms Pentavalent (valence 5) or Trivalent

(valence 3) for intrinsic semiconductor crystal , increases its
electrical conductivity.

46
Fifth – compare between positive p-type semiconductor
crystal and negative N- type semiconductor crystal

p-type semiconductor N- type comparison

crystal semiconductor
crystal
1-How it is produced
2-Majority charge
carriers

Six: What is the concept of each of the following:

1-adoping in semiconductor crystal

2-Energy band

3-valience band

4-Negative N-type semiconductor

47
5-Positive P-type semiconductor

48
 Ch.2
p-n Junction
Semiconductor diodes

49
2-1 Introduction
A p-n junction is the basic building block of many semiconductor devices
like diodes, transistor, etc. A clear understanding of the junction behavior
is important to analyze the working of other semiconductor devices.We
will now try to understand how a junction is formed and how thejunction
behaves under the influence of external applied voltage (alsocalled bias).

2-2 p-n Junction Formation

Consider a thin p-type silicon (p-Si) semiconductor wafer. By
addingprecisely a small quantity of pentavelent impurity, part of the p-Si
wafer
can be converted into n-Si. There are several processes by which
asemiconductor can be formed. The wafer now contains p-region andn-
region and a metallurgical junction between p-, and n- region.

Two important processes occur during the formation of a p-n junction:

2.3 diffusion and drift

We know that in an n-type semiconductor, theconcentration of electrons

(number of electrons per unit volume) is morecompared to the
concentration of holes. Similarly, in a p-typesemiconductor, the
concentration of holes is more than the concentrationof electrons. During
the formation of p-n junction, and due to theconcentration gradient across
p-, and n- sides, holes diffuse from p-sideto n-side (p → n) and electrons
diffuse from n-side to p-side (n → p). Thismotion of charge carries gives
rise to diffusion current across the junction.When an electron diffuses
from n → p, it leaves behind an ionizeddonor on n-side. This ionized
donor (positive charge) is immobile as it isbonded to the surrounding
atoms. Diffusion current is defined as a current passing for very short
interval due to diffusion of charge carrier between the junction terminals.
Density ofholes diffusion current Jp is proportional to the gradient or rate
of change holes concentration (dp/dx)[ where x is through the junction
width], and this can be expressed as follows:

Jp = - e Dp (dp/dx) (1)

50
Where e is the electron charge (negative sign as it is known holes motion
is reverse to electrons motions).
Dp is called diffusion constant for holes measured in square meter per
second (Fig.2-1). Similarly, electrons diffusion current density equation
can be written as follows:

Je= eDn (dn/dx) (2)

There is relation between diffusion constant and electron mobility μ

(measured in square meter/volt.second) and such relation as Enstien
equation and can be written as follows:

Dp /µp =Dn / µn = VT (3)

Where VT represent the volt equivalent of temperature and it is known

as:

VT = k T (4)

Where k is the Boltzman constant = 1.38 x 10-23 J/oK

T is the degree of temperature measured in ( oK(
For VTto be in volts , it is better for k to be measured in ( eV/oK )
and this is obtained dividing Boltzman constant by electron charge i.e :

K=1.38 x 10-23 / 1.602 x 10-19 = 8.62 x 10-5eV/oK

At room temperature T nearly = 300oK, so substituting in equation 4 , we

get:

VT = 8.62 x 10-5 x 300 =0.026 eV approx.

This means :

D = 0.026μ

Now as the electrons continue to diffusefrom n → p, a layer of positive

charge (or positive space-charge region) onn-side of the junction is
developed.Similarly, when a hole diffuses from p → n due to the

51
concentrationgradient, it leaves behind an ionized acceptor (negative
charge) which isimmobile. As the holes continue to diffuse, a layer of
negative charge (ornegative space-charge region) on the p-side of the
junction is developed. This space-charge region on either side of the
junction together is knownas depletion regionas the electrons and holes
taking part in the initialmovement across the junction depleted the region
of itsfree charges (Fig. 2-1). The thickness of depletion regionis of the
order of one-tenth of a micrometre. Due to thepositive space-charge
region on n-side of the junction andnegative space charge region on p-
side of the junction,an electric field directed from positive charge
towardsnegative charge develops. Due to this field, an electron onp-side
of the junction moves to n-side and a hole on nsideof the junction moves
to p-side. The motion of chargecarriers due to the electric field is called
drift. Thus adrift current, which is opposite in direction to the
diffusioncurrent (Fig. 2-1) starts.It is to be noted that drift is the carrier
motion due to applied electric field.

Fig.2-1

52
Initially, diffusion current is large and drift current is small.As the
diffusion process continues, the space-charge regionson either side of the
junction extend, thus increasing the electricfield strength and hence drift
current. This process continuesuntil the diffusion current equals the drift
current. Thus a p-njunction is formed. In a p-n junction under equilibrium
thereis no netcurrent.The loss of electrons from the n-region and the gain
ofelectron by the p-region cause a difference of potential acrossthe
junction of the two regions. The polarity of this potential issuch as to
oppose further flow of carriers so that a condition ofequilibrium exists.
Fig.2-2 shows the p-n junction atequilibrium and the potential across the
junction. Then-material has lost electrons, and p material has
acquiredelectrons. The n material is thus positive relative to the pmaterial.
Since this potential tends to prevent the movement ofelectron from the n
region into the p region, it is often called abarrier potential.

Fig.2-2

2.4 Built-in potentials and Energy band in pn junction

Fig. 2-3 displays band-bending diagram for p–n diode at zero applied
voltage. The depletion region is shaded.The figure shows a band bending
diagram for a p–n diode; that is, the band edges for the conduction band
(upper line) and the valence band (lower line) are shown as a function of
position on both sides of the junction between the p-type material (left
side) and the n-type material (right side). When a p-type and an n-type
region of the same semiconductor are brought together and the two diode
53
contacts are short-circuited, the Fermi half-occupancy level (dashed
horizontal straight line) is situated at a constant level. This level insures
that in the field-free bulk on both sides of the junction the hole and
electron occupancies are correct. (So, for example, it is not necessary for
an electron to leave the n-side and travel to the p-side through the short
circuit to adjust the occupancies.)

However, a flat Fermi level requires the bands on the p-type side to move
higher than the corresponding bands on the n-type side, forming a step or
barrier in the band edges, labeled φB. This step changes the electron
density on the n-side to become a Boltzmann factorexp(−φB/Vth) smaller
on the p-side, to correspond to the lower electron density in p-region.
Here the symbol Vth denotes the thermal voltage, defined as Vth = kBT/q.
At T = 290 kelvins (room temperature), the thermal voltage is
approximately 25 mV. Similar considerations apply for the effect of the
barrier upon the hole density in the n-region.

Fig. 2-3

In Fig.2-4more declaration for diffusion and space charge region

(depletion) for a p–n junction in thermal equilibrium with zero-bias
voltage applied. Electron and hole concentration are reported with blue
and red lines, respectively. Gray regions are charge-neutral. Light-red
zone is positively charged. Light-blue zone is negatively charged. The
electric field is shown on the bottom, the electrostatic force on electrons
and holes and the direction in which the diffusion tends to move electrons
and holes.

54
The electric field created by the space charge region opposes the
diffusion process for both electrons and holes. There are two concurrent
phenomena: the diffusion process that tends to generate more space
charge and the electric field generated by the space charge that tends to
counteract the diffusion. The carrier concentration profile at equilibrium
is shown in figure A with blue and red lines. Also shown are the two
counterbalancing phenomena that establish equilibrium.

Fig 2-4

In Fig.2-5a p–n junction in thermal equilibrium with zero-bias voltage applied. Under
the junction, plots for the charge density, the electric field, and the voltage are
reported.

The space charge region is a zone with a net charge provided by the fixed ions
(donors or acceptors) that have been left uncovered by majority carrier diffusion.
When equilibrium is reached, the charge density is approximated by the displayed
step function. In fact, the region is completely depleted of majority carriers (leaving a
charge density equal to the net doping level), and the edge between the space charge
region and the neutral region is quite sharp (see figure B, Q(x) graph). The space
charge region has the same magnitude of charge on both sides of the p–n interfaces,
thus it extends farther on the less doped side (the n side in Figs.2-3 , 2-4).

Example 1
Can we take one slab of p-type semiconductor andphysically join it to
another n-type semiconductor to get p-n junction?

55
Solution
No! Any slab, howsoever flat, will have roughness muchlarger than the
inter-atomic crystal spacing (~2 to 3 Å) and hencecontinuous contactat
the atomic level will not be possible. The junctionwill behave as a
discontinuity for the flowing charge carriers.

Fig.2-5

2.5 Semiconductor Diode

A semiconductor diode [Fig. 2-6(a)] is basically ap-n junction with

metallic contacts provided at theends for the application of an external
voltage. It is atwo terminal device. A p-n junction diode issymbolically
56
represented as shown in Fig. 2-6(b).The direction of arrow indicates the
conventionaldirection of current (when the diode is under forwardbias).
The equilibrium barrier potential can be alteredby applying an external
voltage Vacross the diode.The situation of p-n junction diode under
equilibrium(without bias) is shown in Fig. 2-2.

Fig. 2-6

2.5.1 p-n junction diode under forward bias

When an external voltage Vis applied across a semiconductor diode

suchthat p-side is connected to the positive terminal of the battery and n-
sideto the negative terminal [Fig. 2-7(a)], it is said to be forward
biased.The applied voltage mostly drops across the depletion region and
thevoltage drop across the p-side and n-side of the junction is
negligible.(This is because the resistance of the depletion region – a
region wherethere are no charges – is very high compared to the
resistance of n-sideand p-side.) The direction of the applied voltage (V) is
opposite to thebuilt-in potential V0. As a result, the depletion layer
widthdecreases and the barrier height is reduced [Fig. 2-7(b)].
Theeffective barrier height under forward bias is (V0 – V ).
If the applied voltage is small, the barrier potential will bereduced only
slightly below the equilibrium value, and only asmall number of carriers
in the material—those that happen tobe in the uppermost energy levels—
will possess enough energyto cross the junction. So the current will be
small. If we increasethe applied voltage significantly, the barrier height
will be reducedand more number of carriers will have the required
energy. Thusthe current increases.Due to the applied voltage, electrons
57
from n-side cross thedepletion region and reach p-side (where they are
minoritycarries). Similarly, holes from p-side cross the junction and
reachthe n-side (where they are minority carries). This process
underforward bias is known as minority carrier injection. At thejunction
boundary, on each side, the minority carrierconcentration increases
significantly compared to the locationsfar from the junction.Due to this

Fig. 2-7

concentration gradient, the injected electrons onp-side diffuse from the

junction edge of p-side to the other endof p-side. Likewise, the injected
holes on n-side diffuse from thejunction edge of n-side to the other end of
n-side(Fig. 2-8). This motion of charged carriers on either sidegives rise
to current. The total diode forward current is sumof hole diffusion current
and conventional current due toelectron diffusion. The magnitude of this
current is usually in mA.

Fig. 2-8

58
2.5.2 P-N Junction Energy Bands at equilibrium
For a p-n junction at equilibrium (Fig.2-9), the Fermi levels match on the
two sides of the junctions. Electrons and holes reach equilibrium at the
junction and form a depletion region. The upward direction in the
diagram represents increasing electron energy. That implies that you
would have to supply energy to get an electron to go up on the diagram,
and supply energy to get a hole to go down.

Fig.2-9

2.5.3 Energy Bands of p-n junction at forward bias

To forward bias the p-n junction, the p side is made more positive, so that
it is "downhill" for electron motion across the junction(Fig.2-10). An
electron can move across the junction and fill a vacancy or "hole" near
the junction. It can then move from vacancy to vacancy leftward toward
the positive terminal, which could be described as the hole moving right.
The conduction direction for electrons in the diagram is right to left, and
the upward direction represents increasing electron energy.

Fig.2-10
Fig.2-11 shows the band-bending diagram for p–n diode in forward bias.
Diffusion drives carriers across the junction.

59
 Fig.2-11

A forward bias separates the two bulk half-occupancy levels by the

amount of the applied voltage, which lowers the separation of the p-type
bulk band edges to be closer in energy to those of the n-type. As shown in
the diagram, the step in band edges is reduced by the applied voltage to
φB−vD. (The band bending diagram is made in units of volts, so no
electron charge appears to convert vD to energy.)

Under forward bias, a diffusion current flows (that is a current driven by a

concentration gradient) of holes from the p-side into the n-side, and of
electrons in the opposite direction from the n-side to the p-side. The
gradient driving this transfer is set up as follows: in the bulk distant from
the interface, minority carriers have a very low concentration compared
to majority carriers, for example, electron density on the p-side (where
they are minority carriers) is a factor exp(−φB/Vth) lower than on the n-
side (where they are majority carriers). On the other hand, near the
interface, application of voltage vD reduces the step in band edges and
increases minority carrier densities by a Boltzmann factor exp(v D/Vth)
above the bulk values. Within the junction, the pn-product is increased
above the equilibrium value.

The gradient driving the diffusion is then the difference between the large
excess minority carrier densities at the barrier and the low densities in the
bulk, and that gradient drives diffusion of minority carriers from the
interface into the bulk. The injected minority carriers are reduced in
number as they travel into the bulk by recombination mechanisms that
drive the excess concentrations toward the bulk values.

60
Recombination can occur by direct encounter with a majority carrier,
annihilating both carriers, or through a recombination-generation center, a
defect that alternately traps holes and electrons, assisting recombination.
The minority carriers have a limited lifetime, and this lifetime in turn
limits how far they can diffuse from the majority carrier side into the
minority carrier side, the so-called diffusion length. In the LED
recombination of electrons and holes is accompanied by emission of light
of a wavelength related to the energy gap between valence and
conduction bands, so the diode converts a portion of the forward current
into light.

The half-occupancy lines for holes and electrons cannot remain flat
throughout the device as they are in equilibrium, but become quasi-Fermi
levels that vary with position. As shown in the figure, the electron quasi-
Fermi level shifts with position, from the half-occupancy equilibrium
Fermi level in the n-bulk, to the half-occupancy equilibrium level for
holes deep in the p-bulk. The hole quasi-Fermi level does the reverse. The
two quasi-Fermi levels do not coincide except deep in the bulk materials.

The figure shows the majority carrier densities drop from the majority
carrier density levels nB, pB in their respective bulk materials, to a level a
factor exp(−(φB−vD)/Vth) smaller at the top of the barrier, which is
reduced from the equilibrium value φB by the amount of the forward
diode bias vD. Because this barrier is located in the oppositely doped
material, the injected carriers at the barrier position are now minority
carriers. As recombination takes hold, the minority carrier densities drop
with depth to their equilibrium values for bulk minority carriers, a factor
exp(−φB/Vth) smaller than their bulk densities n B, pB as majority carriers
before injection. The reduced step in band edges also means that under
forward bias the depletion region narrows as holes are pushed into it from
the p-side and electrons from the n-side.

In the simple p–n diode the forward current increases exponentially with
forward bias voltage due to the exponential increase in carrier densities,
so there is always some current at even very small values of applied
voltage. However, if one is interested in some particular current level, it
will require a "knee" voltage before that current level is reached. For
example, a very common choice in texts about circuits using silicon
diodes is VKnee = 0.7 V. Above the knee, the current continues to increase
exponentially. Some special diodes, such as some varactors, are designed
deliberately to maintain a low current level up to some knee voltage in
the forward direction.

61
2 .6 p-n junction diode under reverse bias

When an external voltage (V) is applied across the diode suchthat n-side
is positive and p-side is negative, it is said to bereverse biased[Fig.2-
12(a)]. The applied voltage mostlydrops across the depletion region. The
direction of applied voltage is sameas the direction of barrier potential.
As a result, the barrier height increasesand the depletion region widens
due to the change in the electric field.The effective barrier height under
reverse bias is (V0 + V), [Fig. 2-12(b)].This suppresses the flow of
electrons from n → p and holes from p → n.Thus, diffusion current,
decreases enormously compared to the diodeunder forward bias.The
electric field direction of the junction is such that if electrons onp-side or
holes on n-side in their random motion come close to thejunction, they
will be swept to its majority zone. This drift of carriersgives rise to
current. The drift current is of the order of a few μA. This isquite low
because it is due to the motion of carriers from their minorityside to their
majority side across the junction. The drift current is alsothere under

Fig. 2-12

forward bias but it is negligible (μA) when compared withcurrent due to

injected carriers which is usually in mA.The diode reverse current is not
very much dependent on the appliedvoltage. Even a small voltage is

62
sufficient to sweep the minority carriersfrom one side of the junction to
the other side of the junction. The current is not limited by the magnitude
of the applied voltage but islimited due to the concentration of the
minority carrier on eitherside of the junction.The current under reverse
bias is essentially voltageindependent up to a critical reverse bias voltage,
known asbreakdown voltage (Vbr). When V = Vbr, the diode reverse
currentincreases sharply. Even a slight increase in the bias voltage
causeslarge change in the current. If the reverse current is not limited
byan external circuit below the rated value (specified by themanufacturer)
the p-n junction will get destroyed. Once it exceedsthe rated value, the
diode gets destroyed due to overheating. Thiscan happen even for the
diode under forward bias, if the forwardcurrent exceeds the rated
value.The circuit arrangement for studying the V-Icharacteristicsof a
diode, (i.e., the variation of current as a function of appliedvoltage) are
shown in Fig. 2-13(a) and (b). The battery is connectedto the diode
through a potentiometer (or rheostat) so that theapplied voltage to the
diode can be changed. For different values bias to measure the current.
You can see in Fig. 2-13(c) that in forwardof voltages, the value of the
current is noted. A graph between Vand I is obtained as in Fig. 2-9(c).

Fig. 2-13

Note that in forward biasmeasurement, we use a milliammeter since the

expected current is large(as explained in the earlier section) while a

63
micrometer is used in reversebias to measure the current. You can see in
Fig. 2-13(c) that in forwardbias, the current first increases very slowly,
almost negligibly, till thevoltage across the diode crosses a certain value.
After the characteristicvoltage, the diode current increases significantly
(exponentially), even fora very small increase in the diode bias voltage.
This voltage is called thethreshold voltageor cut-in voltage (~0.2V for
germanium diode and~0.7 V for silicon diode).For the diode in reverse
bias, the current is very small (~μA) and almostremains constant with
change in bias. It is called reverse saturationcurrent. However, for
special cases, at very high reverse bias (break downvoltage), the current
suddenly increases. The general purpose diodes are notused beyond the
reverse saturation current region.The above discussion shows that the p-n
junction diode primarilyallows the flow of current only in one direction
(forward bias). The forwardbias resistance is low as compared to the
reverse bias resistance. Thisproperty is used for rectification of ac
voltages as discussed in the nextsection. For diodes, we define a quantity
called dynamic resistanceasthe ratio of small change in voltage ΔV to a
small change in current ∆I:

rd= V /I

2.6.1 Energy Bands of p-n junction at reverse bias

To reverse-bias the p-n junction, the p side is made more negative,

making it "uphill" for electrons moving across the junction (Fig.2-14).
The conduction direction for electrons in the diagram is right to left, and
the upward direction represents increasing electron energy.

Fig.2-14

64
In reverse bias the occupancy level for holes again tends to stay at the
level of the bulk p-type semiconductor while the occupancy level for
electrons follows that for the bulk n--type. In this case, the p-type bulk
band edges are raised relative to the n-type bulk by the reverse bias vR
(Fig.2-15), so the two bulk occupancy levels are separated again by an
energy determined by the applied voltage. As shown in the diagram, this
behavior means the step in band edges is increased to φ B+vR, and the
depletion region widens as holes are pulled away from it on the p-side
and electrons on the n-side.

When the reverse bias is applied, the electric field in the depletion region
is increased, pulling the electrons and holes further apart than in the zero
bias case. Thus, any current that flows is due to the very weak process of
carrier generation inside the depletion region due to generation-
recombination defects in this region. That very small current is the source
of the leakage current under reverse bias. In the photodiode, reverse
current is introduced using creation of holes and electrons in the depletion
region by incident light, thus converting a portion of the incident light
into an electric current.

When the reverse bias becomes very large, reaching the breakdown
voltage, the generation process in the depletion region accelerates leading
to an avalanche condition which can cause runaway and destroy the
diode.

Band-bending for p–n diode in reverse bias

Fig.2-15

Example

65
The V-Icharacteristic of a silicon diode is shown inthe Fig. 2-16.
Calculate the resistance of the diode at (a) ID= 15 mAand (b) VD= –10 V.

Solution
Considering the diode characteristics as a straight linebetween I = 10 mA
to I= 20 mA passing through the origin, we cancalculate the resistance
using Ohm‘s law.

(a) From the curve, at I= 20 mA, V= 0.8 V,I= 10 mA, V= 0.7 V

rfb= ΔV/ΔI= 0.1V/10 mA = 10 Ω

(b) From the curve at V = –10 V, I= –1 μA,

Therefore,
rrb= 10 V/1μA= 1.0 × 107 Ω

Fig. 2-16

2.6.2 Relations for Energy Bands in semiconductor Diode

66
When a N-type semiconductor crystal is joined to P-type semiconductor
crystal, we get the semiconductor p-n junction . The details of the
resultant energy band are displayed in Fig.2-17. As depicted from the
figure , the Fermi level is the same for both sides. If this level is not the
same , in this case energy of electrons in one side is greater than that in
the other side, at this situation electrons transport until the level be the
same in the two sides. Also the edges of conduction in the P-side .Ecp
Is not aligned with that in the N-side Ecn , this because Fermi level is near
from conduction band in the N-side, and is near to valiance band in the P-
side. Also edges of valiance band Evp andEvn are not aligned. The symbol
E0 denotes the displacement value in the energy levels where:

E0= Ecp - Ecn = Evp - Evn = E1 + E2 (5)

E0 represents the electron latent energy at the junction as shown in Fig.2-

5. From Fig.2-17 we can write the following relations:

EF - Evp= 1/2 EG - E1 (6)

Ecn - EF = 1/2 EG - E2 (7)

Fig.2-17

67
By summing the two relations 6 and 7 and substituting with the result in
relation 5 we get the following equation:

E0 = E1 + E2 = EG- (Ecn - EF ) - (EF - Evp) (8)

Using equations 10 , 17 and 18 of ch.1 we get the following relation :

np= ni2 = NcNv exp[-( Ec - Ev )/kT]

then:

EG = kT ln(NcNF/ ni2) (9)

Using relations 29 and 30 of ch.1 we get the following relations:

Ecn - EF= kT ln(Nc/ND) (10)

EF – Evp= kT ln(Nv/NA) (11)

Substituting from the above relations 9, 10 and 11 in equation 8 we get

the following relation:

E0 = kT { [ln(NcNF/ ni2)] – [ ln(ND /ND)] – [ln(Nv/NA)] }

then:

E0 = kT ln[(Nc Nv/ ni2)( ND /Nc) (NA/Nv)]

then:

E0 = kT ln(ND NA/ ni2) (12)

It is to be noted that this energy equals the multiplication of the value of

the barrier voltage V0and the electron charge e. So, if E0 measured in
electron-volt , then the value of V0 equals (numerically) the value of E0.

Equation 12 can be expressed in another form using relations 23 , 25, 26

, and 28 of ch.1 in equation 12 to get the following relation :

68
E0 = kT ln(pp/ pn) = kT ln(nn/ np) (13)

So, if :

pp = 1016/cm3 , pn = 104/cm3

and at room temperature kT= 0.026 ev,

then ,

E0 = 0.5 ev and hence :

V0= 0.5 ev

2.7 Current components of semiconductor diode

When applying voltage to a diode biased in forward direction (Fig.2-18
a), free electrons in the n-side (they are the majority carriers) drift to the
p-side to become there the minority carriers and diffuse away from the
junction region and its concentration decreases during diffusion because
of their recominatation with holes there.This is shown in Fig.2-18 b
where Inn is the drift current fromed by electrons of the n-side , while Inp

Fig.2-18

69
is the diffusion current formed by electrons of the p-side.

At the time of forming electrons current , there are holes (represent the
majority in the p-side) drift to the other side and they diffuse there as
minoruty carriers in the n-side and recombine with electrons there during
there diffusion. Inp in Fig.2-18 b is the drift current formed by holes in n-
side. Note that there is no difference between performance of electrons
and holes, only the adoping level is differ in the two sides , i.e:

Ipn ≠Inp

The total current I at any distance x is the sum of the driffusion current
formed by the minority carriers and the current formed by the majority
carriers.

The total current I = Ipp +Inp , so:

Ipp = I- Inp (14)

And also:

Inn = I- Ipn (15)

Summarize of the current component analysis in the forward direction is

that: the current enter the p-side is formed by holes while the current
leaves the n-side formed by electrons (Fig.2-18 b). The diode formed by
joining of two positive and negative crystals, has a current defined as
bipolar current.

At the reverse bias the explanation and description are similar to the case
of forward bias and the main difference is that the current components
shown in Fig.2-18 b move in reverse direction and their values are much
less than in forward bias.

Fig.2-19 represents distribution of minority carriers in forward bias.

70
 Minority-carrier distribution in a forward-biased pn junction. It is
assumed that the p region is more heavily doped than the n region.

Fig.2-19

2.8 Characteristics of of semiconductor diode

The current passing through a semiconductor diode in the case of
applying voltage difference V follow the following known equation :

I = I0 {[exp(V/η VT)] - 1} (16)

Where I0 is the reverse saturation current , η is an ideality factor

introduced to model a slower rate of increase than predicted by the ideal
diode law (in germanium η = 1 , in silicon equals 2). And as in the ch.1 ,
VT isvolt equivalent of temperature.
At room temperature , for germanium biased in forward direction and
when v is larger than 0.1 V , equation 16 is shorted to :

I = I0 {exp(39 V)} (17)

And when the diode is biased in reverse direction with volage that is
greater than VT(0.026 V ) then:

71
I = -I0 approximately (18)

Fig.2-20 shows the volt-ampere characteristics for the diode for both
forward and reverse bias. It is to be noted from this figure at the reverse
voltage ( reverse breakdown voltage) sudden change in the diode
characteristics which is not agree with equations 16 or 18 , this will be
explained before the end of this chapter.

Fig.2-20

Fig. 2-21 displays the difference between characteristics of germanium

and silicon diodes in the forward direction.

Fig.2-21
72
The important difference between them is in the value of the threshold
voltage , also called cutin voltage, it is the voltage below which the
current is very small. For germanium the threshold voltage equals
approximately 0.2 V while for silicon equals approximately 0.6 V. This
difference between the two threshold voltages (approximately 0.4 V) it's
reason is due to the saturation reverse current which in germanium is
greater 1000 timesthan that in silicon. The saturation reverse current in
germanium in the order of micro Amper ( μA) , while in silicon it is in
the order of nanoAmper (nA).

2.9 Temperatur Effect

Equation 16 above gives the characteristics of the diode. Such equation
depends on the temperature through the following two reasons:

1-The reverse saturation current I0 is generated by the minority carriers

which numers depend on intrinsic (pure) density ni that is much
changeable with temperature (equation 16 ch.1).
2-The voltage VT in the equation (Its value is given by relation 4 above)
and itis the volt equivalent of temperature and it is proportional to
temperature and its excitance in the equation 16 makes the characteristics
depend on temperature.

Equation 16 for forward bias can be written in the following simple form
when the value of V is sufficient to make exponential term is much
greater than 1:

I = I0 [exp(V/η VT)] (19)

Differentiate this equation with respect to T (considering V is constant):

dI/d T= (dI0/d T) [exp(V/η kT)] - (V/η kT) (I0) [exp(V/η kT)] (20)

It is find that the reverse saturation current I0 has multiple of its value in
germanium for every 8CO increasing in temperature while for silicon this
current has multiple of its value for every 5CO increasing in temperature.
Algthough change of current with temperature in silicon is more faster
than germanium, the current increase is acceptable in silicon and not for

73
germanium and the reason is refered to the smaller value of I0 in silicon
than germanium.

Finally the change of voltage across the diode with temperature dV/dT
can be calculated by fixing the forward current I. As for threshold voltage
( o.2 V for germanium , 0.6V for silicon) , it is found that change of
voltage with temperature is as follows:

In germanium : dV/dT = -2.1 mV/C0

In silicon: dV/dT = -2.3 mV/C0

The change of the characteristics of the semiconductor diode with

temperature is a disadvantage of such diodes , however this phenomena is
used sometimes in some thermal devices such as measure temperature or
its regulation.

2.10 Diode Resistance and Ideal Diode

The static resistance of the semiconductor diode R is defined as the ratio
of the voltage difference across the diode to the current passing in the
diode ( R = V/I).

At any point on the diode characteristic (Fig.2-20 for example) we can

find R which equals the voltage at this point divided by the current
produced at such point. The static resistance changes from one point to
another . This resistance is the second important one after the dynamic
resistance r which is given as follows:
r=dV/dI (21)

and it can be calculated from characteristic curve at any point by inverse

the slope at that point. Or in the case of forward bias use the following
equation :
I ≈ I0 [exp(39 V)]

dI≈ I0 [exp(39 V)] x 39 dV

r=dV/dI≈ (1/39)(1/I) (22)

If the constant η is introduced in the derivation (equation 19), so:

74
r=dV/dI≈ (η VT /I) (23)

Equation 22 can be written in the following form:

r≈ (26/I) (24)

Where the current I is measured in milli amper mA.

From equation 24 , we see that r is reverse proportional to current, so if

the forward current is 2mA , then r = 13 Ω and the resistance is reduced
to 1 Ω when the current is 26 mA.

The dynamic resistance in reverse direction is very high and this is

expected from the characteristic curves since the current in the reverse
direction is not greatly dependent on the voltage.

The characteristics of semiconductor diode in forward direction are the

nearest to ideal diode which is completely conducting in the case of
forward bias and is completely isolating in the case of reverse bias, this
means , the diode current is zero whatever the value of the reverse voltage
across the diode. Practically ideal diode is not exist.
The characteristics of semiconductor diode can be approximated to the
ideal ones where negecting the forward resistance , but permit drop
votage value ( for silicon 0.7 V or for germanium 0.3 V) across the
semiconductor diode. So, the characteristics of semiconductor diode in
forward direction are similar to that of ideal diode shown in Fig.2-22
where r is the dynamic resistance while R is the Static resistance but it
begins with the mentioned voltage drop and not begin with zero voltage.
In the reverse direction , the reverse characteristics of silicon diode are
the nearer for the ideal than that of germanium in the reverse direction,
and the reason of this is that the reverse saturation current in germanium
is larger than that for silicon.
At temperature (25 C0) , the reverse current approximately is(25 nA) for
the applied voltage of (20V) , for these conditions the reverse resistance
for the diode is:

R = 20/(25 x 10-9) = 800 MΩ

This resistance , for many applications , is considered as isolator.

If the temperature is increased to (100 C0), the reverse current becomes
(3μA) , so, the resistance of the diode becomes:
R = 20/(3 x 10-6) = 6.666 MΩ

75
 Fig.2-22

2.11 Transition an Diffusion capacitance

Electronic devices are inherently sensitive to very high frequencies. Most

shunt capacitiveeffects that can be ignored at lower frequencies because
the reactance XC:

XC= 1/2∏f C

XCis very large (open-circuit equivalent). This, however, cannot be

ignored atvery high frequencies. XCwill become sufficiently small due to
the high value of f tointroduce a low-reactance ―shorting‖ path. In the p-n
semiconductor diode, there aretwo capacitive effects to be considered.
Both types of capacitance are present in the forward- and reverse-bias
regions, but one so outweighs the other in each region thatwe consider the
effects of only one in each region.
In the reverse-bias region we have the transition- or depletion-region
capacitance(CT), while in the forward-bias region we have the diffusion
(CD) orstorage capacitance.
Recall that the basic equation for the capacitance of a parallel-plate
capacitor isdefined by:
C =εA/d

Where ε is the permittivity of the dielectric (insulator) betweenthe plates

of area Aseparated by a distance d. In the reverse-bias region there is a
depletionregion (free of carriers) that behaves essentially like an insulator
between thelayers of opposite charge. Since the depletion width (d) will

76
increase with increasedreverse-bias potential, the resulting transition
capacitance will decrease, as shown inFig2-24. The fact that the
capacitance is dependent on the applied reverse-bias potentialhas
application in a number of electronic systems.
Although the effect described above will also be present in the forward-
bias region, it is overshadowed by a capacitance effect directly dependent
on the rate atwhich charge is injected into the regions just outside the
depletion region. The resultis that increased levels of current will result in
increased levels of diffusion capacitance.However, increased levels of
current result in reduced levels of associated resistance(to be
demonstrated shortly), and the resulting time constant:

Т =RC

Which is very important in high-speed applications, does not become

excessive.
The capacitive effects described above are represented by a capacitor in
parallelwith the ideal diode, as shown in Fig. 2-25. For low- or mid-
frequency applications(except in the power area), however, the capacitor
is normally not included in thediode symbol.

Fig2-24

77
 Fig2-25

2.12 Load Line Analysis

The applied load will normally have an important impact on the point or
region ofoperation of a device. If the analysis is performed in a graphical
manner, a line canbe drawn on the characteristics of the device that
represents the applied load. The intersectionof the load line with the
characteristics will determine the point of operationof the system. Such
an analysis is, for obvious reasons, called load-line analysis. The load line
technique is an introduction offers the simplest application of the method.
It also permitsa validation of the approximate technique described
throughout the diode circuit analysis.
Consider the network of Fig.2-26a employing a diode having the
characteristicsof Fig. 2.26b. Note in Fig. 2.26a that the ―pressure‖
established by the battery is to establisha current through the series circuit
in the clockwise direction. The fact thatthis current and the defined
direction of conduction of the diode are a ―match‖ revealsthat the diode is
in the ―on‖ state and conduction has been established. The
resultingpolarity across the diode will be as shown and the first quadrant
(VD and IDpositive) of Fig. 2.26b will be the region of interest—the
forward-bias region.

78
 Fig. 2.26

Applying Kirchhoff‘s voltage law to the series circuit of Fig. 2.26a will
result in:

E - VD- VR= 0

Or

E =VD+ IDR (25)

The two variables of Eq. (25) (VDand ID) are the same as the diode axis
variables
of Fig. 2.26b. This similarity permits a plotting of Eq. (25) on the same
characteristicsof Fig. 2.1b.The intersections of the load line on the
characteristics can easily be determinedif one simply employs the fact
that anywhere on the horizontal axis ID= 0 A andanywhere on the vertical
axis VD= 0 V.
If we set VD = 0 V in Eq. (25) and solve for ID, we have the magnitude of
ID onthe vertical axis. Therefore, with VD = 0 V, Eq. (25) becomes:

E =VD+ IDR

= 0 V + IDR

and

79
 (26)

as shown in Fig. 2.27 If we set ID= 0 A in Eq. (25) and solve for VD, we
have themagnitude of VD on the horizontal axis. Therefore, with ID= 0 A,
Eq. (25) becomes
E =VD+ IDR
=VD+ (0 A)R

and

(27)

as shown in Fig. 2.27. A straight line drawn between the two points will
define theload line as depicted in Fig. 2.27. Change the level of R (the
load) and the intersectionon the vertical axis will change. The result will
be a change in the slope of the loadline and a different point of
intersection between the load line and the device characteristics.
We now have a load line defined by the network and a characteristic
curve definedby the device. The point of intersection between the two is
the point of operation for this circuit. By simply drawing a line down to
the horizontal axis the diodevoltage VDQ can be determined, whereas a

80
 Fig. 2.27

horizontal line from the point of intersectionto the vertical axis will
provide the level of IDQ. The current ID is actually thecurrent through the
entire series configuration of Fig. 2.1a. The point of operation isusually
called the quiescent point (abbreviated ―Q-pt.‖) to reflect its ―still,
unmoving‖qualities as defined by a dc network.The solution obtained at
the intersection of the two curves is the same that wouldbe obtained by a
simultaneous mathematical solution of Eqs. (25) and (16). Since the curve
for a diode has nonlinear characteristics the mathematicsinvolved would
require the use of nonlinear techniques that are beyond theneeds and
scope of this book. The load-line analysis described above provides a
solutionwith a minimum of effort and a ―pictorial‖ description of why the
levels of solutionfor VDQ and IDQ were obtained.

Example:
For the circuit and diode characteristics shown in Fig. 2.28:
determine:
(a) VDQ and IDQ.
(b) VR.

Fig. 2.28

Solution
(a) fromEq. (2.26):

81
ID = 10 V/ 1kΩ = 10 mA

from Eq. (2.27):

VD= 10 V

The resulting load line appears in Fig. 2.29. The intersection between the
load line andthe characteristic curve defines the Q-point as
VDQ= 0.78 V
IDQ= 9.25 mA
The level of VD is certainly an estimate, and the accuracy of ID is limited
by the chosenscale. A higher degree of accuracy would require a plot that
would be much largerand perhaps unwieldy.

(b) VR= IRR =IDQR = (9.25 mA)(1 kΩ) =9.25 V

or VR= E - VD= 10 V - 0.78 V =9.22 V
The difference in results is due to the accuracy with which the graph can
be read. Ideally,the results obtained either way should be the same.

Fig. 2.29

2.13 Other Types of Diodes

The nonlinear characteristics ofsemiconductor diode make it

important in many applications such as detecting , rectification ,
82
clipping, clamping , logic circuits ,….etc. There are semiconductor diodes
have their special applications , the following are some :

2.13.1 Varicap/Varactor diode

In the reverse bias of the p-n junction mentioned above , the width of the
depletion layer increases after the reverse voltage is applied to the diode.
The gap between the charges placed in the two sides of the junction :
positive and negative, along the ionized layer of the barrier potential,
such gap is similar to a capacitor has two parallel plates:

C =Q/V

Where C is the capacitance , Q is the charge, V is the voltage. The

symbol of theVaractor diode is shown in Fig. 2-30.

Fig. 2-30

As the reverse voltage applied to the diode increases , the distance

separate charges of the two sides increases i.e the distance between the
positive and negative charges(of the two sides) increases and this
situation is similar to increase the distance between tha two plates of the
condencer.

Generally the capacitance of two parallel plates is:

C =εA/d

whereε is the permittivity of the dielectric (insulator) betweenthe plates

of area Aseparated by a distance d.

83
 It is found that the capacitance produced by this diode is (approximately)
reversly proportional to the root of the reverse voltage applied to the
diode:

C = C0/√V =C0/(V)1/2 (25)

Where C0 is the diode capacitance before applying the voltage . Fig.2-31

Fig.2-31

The exact relation of such capacitance is:

C = K / (VT + VR)n

where K = constant determined by the semiconductor material and

constructiontechnique
VT = knee potential as defined before (thermal equivalent voltage)
VR = magnitude of the applied reverse-bias potential
n =1/2 for alloy junctions and 1/3for diffused junctions

displays the characteristics for the varactor diode relate the its capacitance
to the applied reverse voltage. So , this diode can be used as acapacitance
its vaule is variable electroncally not mechanicaqlly . This type of diodes
called diode of variable capacitance : varactor or varicap diode. The main
important use of this diode in tuning the resonant circuits at high
frequencies as well as in special amplifiers.

84
2.13.2 Zener Diode (Zener Effect – Zener breakdown)

It is noted from the diode characteristics at the reverse voltage that

sudden change in the characteristics. There isa point where the
application of too negative a voltage will result in a sharp changein the
characteristics, as shown in Fig. 2.20. The current increases at a very
rapid ratein a direction opposite to that of the positive voltage region. The
reverse-bias potentialthat results in this dramatic change in characteristics
is called the Zener potentialand is given the symbol VZ.

(1)Avalanch Effect
As the voltage across the diode increases in the reverse-bias region, the
velocityof the minority carriers( electrons from p →n andholes from n →
p. ) responsible for the reverse saturation current Iswill also
increase.Eventually, their velocity and associated kinetic energy [WK =
(1/2)mv2] will besufficient to release additional carriers through collisions
with otherwise stable atomicstructures. That is, an ionization process will
result whereby valence electrons absorbsufficient energy to leave the
parent atom. These additional carriers can then aid theionization process
to the point where a high avalanche current is established and
theavalanche breakdownregion determined.

(2) Zener Effect

The avalanche region (VZ) can be brought closer to the vertical axis by
increasingthe doping levels in the p- and n-type materials. However, as
VZdecreases to very lowlevels, such as-5 V, another mechanism, called
Zener breakdown, will contribute tothe sharp change in the
characteristic. It occurs because there is a strong electric fieldin the region
of the junction that can disrupt the bonding forces within the atom
and―generate‖ carriers. Although the Zener breakdown mechanism is a
significant contributoronly at lower levels of VZ, this sharp change in the
characteristic at any level iscalled the Zener regionand diodes employing
this unique portion of the characteristicof a p-n junction are called Zener
diodes (their symbols shown in Fig.2-32). The Zener region of the
semiconductor diode described must be avoided if the responseof a
system is not to be completely altered by the sharp change in
characteristicsin this reverse-voltage region.
The maximum reverse-bias potential that can be applied before entering
theZener region is called the peak inverse voltage (referred to simply as

85
the PIVrating) or the peak reverse voltage (denoted by PRV rating).If an
application requires a PIV rating greater than that of a single unit, a
numberof diodes of the same characteristics can be connected in series.
Diodes are alsoconnected in parallel to increase the current-carrying
capacity.

Fig.2-32

For the semiconductor diode the ―on‖ state will support a current in the
direction of the arrow in the symbol (Fig.2-20a). For the Zener diode the
direction of conductionis opposite to that of the arrow in the symbol .
Note also that the polarity of VDand VZare the same as would be
obtainedif each were a resistive element.
The location of the Zener region can be controlled by varying the doping
levels.An increase in doping, producing an increase in the number of
added impurities, willdecrease the Zener potential. Zener diodes are
available having Zener potentials of1.8 to 200 V with power ratings from
1/4 to 50 W. Because of its higher temperatureand current capability,
silicon is usually preferred in the manufacture of Zener diodes.The
complete equivalent circuit of the Zener diode in the Zener region
includesa small dynamic resistance and dc battery equal to the Zener
potential, as shown inFig. 2-33. For all applications to follow, however,
we shall assume as a first approximationthat the external resistors are
much larger in magnitude than the Zener-equivalentresistor and that the
equivalent circuit is simply the one indicated in Fig.2-33b.

86
 Fig. 2-33

(3) Zener diode as a voltage regulator

We know that when the ac input voltage of a rectifier fluctuates, its
rectifiedoutput also fluctuates. To get a constant dc voltage from the
dcunregulated output of a rectifier, we use a Zener diode. The circuit
diagramof a voltage regulator using a Zener diode is shown in Fig. 2-34.
The unregulated dc voltage (filtered output of arectifier) is connected to
the Zener diode through a seriesresistance Rs such that the Zener diode is
reverse biased.If the input voltage increases, the current through Rsand
Zener diode also increases. This increases thevoltage drop across Rs
without any change in thevoltage across the Zener diode. This is because
in thebreakdown region, Zener voltage remains constant eventhough the
current through the Zener diode changes.Similarly, if the input voltage
decreases, the currentthrough Rs and Zener diode also decreases. The
voltagedrop across Rs decreases without any change in thevoltage across
the Zener diode. Thus any increase /decrease in the input voltage results
in, increase/decrease of the voltage drop across Rs without anychange in
voltage across the Zener diode. Thus the Zener diode acts as a
voltage regulator. We have to select the Zener diode according to
therequired output voltage and accordingly the series resistance Rs.

87
 Fig. 2-34

Example

In a Zener regulated power supply a Zener diode withVZ= 6.0 V is used

for regulation. The load current is to be 4.0 mA andthe unregulated input
is 10.0 V. What should be the value of seriesresistor RS?

Solution

The value of RSshould be such that the current through the Zenerdiode is
much larger than the load current. This is to have good loadregulation.
Choose Zener current as five times the load current, i.e.,

IZ = 20 mA.

The total current through RSis, therefore, 24 mA. Thevoltage drop across
RSis :

VRS=10.0 – 6.0 = 4.0 V. This gives:

RS= 4.0V/(24 × 10–3) A =
= 167 Ω.

The nearest value of carbon resistoris 150 Ω. So, a series resistor of 150
Ω is appropriate.
Note that slightvariation in the value of the resistor does not matter, what
is importantis that the current IZ should be sufficiently larger than IL.

88
2.13.3 Tunnel Diodes

The tunnel diode was first introduced by Leo Esaki in 1958. Its
characteristics, shownin Fig. 2.35b, are different from any diode
discussed thus far in that it has a negativeresistanceregion. In this region,
an increase in terminal voltage results in a reduction
in diode current.
The tunnel diode is fabricated by doping the semiconductor materials that
willform the p-njunction at a level one hundred to several thousand times
that of a typicalsemiconductor diode. This will result in a greatly reduced
depletion region, ofthe order of magnitude of 10-6 cm, or typically about
(1/100) the width of this region fora typical semiconductor diode. It is
this thin depletion region that many carriers can―tunnel‖ through, rather
than attempt to surmount, at low forward-bias potentials thataccounts for
the peak in the curve of Fig. 2.35. For comparison purposes, a
typicalsemiconductor diode characteristic has been superimposed on the
tunnel-diode characteristicof Fig. 2.35b.
This reduced depletion region results in carriers ―punching through‖ at
velocities that far exceed those available with conventional diodes. The
tunnel diode can thereforebe used in high-speed applications such as in
computers, where switching timesin the order of nanoseconds or
picoseconds are desirable.The diode symbol is shown in Fig. 2.35a
You will recall that an increase in the doping level will dropthe Zener
potential. Note the effect of a very high doping level on this region in
Fig.2.35. The semiconductor materials most frequently used in the
manufacture of tunneldiodes are germanium and gallium arsenide. The
ratio IP/IVis very important forcomputer applications. For germanium, it is
typically 10:1, while for gallium arsenide,it is closer to 20:1.
The peak current, IP, of a tunnel diode can vary from a few microamperes
to severalhundred amperes. The peak voltage, however, is limited to
about 600 mV. Forthis reason, a simple VOM (Voltmeter)with an internal
dc battery potential of 1.5 V can severelydamage a tunnel diode if applied
improperly.

89
 Fig.2.35

2.13.4 Schottky Barrier (Hot-carrier) Diodes

In recent years, there has been increasing interest in a two-terminal device

referredto as a Schottky-barrier, surface-barrier, or hot-carrier diode. Its
areas of applicationwere first limited to the very high frequency range
due to its quick response time (especiallyimportant at high frequencies)
and a lower noise figure (a quantity of realimportance in high-frequency
applications). In recent years, however, it is appearingmore and more in
low-voltage/high-current power supplies and ac-to-dc converters.Other
areas of application of the device include radar systems, Schottky TTL
logicfor computers, mixers and detectors in communication equipment,
instrumentation,and analog-to-digital converters.
Its construction is quite different from the conventional p-n junction in
that a metalsemiconductorjunction is created. The semiconductor
isnormally n-type silicon (although p-type silicon is sometimes used),
while a host ofdifferent metals, such as molybdenum, platinum, chrome,
or tungsten, are used. Differentconstruction techniques will result in a
different set of characteristics for thedevice, such as increased frequency

90
range, lower forward bias, and so on. Prioritiesdo not permit an
examination of each technique here, but information will usually
beprovided by the manufacturer. In general, however, Schottky diode
construction resultsin a more uniform junction region and a high level of
ruggedness.
In both materials, the electron is the majority carrier. In the metal, the
level of minoritycarriers (holes) is insignificant. When the materials are
joined, the electrons inthe n-type silicon semiconductor material
immediately flow into the adjoining metal,establishing a heavy flow of
majority carriers. Since the injected carriers have a veryhigh kinetic
energy level compared to the electrons of the metal, they are
commonlycalled ―hot carriers.‖ In the conventional p-n junction, there
was the injection of minoritycarriers into the adjoining region. Here the
electrons are injected into a regionof the same electron plurality. Schottky
diodes are therefore unique in that conductionis entirely by majority
carriers. The heavy flow of electrons into the metal createsa region near
the junction surface depleted of carriers in the silicon material—much
like the depletion region in the p-n junction diode. The additional carriers
inthe metal establish a ―negative wall‖ in the metal at the boundary
between the twomaterials. The net result is a ―surface barrier‖ between
the two materials, preventingany further current. That is, any electrons
(negatively charged) in the silicon materialface a carrier-free region and a
―negative wall‖ at the surface of the metal.
The application of a forward bias as shown in the first quadrant of Fig.
2.36willreduce the strength of the negative barrier through the attraction
of the applied positivepotential for electrons from this region. The result
is a return to the heavy flowof electrons across the boundary, the
magnitude of which is controlled by the levelof the applied bias potential.
The barrier at the junction for a Schottky diode is lessthan that of the p-n
junction device in both the forward- and reverse-bias regions. Theresult is
therefore a higher current at the same applied bias in the forward-
andreverse-bias regions. This is a desirable effect in the forward-bias
region but highlyundesirable in the reverse-bias region.

91
 Fig. 2.36

The exponential rise in current with forward bias is described by Eq. (16)
butwith η dependent on the construction technique (1.05 for the metal
whisker type ofconstruction, which is somewhat similar to the germanium
diode). In the reverse-biasregion, the current Isis due primarily to those
electrons in the metal passing into thesemiconductor material. One of the
areas of continuing research on the Schottky diodecenters on reducing the
high leakage currents that result withtemperatures over 100°C.Through
design, improvement units are now becoming available that have a
temperaturerange from -65 to +150°C. At room temperature, Isis typically
in the microampererange for low-power units and milliampere range for
high-power devices,although it is typically larger than that encountered
using conventional p-njunctiondevices with the same current limits. In
addition, the PIV of Schottkydiodes is usuallysignificantly less than that
of a comparable p-njunction unit. Typically, for a50-A unit, the PIV of
the Schottky diode would be about 50 V as compared to 150 Vfor the p-
njunction variety. Recent advances, however, have resulted in
Schottkydiodes with PIVs greater than 100 V at this current level. It is
obvious from the characteristicsof Fig. 2.36that the Schottky diode is
closer to the ideal set of characteristicsthan the point contact and has
levels of VTless than the typical silicon semiconductorp-njunction. The
level of VTfor the ―hot-carrier‖ diode is controlled to alarge measure by
the metal employed. There exists a required trade-off between
temperaturerange and level of VT. An increase in one appears to
correspond to a resultingincrease in the other. In addition, the lower the
range of allowable current levels,the lower the value of VT. For some
low-level units, the value of VTcan be assumedto be essentially zero on

92
an approximate basis. For the middle and high range, however,a value of
0.2 V would appear to be a good representative value.
The maximum current rating of the device is presently limited to about 75
A, although100-A units appear to be on the horizon. One of the primary
areas of applicationof this diode is in switching power suppliesthat
operate in the frequency rangeof 20 kHz or more. A typical unit at 25°C
may be rated at 50 A at a forward voltageof 0.6 V with a recovery time of
10 ns for use in one of these supplies. A p-njunctiondevice with the same
current limit of 50 A may have aforward voltage dropof 1.1 V and a
recovery time of 30 to 50 ns. The difference in forward voltage maynot
appear significant, but consider the power dissipation difference: Phot
carrier; (0.6 V)(50 A) = 30 W compared to:

Pp-n= (1.1 V)(50 A) = 55 W

which is a measurabledifference when efficiency criteria must be met.

There will, of course, be ahigher dissipation in the reverse-bias region for
the Schottky diode due to the higherleakage current, but the total power
loss in the forward- and reverse-bias regions isstill significantly improved
as compared to the p-njunction device.
Recall from our discussion of reverse recovery time for the
semiconductor diodethat the injected minority carriers accounted for the
high level of trr(the reverse recoverytime). The absence of minority
carriers at any appreciable level in the Schottkydiode results in a reverse
recovery time of significantly lower levels, as indicatedabove. This is the
primary reason Schottky diodes are so effective atfrequencies
approaching 20 GHz, where the device must switch states at a very
highrate. For higher frequencies the point-contact diode, with its very
small junctionarea, is still employed.
The approximate equivalent circuit (the ideal inparallel with the junction
capacitance) for the device and its symbol Fig. 2.37.

93
 Fig. 2.37

2.13.5 Gunn Diode

(1)Introduction:
We present Gunn device as a low power microwave oscillator. It is a
negative resistance solid state device ,often used as a local oscillator.apart
from economic factors the requirements of an oscillator include:
-Excellent frequency stability , i.e negligible variation the frequency of
oscillations due to variations in temperature, power supply voltage and
the oscillator loading (load pulling).
-Adequate power output fo the intended use.
-Low amplitude , phase and frequency modulation noise.
-Variable tuning including mechanical tuning and voltage control.
Capability to be modulated in amplitude(AM), frequency (FM), or
phase(PM).
-simple circuit requirements.
A variable frequency oscillator (VFO) whose frequency is varied by
means od an applied control voltage is called a voltage controlled
oscillator(VCO).
-Good frequency stability and low noise are obtained by employing a
high –Q resonator in the oscillator circuit . The resonator should have a
resonant frequency that is insensitive to the variations in the ambient
temperature and this usually translates into low thermal expansion of the
resonator. For critical applications the resonator may be placed in a
temperature controlled oven.
The frequency of an resonator will vary with the dc bias voltages that are
applied . This effect called " oscillator pushing" and can sometimes be
used to advantage to fine-tune an oscillator over a narrow band of
frequencies.

94
frequency ofoscillation is determined by resonantfrequencyof the input
and output networks. Consequently any change in the impedance of the
load connected to the oscillator will result in a change in the oscillator
frequency . This effect which is referred to as oscillator loadpulling is
usually undesirable . The pulling effect can be minimized by using loose
coupling between the oscillator and the load i.e the external Q-should be
large. A disadvantage of use loose coupled load impedance is that the
output power will be smaller and the oscillator efficiency will be reduced.
Load pulling can be minimized by using a very high Q-resonator as the
main frequency –determing element in the oscillator circuit.

(2) Gunn Oscillators

Semiconductor materials from view point of energy bands can be

classified to two types :direct and indirect (Fig.2-38). Some bulk
semiconductor materials such as gallium arsenide (Ga As), indium
ohosphide (InP) and cadmium telluride (Cd Te) have two closely spaced
energy bands in the conduction band. A typical energy E versus
momentum(k) band structure is shown in Fig 2-39.

Fig 2-38

At low electric field strengths in the material , most of the electrons will
be located in the low energy band. At high electric field strengths, most
of the electrons will be transferred to the high energy band. In thehigh
energy band the effective electron mass is larger and hence the electron
mobility is lower than what it is in the low-energy band. Since the
conductivity is directly proportional to the mobility, there is a an
intermediate range of electric field strengths for which the fraction of

95
electrons that are transferred to the high energy low mobility conduction
band is such that the average mobility and hence conductivity decreases
with an increase in electric field strength. Thus there is a range of applied
voltages over which the current decreases with increasing voltage and a
negative increment resistance is displayed by the device.

Fig 2-39. Conduction band in some semiconductors

A typical current-voltage characteristics for a Gunn device is shown in

Fig.2-40. Gunn device is so called a transferred –electron device since the
negative resistance arises from the transfer of electrons from the low to
the high energy bands.

Fig.2-40 current-voltage characteristics for a Gunn device

The oscillation that occurs in the materiak with the energy band structure
noted above was discovered by J.B Gunn. The possibility of obtaining

96
negative differential resistance gad been predicted earlier by Ridley and
Watkins.

There are two principle modes of operation that result in oscillations for
Gunn device.

(3) The First mode is: transit time mode:

When the applied voltage exceeds the threshold value , a dipole domain
(a region of electron concentration and depletion) forms near the cathode
end with most of the voltage drop appearing across the high resistance
part of the device. A short section of the input region is in the low energy
high mobility state and electrons leave the cathode with a large velocity.
At the point in the material that separates the high mobility and low
mobility states, electrons accumulate on the left side and are depleted on
the right side by virtue of the different mobilities. This dipole
arrangement of charge is shown in Fig.2-41. This dipole domain sweeps
across the device and when it arrives at the anode , the device is in a high
mobility state and a new dipole domain forms at the cathode end and
moves toward the anode. This mechanism is self repeating and represents
an oscillation with a period equal to the transit time. This mode of
oscillation has a low efficiency (a few percentages) of power generation
and a frequency that cannot be controlled by the external circuit. This
mode of oscillation called transit time mode or Gunn mode.

Fig.2-41 Simple circuit for Gunn oscillator operate in the oscillation

mode type: transit time

(4) Limited –space charge accumulation (LSA) mode

97
This is the second mode of operatrion of Gunn oscillator. Operatrion of
Gunn oscillator in the LSA mode can produce several watts of power
with efficiencies of around 20% or more. The power outpus that have
been obtained decrease with frequency and are below 1 W at frequencies
greater than 10 GHz , output power of several milliwatts can be obtained.
In LSA mode the Gunn device is incorporated as part of a resonant circuit
as shown in Fig.2-42.

Fig.2-42: A basic Gunn oscillator operating in the LSA mode

The frequency of the resonant circuit is adjusted so that it is several times

greater than that of the first mode (transit time mode). As a consequence ,
dipole domain do not have sufficient time to form and the device operates
essentially as a negative resistance device. The dc bias is adjusted to a
value somewhat greater than the threshold voltage. The RF voltage of the
oscillations will build up to a peak-peak value approximately equal to the
voltage increment over which the device resistance is negative as shown
in Fig.2-43. The resonator loading represented by the resistor R , is
adjusted to a value about 20% greater than the maximum negative
resistance of the device. This will ensure that oscillations will start. The
amplitude of the oscillations will build up until the average negative
resistance of the Gunn diode becomes equal to the resonator resistance R.

(5) Quenched –domain mode

If the resonator frequency is adjusted to a value slightly above that of
thetransit -time- mode, the Gunn device will operate very much like the
basic Gun mode , but the dipole dimain will be quenched before it arrives
at the anode by the negative –going oscillation voltage. This type of
operating mode is called a quenched –domain mode (Fig.2-44).

98
 Fig.2-43 Radio frequency voltage for oscillation across Gunn device
operates in LSA mode

Fig.2-44 Quenched –domain mode

(6) Delayed(inhibited) mode

Oscillations can also occur by adjusting the resonator frequency , so that
it is lower than frequency of the Gunn diode. In this case the dipole
domain have sufficient to sweep across the device and arrive at the anode.
However , the initiation of a new dipole domain is delayed until the
oscillation voltage rises above the threshold value. This mode of
operation is called the inhibited or delayed mode (Fig.2-45).

99
 Fig.2-45: delayed mode

2.13.6 Photodiode
A Photodiode is again a special purpose p-njunction diode fabricated with
a transparentwindow to allow light to fall on the diode. It isoperated
under reverse bias. When the photodiodeis illuminated with light
(photons) with energy (hv)greater than the energy gap (Eg) of
thesemiconductor, then electron-hole pairs aregenerated due to the
absorption of photons. Thediode is fabricated such that the generation of
e-h pairs takes place in or near the depletion regionof the diode. Due to
electric field of the junction,electrons and holes are separated before they
recombine. The direction of the electric field is suchthat electrons reach
n-side and holes reach p-side.Electrons are collected on n-side and holes
arecollected on p-side giving rise to an emf. When anexternal load is
connected, current flows. Themagnitude of the photocurrent depends on
theintensity of incident light (photocurrent isproportional to incident light
intensity).
It is easier to observe the change in the currentwith change in the light
intensity, if a reverse biasis applied. Thus photodiode can be used as
aphotodetector to detect optical signals.Fig.2-46 showns the circuit
symbol of the photo diode and the reverse circuit of its connection. The
circuitdiagram used for the measurement of I-Vcharacteristics of a
photodiode is shown inFig. 2-47(a) and a typical I-V characteristics in
Fig. 2-47(b).

Fig.2-46

100
 Fig. 2-47

Example
The current in the forward bias is known to be more(~mA) than the
current in the reverse bias (~μA). What is the reasonthen to operate the
photodiodes in reverse bias?

Solution

Consider the case of an n-type semiconductor. Obviously,the majority

carrier density (n) is considerably larger than theminority hole density p
(i.e., n >> p). On illumination, let the excesselectrons and holes generated
be Δn and Δp, respectively:

n′ = n + Δn

p′ = p + Δp

Here n′ andp′ are the electron and hole concentrations* at anyparticular

illumination and n and p are carriers concentration whenthere is no
illumination. Remember Δn = Δp and n >> p. Hence, thefractional change
in the majority carriers (i.e., Δn/n) would be muchless than that in the
minority carriers (i.e., Δp/p). In general, we canstate that the fractional
change due to the photo-effects on theminority carrier dominated
reverse bias current is more easilymeasurable than the fractional change
in the forward bias current.Hence, photodiodes are preferably used in the
reverse bias conditionfor measuring light intensity.

101
* Note that, to create an e-h pair, we spend some energy (photo
excitation, thermalexcitation, etc.). Therefore when an electron and hole
recombine the energy isreleased in the form of light (radiative
recombination) or heat (non-radiative recombination). It depends on
semiconductor and the method of fabrication ofthe p-n junction. For the
fabrication of LEDs, semiconductors like GaAs, GaAs-GaP are used in
which radiative recombination dominates.

2.13.7 Light emitting diode (LED)

It is a heavily doped p-n junction which under forward bias
emitsspontaneous radiation. The diode is encapsulated with a
transparentcover so that emitted light can come out.
When the diode is forward biased, electrons are sent from n → p (where
they are minority carriers) and holes are sent from p → n (where they are
minority carriers). At the junction boundary the concentration of minority
carriers increases compared to the equilibrium concentration (i.e.,
whenthere is no bias). Thus at the junction boundary on either side of
thejunction, excess minority carriers are there which recombine with
majoritycarriers near the junction. On recombination, the energy is
released inthe form of photons. Photons with energy equal to or slightly
less thanthe band gap are emitted. When the forward current of the diode
is small,the intensity of light emitted is small. As the forward current
increases,intensity of light increases and reaches a maximum. Further
increase inthe forward current results in decrease of light intensity. LEDs
are biasedsuch that the light emitting efficiency is maximum. The circuit
symbol for the light emitting diode is shown in Fig.2-48.

Fig.2-48. Circuit symbol for the light emitting diode.

The V-I characteristics of a LED is similar to that of a Si junctiondiode.

But the threshold voltages are much higher and slightly differentfor each
colour. The reverse breakdown voltages of LEDs are very low,typically
around 5V. So care should be taken that high reverse voltagesdo not
appear across them.

102
LEDs that can emit red, yellow, orange, green and blue light
arecommercially available. The semiconductor used for fabrication of
visible
LEDs must at least have a band gap of 1.8 eV (spectral range of
visiblelight is from about 0.4 μm to 0.7 μm, i.e., from about 3 eV to 1.8
eV). Thecompound semiconductor Gallium Arsenide – Phosphide
(GaAs1–xPx) isused for making LEDs of different colours. GaAs0.6 P0.4
(Eg ~ 1.9 eV) isused for red LED. GaAs (Eg ~ 1.4 eV) is used for making
infrared LED.These LEDs find extensive use in remote controls, burglar
alarm systems,optical communication, etc. Extensive research is being
done for developing white LEDs which can replace incandescent lamps.
LEDs have the following advantages over conventional incandescentlow
power lamps:
(i) Low operational voltage and less power.
(ii) Fast action and no warm-up time required.
(iii) The bandwidth of emitted light is 100 Å to 500 Å or in other words it
is nearly (but not exactly) monochromatic.
(iv) Long life and ruggedness.
(v) Fast on-off switching capability.

2.13.8 Solar cell

A solar cell is basically a p-n junction whichgenerates emf when solar
radiation falls on thep-n junction. It works on the same
principle(photovoltaic effect) as the photodiode, except thatno external
bias is applied and the junction areais kept much larger for solar radiation
to be incident because we are interested in more power.
A simple p-n junction solar cell is shown inFig. 2-49.

Fig. 2-49.A simple p-n junction solar cell

103
A p-Si wafer of about 300 μm is taken overwhich a thin layer (~0.3 μm)
of n-Si is grown onone-side by diffusion process. The other side ofp-Si is
coated with a metal (back contact). On thetop of n-Si layer, metal finger
electrode (or metallicgrid) is deposited. This acts as a front contact.
Themetallic grid occupies only a very small fractionof the cell area
(<15%) so that light can be incidenton the cell from the top.
The generation of emf by a solar cell, when light falls on, it is due to
the following three basic processes: generation, separation and
collection—
(i) generation of e-h pairs due to light (with hν>Eg)close to the
junction;(ii) separation of electrons andholes due to electric field of the
depletion region.Electrons are swept to n-side and holes to p-side;
(iii) the electrons reaching the n-side are collected bythe front contact and
holes reaching p-side are collectedby the back contact. Thus p-side
becomes positive andn-side becomes negative giving rise to
photovoltage.
When an external load is connected as shown inthe Fig. 2-50(a) a
photocurrent IL flows through theload. A typical I-V characteristics of a
solar cell is shownin the Fig. 14.25(b).

Fig.2-50 External load is connected tosolar cell and itsI – Vcharacteristics

Note that the I – V characteristics of solar cell isdrawn in the fourth

quadrant of the coordinate axes.This is because a solar cell does not draw
current butsupplies the same to the load.

104
Semiconductors with band gap close to 1.5 eV areideal materials for solar
cell fabrication. Solar cells aremade with semiconductors like Si (Eg = 1.1
eV), GaAs(Eg = 1.43 eV), CdTe (Eg= 1.45 eV), CuInSe2 (Eg = 1.04eV),
etc. The important criteria for the selection of amaterial for solar cell
fabrication are;
(i) band gap (~1.0to 1.8 eV),
(ii) (ii) high optical absorption (~104 cm–1),
(iii) electrical conductivity,
(iv) availability of the rawmaterial, and (v) cost.
Note that sunlight is not alwaysrequired for a solar cell. Any light with
photon energiesgreater than the bandgap will do. Solar cells are usedto
power electronic devices in satellites and spacevehicles and also as power
supply to some calculators. Production oflow-cost photovoltaic cells for
large-scale solar energy is a topicfor research.

Example
Why are Si and GaAs are preferred materials forsolar cells?

Solution
The solar radiation spectrum received by us is shown inFig. 2-51.The
maxima is near 1.5 eV. For photo-excitation, hν>Eg.
Hence,semiconductor with band gap ~1.5 eV or lower is likely to give
bettersolar conversion efficiency. Silicon has Eg ~ 1.1 eV while for GaAs
it is
~1.53 eV. In fact, GaAs is better (in spite of its higher band gap) thanSi
because of its relatively higher absorption coefficient. If we
choosematerials like CdS or CdSe (Eg ~ 2.4 eV), we can use only the
highenergy component of the solar energy for photo-conversion and
asignificant part of energy will be of no use.
The question arises: why we do not use material like PbS (Eg ~ 0.4
eV)which satisfy the condition hν>Egfor ν maxima corresponding to
thesolar radiation spectra? If we do so, most of the solar radiation will
beabsorbed on the top-layer of solar cell and will not reach in or nearthe
depletion region. For effective electron-hole separation, due tothe
junction field, we want the photo-generation to occur in thejunction
region only.

105
 Fig. 2-51

2.14 Sinusoidal Inputs; Half –Wave Rectifier

The diode analysis will now be expanded to include time-varying

functions such asthe sinusoidal waveform and the square wave. There is
no question that the degree ofdifficulty will increase, but once a few
fundamental maneuvers are understood, theanalysis will be fairly direct
and follow a common thread.
The simplest of networks to examine with a time-varying signal appears
in Fig.2.52. For the moment we will use the ideal model (note the absence
of the Si or Gelabel to denote ideal diode) to ensure that the approach is
not clouded by additionalmathematical complexity.

Fig.2.52

106
Over one full cycle, defined by the period T of Fig. 2.52, the average
value (thealgebraic sum of the areas above and below the axis) is zero.
The circuit of Fig. 2.52,called a half-wave rectifier, will generate a
waveform vo that will have an averagevalue of particular, use in the ac-to-
dc conversion process. When employed in the rectificationprocess, a
diode is typically referred to as a rectifier. Its power and currentratings
are typically much higher than those of diodes employed in other
applications,such as computers and communication systems.
During the interval t = 0 → T/2 in Fig. 2.52 the polarity of the applied
voltage viis such as to establish ―pressure‖ in the direction indicated and
turn on the diode withthe polarity appearing above the diode. Substituting
the short-circuit equivalence forthe ideal diode will result in the
equivalent circuit of Fig. 2.53, where it is fairly obviousthat the output
signal is an exact replica of the applied signal. The two terminalsdefining
the output voltage are connected directly to the applied signal via
theshort-circuit equivalence of the diode.

Fig. 2.53

For the period T/2 → T, the polarity of the input vi is as shown in Fig.
2.54 andthe resulting polarity across the ideal diode produces an ―off‖
state with an open-circuitequivalent. The result is the absence of a path
for charge to flow and vo= iR = (0)R= 0 V for the period T/2 → T. The
input viand the output vowere sketched together
in Fig. 2.55 for comparison purposes. The output signal vo now has a net
positivearea above the axis over a full period and an average value
determined by :

Vdc= 0.318Vmhalf-wave (26)

107
 Fig. 2.54

Fig. 2.55

The process of removing one-half the input signal to establish a dc level

is aptlycalled half-wave rectification.
The effect of using a silicon diode with:

108
VT= 0.7 V is demonstrated in Fig. 2.56for the forward-bias region. The
applied signal must now be at least 0.7 V before thediode can turn ―on.‖
For levels of vi less than 0.7 V, the diode is still in an opencircuitstate and
vo= 0 V as shown in the same figure. When conducting, the
differencebetween voand vi is a fixed level of VT= 0.7 V and:
vo= vi -VT,as shown inthe figure. The net effect is a reduction in area
above the axis, which naturally reducesthe resulting dc voltage level. For
situations where Vm>>VT, Eq. 2.8 can be appliedto determine the
average value with a relatively high level of accuracy.
Vdc= 0.318(Vm- VT) (27)
In fact, if Vm is sufficiently greater than VT, Eq. 26 is often applied as a
first approximationfor Vdc.

Fig. 2.56

Example
(a) Sketch the output vo and determine the dc level of the output for
thenetwork ofFig. 2.57.
(b) Repeat part (a) if the ideal diode is replaced by a silicon diode.
(c) Repeat parts (a) and (b) if Vm is increased to 200 V and compare
solutions usingEqs. (26) and (27).

109
 Fig. 2.57
Solution
(a) In this situation the diode will conduct during the negative part of
the input as shown in Fig. 2.58, and vo will appear as shown in the
same figure. For the full period, the dc level is:

Vdc= -0.318Vm= -0.318(20 V) = -6.36 V

The negative sign indicates that the polarity of the output is opposite to
the definedpolarity of Fig. 2.57.
(b) Using a silicon diode, the output has the appearance of Fig. 2.59 and
Vdc≡-0.318(Vm- 0.7 V)= - 0.318(19.3 V) =-6.14 V

Fig. 2.58

110
 Fig. 2.59

The resulting drop in dc level is 0.22 V or about 3.5%.

(c) Eq. (26): Vdc= -0.318Vm = -0.318(200 V) = -63.6 V
Eq. (2.8): Vdc= -0.318(Vm - VT) = - 0.318(200 V - 0.7 V)
= - (0.318)(199.3 V) = -63.38 V

2.15 Full –Wave Rectification

2.15.1 Bridge Network

The dc level obtained from a sinusoidal input can be improved 100%
using a processcalled full-wave rectification. The most familiar network
for performing such a functionappears in Fig. 2.60 with its four diodes in
a bridge configuration. During theperiod t =0 to T/2 the polarity of the
input is as shown in Fig. 2.61. The resultingpolarities across the ideal
diodes are also shown in Fig. 2.62 to reveal that D2 and D3are conducting
while D1 and D4 are in the ―off‖ state. The net result is the configuration
of Fig. 2.62, with its indicated current and polarity across R. Since the
diodesare ideal the load voltage is vo= vi, as shown in the same figure.

Fig. 2.60

111
 Fig. 2.61

Fig. 2.62

For the negative region of the input the conducting diodes are D 1 and D2,
resultingin the configuration of Fig. 2.63. The important result is that the
polarity acrossthe load resistor R is the same as in Fig. 2.60, establishing
a second positive pulse,as shown in Fig. 2.63. Over one full cycle
theinput and output voltages will appearas shown in Fig. 2.64.

112
 Fig. 2.63

Fig. 2.64

Since the area above the axis for one full cycle is now twice that obtained
for ahalf-wave system, the dc level has also been doubled and;

Vdc= 2(Eq. 26) = 2(0.318Vm)Or

(28)

If silicon rather than ideal diodes are employed as shown in Fig. 2.65, an
applicationof Kirchhoff‘s voltage law around the conduction path would
result in:
vi- VT-vO- VT= 0

andvO=vi-2VT
The peak value of the output voltage vOis therefore
Vomax≡Vm- 2VT

113
For situations where Vm>>2 VT, Eq. (29) can be applied for the average
value witha relatively high level of accuracy.

(29)

Fig. 2.65

Then again, if Vm is sufficiently greater than 2 VT, then Eq. (28) is often
applied asa first approximation for Vdc.

2.15.2 Center-Tapped Transformer

A second popular full-wave rectifier appears in Fig. 2.66 with only two
diodes butrequiring a center-tapped (CT) transformer to establish the
input signal across eachsection of the secondary of the transformer.
During the positive portion of vi appliedto the primary of the transformer,
the network will appear as shown in Fig. 2.66. D1assumes the short-
circuit equivalent and D2 the open-circuit equivalent, as determinedby the
secondary voltages and the resulting current directions. The output
voltage appearsas shown in Fig. 2.67.

114
 Fig. 2.66

Fig. 2.67

During the negative portion of the input the network appears as shown in
Fig.2.68, reversing the roles of the diodes but maintaining the same
polarity for the voltage across the load resistor R. The net effect is the
same output as that appearing inFig. 2.56 with the same dc levels.

115
 Fig. 2.68

Example
Determine the output waveform for the network of Fig. 2.69 and calculate
the outputdc level.

Fig. 2.69

Solution
The network will appear as shown in Fig. 2.70 for the positive region of
the inputvoltage. Redrawing the network will result in the configuration
of Fig. 2.71, where
vo=(1/2) vi or

116
Vomax=(1/2) _Vimax= (1/2)(10 V) = 5 V, as shown in Fig. 2.71. For the
negativepart of the input the roles of the diodes will be interchanged and
vowill appear asshown in Fig. 2.72.

Fig. 2.70

Fig. 2.71

117
 Fig. 2.72

The effect of removing two diodes from the bridge configuration was
therefore toreduce the available dc level to the following:

Vdc= 0.636(5 V) =3.18 V

or that available from a half-wave rectifier with the same input.

.

2.15.3 Full Wave Rectifier with Capavcitive Filtering

Now we shall discuss the role ofcapacitor in filtering. When the voltage
across the capacitor is rising, it getscharged. If there is no external load, it
remains charged to the peak voltageof the rectified output. When there is
a load, it gets discharged throughthe load and the voltage across it begins
to fall. In the next half-cycle ofrectified output it again gets charged to the
peak value (Fig. 2.73). Therate of fall of the voltage across the capacitor
depends upon the inverseproduct of capacitor C and the effective
resistance RL used in the circuitand is called the time constant. To make
the time constant large value ofC should be large. So capacitor input
filters use large capacitors. Theoutput voltage obtained by using capacitor
input filter is nearer to thepeak voltage of the rectified voltage. This type
of filter is most widelyused in power supplies.

118
 Fig. 2.73

2.16 Clamping Circuits

Certain applications in electronics require that the upper or lower
extremity of a wave be fixed at a specific value In such applications, a
clamping/clamper circuits are used.

A circuit that places either the positive or negative peak of a signal at a

desired D.C level is known as a clamping circuit. A clamping circuit
introduces (or restores) a D.C level to an A.C signal. Thus a clamping
circuit is also known as D.C restorer, or D.C reinserted or a baseline
stabilizer. The following are two general types of clamping.

119
 1. Positive clamping occurs when negative peaks raised or clamped to
ground or on the zero level In other words, it pushes the signal
upwards so that negative peaks fall on the zero level.
2. Negative clamping occurs when positive peaks raised or clamped
to ground or on the zero level In other words, it pushes the signal
downwards so that the positive peaks fall on the zero level.

In both cases the shape of the original signal has not changed, only there
is vertical shift in the signal Fig. 2.74 shows the clamping wave form.

Fig. 2.74

2.16.1 Diode clampers

(1) Positive Clamper

Fig 2.75 shows the circuit of a positive clamper It consists of a diode and
a capacitor the clamper output is taken across the load resistance R.

Fig 2.75

During the negative half cycle of the input voltage, the diode conducts
heavily and behaves as a closed switch At the negative peak, the
120
capacitor is charged to maximum voltage V slightly beyond the negative
peak, the diode is shunt off and the capacitor charged to Vm behaves as a
battery during the positive half cycle of the input signal. The diode is
reversed biased and the output voltage will be equal to Vm + V this gives
positive clamped voltage and is called positive clamper circuit.

(2) Positive clamper with bias

Biased clamper circuit operates in exactly the same manner as unbiased
clampers. The difference is only that a dc bias voltage is add in series
with the diode and resistor. A biased clamper means that the clamping
can be done at any voltage level other than zero (Fig.76).

Fig.2.76

Fig 2.76(a) shows the circuit of positive clamper with positive biased
Here a battery of 10 V is added in such a way that the clamping take
place positively at 10V. Similarly, it is possible to clamp the input wave
form positively at -10V by reversing the battery connections as shown in
Fig 2.76(b).

121
(3) Negative Clamber

Fig.2.77 shows the circuit of a negative clamper during the positive half
cycle of the input signal, the capacitor is charged to Vm, with the polarity
shown in Fig. 2.77. Observe that voltage across the capacitor is opposing
the input voltage V. This gives negative clamped voltage and is called
negative clamper circuit.

Fig.2.77

(4) Negative Clamper With bias

Fig.2.78(a) shows the circuit of negative clamper with positive bias. With
no input signal the capacitor charges to the battery voltage and the output
is positive because the negative side of the batter is grounded. The output
waveform is clamped to +10V, the value of the battery. Since this is a
negative clamper (cathode to ground), the top of the output wave touch
the +10V reference line.

122
 Fig.2.78

Similarly it is possible to clamp the input waveform negatively at by

reversing the battery connections as shown in Fig .2.78(b)

2.17 Clipping Circuits

Clipping circuit is a wave-shaping circuit, and is used to either remove or
clip a portion of the applied wave in order to control the shape of the
output waveform. There are a variety of diode networks called clippers
that have the ability to ―clip‖ off a portion of the input signal without
distorting the remaining part of the alternating waveform and this is done
by the shown simple clipping circuit in Fig. 2.79

123
 Fig. 2.79

One of the most basic clipping circuit is the half-wave rectifier. A half-
wave rectifier clips either the negative half cycle or the positive half cycle
of an alternating waveform, and allows to pass only one half cycle. Such
a circuit has great applications in radars, digital computers and other
electronic systems for removing unwanted portions of the input signal
voltages above or below a specified level. Another application is in radio-
receivers for communication circuits where noise pulses that rise well
above the signal amplitude are clipped down to the desired level.
Clipping circuits are also referred to as voltage limiters.

2.17.1 Classifications Of Clippers

Clipping circuit consists of non-linear and linear devices. The non-linear
devices generally used for clipping are diodes and transistors.

According to biasing, the clippers may be classified as

 Unbiased clippers and

124
  Biased clippers.

According to configuration used the clippers may be

 Series diode clippers

 Parallel or shunt diode clippers
 A series combination of diode, resistor and reference supply

According to level of clipping the clippers may be

 Positive clippers
 Negative clippers
 Biased clippers and
 Combination clippers

This article explains the working of different diode clipper circuits

like Positive and Negative Diode Clippers, Biased Clipper circuit, and
Combinational Clipper Circuit with the help of circuit diagrams and
waveforms.

The basic components required for a clipping circuit are – an ideal diode
and a resistor. In order to fix the clipping level to the desired amount, a dc
battery must also be included. When the diode is forward biased, it acts
as a closed switch, and when it is reverse biased, it acts as an open switch.
Different levels of clipping can be obtained by varying the amount of
voltage of the battery and also interchanging the positions of the diode
and resistor.

Depending on the features of the diode, the positive or negative region of

the input signal is ―clipped‖ off and accordingly the diode clippers may
be positive or negative clippers.

There are two general categories of clippers: series and parallel (or
shunt). The series configuration is defined as one where diode is in
series with the load, while the shunt clipper has the diode in a branch
parallel to the load.

2.17.2 Positive Clipper and Negative Clipper

(1) Positive Diode Clipper

125
In a positive clipper, the positive half cycles of the input voltage will be
removed. The circuit arrangements for a positive clipper are illustrated in
the Fig.2.80 ( a is the input , b the clipping circuit , c the output) .

As shown in the figure…., the diode is kept in series with the load.

Fig.2.80

During the positive half cycle of the input waveform, the diode ‗D‘ is
reverse biased, which maintains the output voltage at 0 Volts. Thus
causes the positive half cycle to be clipped off. During the negative half
cycle of the input, the diode is forward biased and so the negative half
cycle appears across the output.

126
In Fig.2.81, the diode is kept in parallel with the load. This is the

Fig.2.81

diagram of a positive shunt clipper circuit. During the positive half cycle,
the diode ‗D‘ is forward biased and the diode acts as a closed switch. This
causes the diode to conduct heavily. This causes the voltage drop across
the diode or across the load resistance RL to be zero. Thus output voltage
during the positive half cycles is zero, as shown in the output waveform.
During the negative half cycles of the input signal voltage, the diode D is
reverse biased and behaves as an open switch. Consequently the entire
input voltage appears across the diode or across the load resistance R L if
R is much smaller than RL

Actually the circuit behaves as a voltage divider with an output voltage of

[RL / R+ RL] Vmax = -Vmax when RL >> R

(2) Negative Diode Clipper

127
The negative clipping circuit is almost same as the positive clipping
circuit, with only one difference. If the diode in Fig.2.80 and 81 is
reconnected with reversed polarity, the circuits will become for a
negative series clipper and negative shunt clipper respectively. The
negative series and negative shunt clippers are shown in Fig.2.82 and
2.83 as given below.

Fig.2.82

128
 Fig.2.83

In all the above discussions, the diode is considered to be ideal one. In a

practical diode, the breakdown voltage will exist (0.7 V for silicon and
0.3 V for Germanium). When this is taken into account, the output wave-
forms for positive and negative clippers will be of the shape shown in the
Fig.2.84 below.

129
 Fig.2.84

2.17.3 Biased Positive Clipper and Biased Negative Clipper

A biased clipper comes in handy when a small portion of positive or
negative half cycles of the signal voltage is to be removed. When a
small portion of the negative half cycle is to be removed, it is called a
biased negative clipper. The circuit diagram and waveform is shown
in the Fig.2.85 below.

Fig.2.85

In a biased clipper, when the input signal voltage is positive, the

diode ‗D‘ is reverse-biased. This causes it to act as an open-switch.
Thus the entire positive half cycle appears across the load, as

130
illustrated by output waveform [Fig.2.85 (a)]. When the input signal
voltage is negative but does not exceed battery the voltage ‗V‘, the di-
ode ‗D‘ remains reverse-biased and most of the input voltage appears
across the output. When during the negative half cycle of input signal,
the signal voltage becomes more than the battery voltage V, the diode
D is forward biased and so conducts heavily. The output voltage is
equal to ‗- V‘ and stays at ‗- V‘ as long as the magnitude of the input
signal voltage is greater than the magnitude of the battery voltage,
‗V‘. Thus a biased negative clipper removes input voltage when the
input signal voltage becomes greater than the battery voltage.
Clipping can be changed by reversing the battery and diode
connections, as illustrated in Fig.2.86(b).

Fig.2.86

2.17.4 Combination Clipper

When a portion of both positive and negative of each half cycle of
the input voltage is to be clipped (or removed), combination
clipper is employed. The circuit for such a clipper is given in the
Fig.2.87.

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 Fig.2.87

The action of the circuit is summarized below. For positive input

voltage signal when input voltage exceeds battery voltage ‗+
V1‗ diode D1 conducts heavily while diode ‗D2‗ is reversed biased
and so voltage ‗+ V1‗ appears across the output. This output
voltage ‗+ V1‗ stays as long as. the input signal voltage exceeds ‗+
V1‗. On the other hand for the negative input voltage signal, the
diode ‗D1‗ remains reverse biased and diode ‗D2‗ conducts heavily
only when input voltage exceeds battery voltage ‗V2‗ in
magnitude. Thus during the negative half cycle the output stays at
‗- V2‗ so long as the input signal voltage is greater than ‗-V2‗.

Drawbacks of Series and Shunt Diode Clippers

 In series clippers, when the diode is in ‗OFF‘ position, there

will be no transmission of input signal to output. But in case
of high frequency signals transmission occurs through diode
capacitance which is undesirable. This is the drawback of
using diode as a series element in such clippers.
 In shunt clippers, when diode is in the ‗off condition,
transmission of input signal should take place to output. But
in case of high frequency input signals, diode capacitance
affects the circuit operation adversely and the signal gets
attenuated (that is, it passes through diode capacitance to
ground).

132
 Ch.3

Bipolar Junction Transistors (BJT)

133
3.1 Introduction
Before transistors were invented, circuits used vacuum tubes:

– Fragile, large in size, heavy, generate large quantities of

heat, require a large amount of power

The first transistors were created at Bell Telephone Laboratories in 1947

William Shockley, John Bardeen, and Walter Brattain created the
transistors in and effort to develop a technology that would overcome the
problems of tubes

– The first patents for the principle of a field effect transistor

were registered in 1928 by Julius Lille field.

– Shockley, Bardeen, and Brattain had referenced this

material in their work

The word ―transistor‖ is a combination of the terms ―trans-conductance‖

and ―variable resistor‖ i.e it is the abbreviation of "transfer resistor".

The transistor is the main building block ―element‖ of electronics. It is a

semiconductor device and it comes in two general types:
-the Bipolar Junction Transistor (BJT) and
- the Field Effect Transistor (FET).
Here we will describe the system characteristics of the BJT configuration
and explore its use in fundamental signal shaping and amplifier circuits.

3.2 Transistor Construction

The transistor is a three-layer semiconductor device consisting of either
two n- and one p-type layers of material or two p- and one n-type layers
of material. The former is called an npn transistor, while the latter is
called a pnp transistor. Both are shown in Fig. 3.1 . The emitter layer is
heavily doped, the base lightly doped, and the collector only lightly
doped. The outer layers have widths much greater than the sandwiched p-
or n-type material. As an example the transistors may have the ratio of the
total width to that of the center layer is 0.150/0.001 = 150:1. The doping
of the sandwiched layer is also considerably less than that of the outer
layers (typically, 10:1 or less). This lower doping level decreases the
conductivity (increases the resistance) of this material by limiting the
134
number of ―free‖ carriers. The symbols for both npn and pnp transistors
are shown in Fig.3.2. The terminals have been indicated by the capital
letters E for emitter, C for collector, and B for base.

• Emitter: This is the segment on one side of the transistor shown in Fig.
3-1. It is of moderate size and heavily doped. It supplies a large number
of majority carriers for the current flow through the transistor.

• Base: This is the central segment. It is very thin and lightly doped.

• Collector: This segment collects a major portion of the majority carriers

supplied by the emitter. The collector side is moderately doped and larger
in size as compared to the emitter.

An appreciation for this choice of notation will develop when we discuss

the basic operation of the transistor. The abbreviation BJT, from bipolar
junction transistor, is often applied to this three terminal device. The term
bipolar reflects the fact that holes and electrons participate in the
injection process into the oppositely polarized material( In FET
Transistor only one of them used). If only one carrier is employed
(electron or hole), it is considered a unipolar device.

Fig. 3.1 Transistor construction

135
 Fig.3.2 Transistor symbols

The BJT has two junctions (boundaries between the n and the p regions).
These junctions are similar to the junctions we saw in the diodes and thus
they may be forward biased or reverse biased. By relating these junctions
to a diode model the pnp BJT may be modeled as shown on Fig.3. 3.

Fig.3. 3. Transistor junctions

3.3 Transistor Operation

Behavior of NPN BJT is discussed below. Operation of a PNP transistor
is analogous to that of a NPN transistor except that the role of charge
carries reversed. In NPN transistors, electron flow is dominant while PNP
transistors rely mostly on the flow of "holes." Therefore, to zeroth order,
NPN and PNP transistors behave similarly except the sign of current and
voltages are reversed. i.e., PNP = - NPN ! .
In practice, NPN transistors are much more popular than PNP transistors
because electrons move faster in a semiconductor. As a results, a NPN
transistor has a faster response time compared to a PNP transistor.
136
At the first glance, a BJT looks like 2 diodes placed back to back. Indeed
this is the case if we apply voltage to only two of the three terminals,
letting the third terminal float. This is also the way that we check if a
transistor is working: use an ohm-meter to ensure both diodes are in
working conditions. (One should also check the resistance between CE
terminals and read a vary high resistance as one may have a burn through
the base connecting collector and emitter.)

The behavior of the BJT is different, however, when voltage sources are
attached to both BE and CE terminals. The BE junction acts like a diode.
When this junction is forward biased, electrons flow from emitter to the
base (and a small current of holes from base to emitter). The base region
is narrow and when a voltage is applied between collector and emitter,
most of the electrons that were owing from emitter to base, cross the
narrow base region and are collected at the collector region. So while the
BC junction is reversed biased, a large current can flow through that
region and BC junction does not act as a diode.

The amount of the current that crosses from emitter to collector region
depends strongly on the voltage applied to the BE junction, vBE. (It also
depends weakly on voltage applied between collector and emitter, vCE.)
As such, small changes in vBE or iB controls a much larger collector
current iC. Note that the transistor does not generate iC. It acts as a valve
controlling the current that can flow through it. The source of current
(and power) is the power supply that feeds the CE terminals.

3.3.1 Active mode

Some details
A BJT has three terminals. Six parameters; iC, iB, iE, vCE, vBE, and vCB;
define the state of the transistor. However, because BJT has three
terminals, KVL (Kirchhoff voltage Low) and KCL (Kirchhoff current
Low) should hold for these terminals,(Fig. 3. 4) i.e.,

i E = i C + iB , vBC = vBE - vCE (1)

137
 Fig. 3. 4 Transistor six parameters

So, when the BE junction is forward biased (Fig.3.5, electrons from the
emitter diffuse into the base and holes from the base into the emitter
setting up the BE diode diffusion current. Because the emitter is heavily
doped, a large number of electrons enter the base. If the base is thin
enough, there would be a substantial number of electrons in the vicinity
of the BC junction.

Fig.3.5 BE junction in forward bias

If a ―negative‖ voltage is applied to the BC junction (Fig.3-6), the elec-

trons from the emitter which had diffused to the vicinity of the BC
junction are swept into the collector (a drift current). As a result, a
substantial current flows between emitter and collector terminals. Note
that the BC junction is reversed biased in this case (but the BC junction
does not ―act‖ as a diode).

This mode of operation is called the active mode: the BE junction is

forward biased while the BC junction is reversed biased:

138
 Fig.3-6 Transistor in active mode

vBE = VD0 & vBC < 0 → vCE = vCB + vBE > VD0

3.3.2 Charge Concentration;

Fig3.7 shows Profiles of minority-carrier concentrations in the base and

in the emitter of an npn transistor operating in the active mode: vBE > 0
and vCB ≥ 0.

Fig3.7 Profiles of minority-carrier concentrations in the base and in the

emitter of an npn transistor.

139
Since the BE junction acts as a diode, the number of electrons which
diffused into base and are near the BC junction scales as exp(vBE/VT ) (for
an emission coefficient, n = 1). As all these electrons will be swept into
the collector, regardless of vBC (or vCE = vBE − vBC), the collector current,
iC should not depend on vCE. Furthermore:

iC = IS exp(vBE/VT) (2)

The base current, iB, also scales as exp(vBE/VT). However, because

emitter is heavily doped and base is thin, only a very small fraction of
electrons that diffused into base combine with holes – majority of
emitter-originated electrons are swept into the collector. As such, the ratio
of:
iC/iB = β (3)

is large and relatively constant (but changes with temperature, etc.).

Parameter β is called the BJT common-emitter current gain (or current
gain for short):

iB = (IS/β ) exp(vBE/VT) (4)

As can be seen, operation of a BJT requires the presence of emitter-

generated electrons near the BC junction (thus, the BE junction should be
forward biased).

In Fig. 3.8, VCC and VEE are used for creating the respective biasing.
When the transistor is biased in this way it is said to be in active state. We
represent the voltage between emitter and base as VEB and that between
the collector and the base as VCB. In Fig. (3.8a , b), base is a common
terminal for the two power supplies whose other terminals are connected
to emitter and collector, respectively. So the two power supplies are
represented as VEE, and VEE, respectively. In circuits, where emitter is the
common terminal, the power supply between the base and the emitter is
represented as VBB and that between collector and emitter as VEE.
Let us see now the paths of current carriers in the transistor with emitter-
base junction forward biased and base-collector junction reverse biased.
The heavily doped emitter has a high concentration of majority carriers,
which will be holes in a p-n-p transistor and electrons in an n-p-n
transistor. These majority carriers enter the base region in large numbers.
The base is thin and lightly doped. So the majority carriers there would be
few. In a p-n-p transistor the majority carriers in the base are electrons

140
since base is of n-type semiconductor. The large number of holes entering
the base from the emitter swamps the small number of electrons there.

Fig. 3.8 Bias voltage applied to pnp and npn transistors

141
As the base collector-junction is reverse biased, these holes, which appear
as minority carriers at the junction, can easily cross the junction and enter
the collector. The holes in the base could move either towards the base
terminal to combine with the electrons entering from outside or cross the
junction to enter into the collector and reach the collector terminal. The
base is made thin so that most of the holes find themselves near the
reverse-biased base-collector junction and so cross the junction instead of
moving to the base terminal. It is interesting to note that due to forward
bias a large current enters the emitter-base junction, but most of it is
diverted to adjacent reverse-biased base-collector junction and the current
coming out of the base becomes a very small fraction of the current that
entered the junction. If we represent the hole current and the electron
current crossing the forward biased junction by Ih and Ie respectively then
the total current in a forward biased diode is the sum
Ih + Ie. We see that the emitter current IE is:

IE = Ih + Ie

but the base current IB is:

IB << Ih + Ie

This is because a major part of IE goes to collector instead of coming out

of the base terminal. The base current is thus a small fraction of the
emitter current.

3.3.3 Current Components

The current entering into the emitter from outside is equal to the emitter
current IE. Similarly the current emerging from the base terminal is IB and
that from collector terminal is IC. It is obvious from the above description
and also from a straight forward application of Kirchhoff‘s law to Fig.
3.8(a) that the emitter current is the sum of collector current and base
current:

IE = IC + IB (5)

Our description of the direction of motion of the holes is identical with

the direction of the conventional current. But the direction of motion of
electrons is just opposite to that of the current. Thus in a p-n-p transistor
the current enters from emitter into base whereas in a n-p-n transistor it

142
enters from the base into the emitter. The arrowhead in the emitter shows
the direction of the conventional current.
The description about the paths followed by the majority and minority
carriers in a n-p-n is exactly the same as that for the p-n-p transistor. But
the current paths are exactly opposite, as shown in Fig. 3.8. In Fig. 3.8(b)
the electrons are the majority carriers supplied by the n-type emitter
region. They cross the thin p-base region and are able to reach the
collector to give the collector current, IC . From the above description we
can conclude that in the active state of the transistor the emitter-base
junction acts as a low resistance while the base collector acts as a high
resistance.

Example 1

A transistor is connected as shown in Fig. 3–9. It has a base current of 8

μA and a collector current of 1.2 mA. What is the emitter current and the
beta of the transistor:

Fig. 3–9

Solution:

Step 1: calculate emitter current.

IE = IB + IC Transistor current divider

IE = 8 μA + 1.2 mA
IE = 1208 μA

Step 2. Calculate beta.

143
β = IC/IB Transistor current gain (beta)
β = 1200 mA / 8 mA
= 150

Example 2

A transistor is connected as shown in Figure 4–7. It has an emitter current

of 2.42 mA and a collector current of 2.4 mA. What is the base current
and beta of the transistor?

Solution

Step 1. Calculate base current.

IE = IB + IC
IB = IE – IC
IB = 2.42 mA – 2.40 mA
IB = 0.02 mA or 20 μA

Step 2. Calculate beta.

β = IC / IB
β = 2400 μA / 20 μA
β = 120

Example 3

A transistor is connected as in Figure 4–7 and has a base current of 16 μA

and a beta of 80. What is the collector current and emitter current of the
transistor?
Step 1. Calculate the collector current.

β = IC / IB

IC = β × IB
IC = 80 × 16μA
IC = 1280 μA or 1.28 mA
Step 2. Calculate the emitter current.

IE = IB+ IC

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IE = 16 μA + 1280 μA
IE = 1296 μA or 1.296 mA

3.4 Basic transistor circuit configurations and transistor

Characteristics

In a transistor, only three terminals are available, viz., Emitter (E), Base
(B) and Collector (C). Therefore, in a circuit the input/output connections
have to be such that one of these (E, B or C) is common to both the input
and the output. Accordingly, the transistor can be connected in either of
the following three configurations (Fig.3.10 ):

-Common Emitter (CE),

-Common Base (CB),

-Common Collector (CC)

Fig.3.10 Basic transistor circuit configurations

The transistor is most widely used in the CE configuration and we shall

restrict our discussion to only this configuration. Since more commonly
used transistors are n-p-n Si transistors, we shall confine our discussion to
such transistors only. With p-n-p transistors the polarities of the external
power supplies are to be inverted. We indicate shortly C.B and C.C

145
3.4.1 Common base transistor characteristics (C.B)

When a transistor is used in CB configuration, the input is between the

emitter and the base and the output is between the collector and the base
as shown in Fig.3.11

Fig.3.11 CB configuration

Input characteristics for the common base configuration are shown in

Fig.3.12 which display change of VEB with IE .

Fig.3.12 Input characteristics for CB configuration

146
Output characteristics for the common base configuration are shown in
Fig.3.13 which display change of VCB with IC . These characteristics have
three regions:
1- Cut –off region: in which no current passing in the collector-base
junction. This means IE =0 , IC = IC0

2- Active region (also called amplification region or linear operation

region): in this region base junction (between emitter and base) is
forward biased while collector junction (between collector and
base) is reversely biased.

3- Saturation region: in which larger current pass in collector base

junction.

Fig.3.13 Output characteristics for CB configuration

3.4.2 Common Collector transistor characteristics(C.C)

Fig.3-14 shows a simple circuit for the common collector, and

proceeding as in C.B . It is to be noted that the characteristics of this

147
configuration is not differ much from common emitter which is very
familiar in transistor circuits.

Fig.3-14 CC circuit configuration

3.4.3 Common emitter transistor characteristics

When a transistor is used in CE configuration, the input is between the

base and the emitter and the output is between the collector and the
emitter as shown in Fig.3.15 a. The variation of the base current IB with
the base-emitter voltage VBE is called the input characteristic. Similarly,
the variation of the collector current IC with the collector-emitter voltage
VCE is called the output characteristic. You will see that the output
characteristics are controlled by the input characteristics. This implies
that the collector current changes with the base current.

The input and the output characteristics of an n-p-n transistors can be

studied by using the circuit shown in Fig. 3.15b. To study the input
characteristics of the transistor in CE configuration, a curve is plotted
between the base current IB against the base-emitter voltage VBE. The

148
 (a)

(b)

Fig. 3.15.CE configuration and circuit arrangement

collector-emitter voltage VCE is kept fixed while studying the dependence

of IB on VBE. We are interested to obtain the input characteristic when the

149
transistor is in active state. So the collector-emitter voltage VCE is kept
large enough to make the base collector junction reverse biased. Since
VCE = VCB + VBE and for Si transistor VBE is 0.6 to 0.7 V, VCE must be
sufficiently larger than 0.7 V. Since the transistor is operated as an
amplifier over large range of VCE, the reverse bias across the base-
collector junction is high most of the time.

Therefore, the input characteristics may be obtained for VCE somewhere

in the range of 3 V to 20 V. Since the increase in VCE appears as increase
in VCB, its effect on IB is negligible. As a consequence, input
characteristics for various values of VCE will give almost identical curves.
Hence, it is enough to determine only one input characteristics. The input
characteristics of a transistor is as shown in Fig. 3.16(a).

The output characteristic is obtained by observing the variation of IC as

VCE is varied keeping IB constant. It is obvious that if VBE is increased by
a small amount, both hole current from the emitter region and the electron
current from the base region will increase. As a consequence both IB and
IC will increase proportionately. This shows that when IB increases IC also
increases. The plot of IC versus VCE for different fixed values of IB gives
one output characteristic. So there will be different output characteristics
corresponding to different values of IB as shown in Fig. 3.16(b). The
linear segments of both the input and output characteristics can be used to
calculate some important ac parameters of transistors as shown below.

Fig. 3.16 input and output characteristics for CE

150
BJT i-v characteristics above is typically shown… as plot of iB vs vBE
(similar to a diode iv curve) and a ―contour‖ plot of iC vs vCE with each
contour lines representing a value of iB. Note that iC = g(vCE, iB) is
actually a ―surface‖ plot in the 3-D space of iC, vCE, iB. The iC vCE plot
shown is a projection of this 3-D surface with the iB axis pointing into the
plane. An iC-vCE plot of a commercial BJT is shown in Fig. 3.16.

A transistor can be damaged if :

(1) a large positive voltage is applied between the collector and emitter
(breakdown region), or
(2) product of iCvCE exceed the power handling capability of the
transistor, or
(3) a large reverse voltage is applied between any two terminals.

3.4.4 Early Effect

Our rather simple description of the operation of a BJT in the active mode
indicated that for a given iB, iC =_iB and is independent of vCE. However,
as iC -vCE plot above shows, iC increases slightly with vCE. The reason for
this increase in iC is that as vCE is increased, the ―effective‖ width of the
base region is reduced and more electrons can reach the collector.
This is called the ―Early‖ effect.
In fact, if we extrapolate all characteristics lines of the active region, they
would meet at a negative voltage of vCE = −VA as is shown in Fig.3.17.
The voltage VA is particular to each BJT (depends on its manufacturing)
and has a typical value of 50 to 100 V. It is called the ―Early‖ voltage.

Fig.3.17 ―Early‖ voltage (effect).

151
The Early effect can be accounted for by the following addition to the i C
equation (Note that iB equation does NOT change):

iB = (IS/β ) [ exp(vBE/VT)] [1 + vCE / VA] (6)

The above model, is called a ―large signal‖ model as it applies to any size
currents/voltages applied to the BJT (as opposed to a ―small-signal‖
model discussed later). While rather simple, it is quite sufficient for
analysis.
Note that the explicit non-linear form is included only in the active mode
equations. Furthermore, only ―deep‖ saturation mode is included as for
practical reasons, BJT is only operated in deep saturation mode when it is
used as a switch or a logic gate and soft saturation is usually avoided
when BJT is used in the active mode (e.g., as an amplifier), in order to
reduce non-linear distortion.

3.4.5 Cut-off mode

A BJT is called to be in ―cut-off‖ if the BE junction is NOT forward

biased. In this case, iB = 0 and iC = 0 regardless of any voltage applied to
the BC junction.

3.4.6 Saturation mode

Now, let‘s consider the case of the BC junction being forward biased
(with BE junction still forward biased), So:

vCE = vBE − vBC < VD0.

This is called the saturation mode.

As the BC junction is forward biased, a diffusion current is set up

between the collector and base regions (which is in the opposite direction
to iB and iC). When vBC is small (vBC < 0.3V , or vCE > 0.4V for Si), the
diffusion current from the BC junction is negligible and iC remains close
to its value for the active mode. This region is usually called the ―soft
saturation region.‖ Some text books include this region as part of the
active mode, i.e., say BJT is in active if vCE > 0.4 V (instead of vCE ≥ VD0
= 0.7 V).

152
When vBC becomes large enough (vCE ≈ 0.1 − 0.3 V for Si) a substantial
diffusion current flows from the collector to the base, thereby reducing i C
below its active-mode level, i.e., iC < _iB. This is called the ―deep
saturation‖ region.
For vCE close to zero (vCE < 0.1 V for Si), the collector current rapidly
goes to zero. This region is referred to as the ―near cut-off‖ region.

(i)Input resistance (ri):

This is defined as the ratio of change in base-emitter voltage (ΔVBE) to

the resulting change in base current (ΔIB) at constant collector-emitter
voltage (VCE). This is dynamic (ac resistance)
and as can be seen from the input characteristic, its value varies with
the operating current in the transistor:

ri= ΔVBE /ΔIB at constant collector-emitter voltage (VCE) (7)

The value of ri can be anything from a few hundreds to a few thousand

ohms.

(ii) Output resistance (ro):

This is defined as the ratio of change in collector-emitter voltage (ΔVCE)

to the change in collector current (ΔIC)
at a constant base current IB.

ro = ΔVCE / ΔIC at a constant base current IB. (8)

The output characteristics show that initially for very small values of
VCE, IC increases almost linearly. This happens because the base-collector
junction is not reverse biased and the transistor is not in active state. In
fact, the transistor is in the saturation state and the current is controlled by
the supply voltage VCC (=VCE) in this part of the characteristic. When VCE
is more than that required to reverse bias the base-collector junction, IC
increases very little with VCE. The reciprocal of the slope of the linear
part of the output characteristic gives the values of ro. The output
resistance of the transistor is mainly controlled by the bias of the base-
collector junction. The high magnitude of the output resistance (of the

153
order of 100 kΩ) is due to the reverse-biased state of this diode. This also
explains why the resistance at the initial part of the characteristic, when
the transistor is in saturation state, is very low.

(iii) Current amplification factor (β ):

This is defined as the ratio of the change in collector current to the change
in base current at a constant collector-emitter voltage (VCE) when the
transistor is in active state.

βac = IC/ IB at a constant collector-emitter voltage (VCE) (9)

This is also known as small signal current gain and its value is very large.
If we simply find the ratio of IC and IB we get what is called dc β of the
transistor. Hence,

βdc = IC/ IB (10)

Since IC increases with IB almost linearly and IC = 0 when IB = 0, the

values of both βdc and βac are nearly equal. So, for most calculations βdc
can be used. Both βac and βdc vary with VCE and IB (or IC) slightly.

Example

From the output characteristics shown in Fig. 3.16(b), calculate the values
of βac and βdc of the transistor when VCE is

Solution

βac = IC/ IB , βdc = IC/ IB

For determining βac and βdc at the stated values of VCE and IC one can
proceed as follows. Consider any two characteristics for two values of IB
which lie above and below the given value of IC . Here IC = 4.0 mA.
(Choose characteristics for IB= 30 and 20 μA.) At VCE = 10 V we read the
two values of IC from the graph. Then

ΔIB = (30 – 20) μA = 10 μA, ΔIC = (4.5 – 3.0) mA = 1.5 mA

Therefore, βac = 1.5 mA/ 10 μA = 150

154
For determining βdc, either estimate the value of IB corresponding to :

IC = 4.0 mA at VCE = 10 V

or calculate the two values of βdc for the two characteristics chosen and
find their mean.

Therefore, for IC = 4.5 mA and IB = 30 μA,

βdc = 4.5 mA/ 30 μA = 150
and for IC = 3.0 mA and IB = 20 μA
βdc =3.0 mA / 20 μA = 150
Hence, βdc =(150 + 150) /2 = 150

3.5 Transistor Switches

A transistor can function as an SPST (single-pole single-throw) switch,

but rather than being mechanically controlled, it is controlled by an
electronic signal driving the base terminal. Fig. 3.18 shows a comparison
between an open SPST switch and an NPN transistor.

Fig. 3.18 Transistor switche

155
When the switch is open, as shown in Figure 3.18(a), there is no current
flowing in the circuit and the bulb is off. When the control signal on the
base terminal of the transistor turns the transistor off, as shown in Fig.
3.18(b), the transistor acts like an open switch. The resistance between
the collector and the emitter terminals rises infinitely high and prevents
current flow in the circuit. The bulb in series with the transistor is off.
So, when a transistor is used for switching, it is in one of two states: on or
off. In the off state, the base bias current (IB) is zero, and the transistor is
cut off. (Actually there is a small amount of leakage current, but it can be
ignored in most cases.) In the on state(saturation), the base bias current
(IB) is set large enough to drive the transistor into saturation. In
saturation, the voltage drop across the transistor (VCE) decreases to zero,
and the voltage across the load goes to Vcc. (Actually the voltage drop
across the transistor decreases to approximately 0.2 V, and the voltage
drop across the load rises to Vcc minus 0.2 V). Transistors find many uses
in the switching mode. They are used to switch off and on electrical loads
of all types and are used extensively in digital electronics where the
circuitry requires an on or off state.

3.6 Transistor amplifiers

Gain and Amplification

Transistor amplifiers are circuits that provide signal gain. Gain is an
important concept in electronics. Let us take a moment to make sure we
have a common understanding of the word. Gain is the ratio of output to
input. The general formula is :

Gain = Output / Input. (11)

Gain has no units because the output and the input must be in the same
units, and the units cancel.

Fig.3.19 shows the symbol used for an amplifier. An amplifier is an

electronic circuit used to obtain gain. In Figure 3.19, the amplifier has an
input of 0.6 Vp-p and an output of 6 Vp-p. By using the gain formula, we
can calculate the voltage gain to be 10 (6 Vp-p /0.6 Vp-p = 10). The word
voltage preceding gain indicates that the gain ratio is comprised of the
output voltage and the input voltage. It is also possible to have current
and power gains.

156
 Fig.3.19 Symbol for transistor amplifier

3.7 Biasing and classification of Transistor Amplifier

Biasing a transistor amplifier circuit is the process of setting the DC

voltage and current to the proper level so a signal can be accepted and
amplified by the circuit. A comparison can be made between an
automobile idle and the transistor amplifier bias current. With the idle set
properly, the automobile is ready to receive an input from the accelerator.
With the bias current set properly, the transistor amplifier is ready to
receive an input from the signal generator. In the case of the automobile,
we are trying to set the engine to a constant rpm with no input applied. In
the case of the transistor amplifier, we are trying to set the collector
current (IC) to a constant value with no input signal applied.
Theoretically, the idle of an automobile could be set anywhere from zero
rpms (engine off) to the maximum rpms (engine wide open).The proper
idle point is somewhere between the two extremes. The same is true of a
transistor amplifier; theoretically, the bias could be set anywhere from IC
= 0 amps (cutoff) to maximum IC (saturation). The proper bias point is
somewhere between the two extremes and is called the quiescent
operating point, or Q-point.

When an amplifier is biased so the Q-point is near the middle of its

operating range (halfway between cutoff and saturation), it is said to be
operating class-A. This operation permits the output current to increase
and decrease from the Q-point as the input swings through a complete
cycle. In other words, output current flows for the full 360‫ ؛‬of the input
cycle. Fig.3.20(a) shows a class-A amplifier that permits the output
current to flow for the full 360O of the input cycle.

157
 Fig.3.20 Classes of transistor amplifiers

When an amplifier is biased at cutoff, it is operating class-B. In class-B

operation, the output current will flow only for one alternation, or 180‫؛‬,
of the input cycle. Fig.3.20(b) shows a class-B amplifier.
In class-C operation, the amplifier is biased below cutoff. This means
the input signal must cross zero and move partway through an alternation
before output current starts to flow. In other words, output current flows
less than 180‫؛‬. Fig. 3–20(c) shows a class-C amplifier.
Class-B and class-C amplifiers do not provide a true reproduction of the
input signal; however, they are both much more efficient than class-A
amplifiers.
class-A amplifier circuits have output current flow for the complete cycle
of the input signal, the output wave shape will be the same as the input.
However, because the circuit has gain, the magnitude of the output
signal is larger.

3.7.1 DC Biasing of BJTs:

158
The analysis or design of a transistor amplifier requires a knowledge of
both the dc and ac response of the system. Too often it is assumed that the
transistor is a magical device that can raise the level of the applied ac
input without the assistance of an external energy source. In actuality, the
improved output ac power level is the result of a transfer of energy from
the applied dc supplies. The analysis or design of any electronic amplifier
therefore has two components: the dc portion and the ac portion.
Fortunately, the superposition theorem is applicable and the investigation
of the dc conditions can be totally separated from the ac response.
However, one must keep in mind that during the design or synthesis stage
the choice of parameters for the required dc levels will affect the ac
response, and vice versa.
The dc level of operation of a transistor is controlled by a number of
factors, including the range of possible operating points on the device
characteristics. In Section 4.2 we specify the range for the BJT amplifier.
Once the desired dc current and voltage levels have been defined, a
network must be constructed that will establish the desired operating
point—a number of these networks are analyzed in this chapter. Each
design will also determine the stability of the system, that is, how
sensitive the system is to temperature variations—another topic to be
investigated in a later section of this chapter.
Although a number of networks are analyzed in this chapter, there is an
underlying similarity between the analysis of each configuration due to
the recurring use of the following important basic relationships for a

VBE = 0.7 V (12)

IE = (β + 1)IB ≡ IC (13)
IC =βIB (14)

In fact, once the analysis of the first few networks is clearly understood,
the path toward the solution of the networks to follow will begin to
become quite apparent. In most instances the base current IB is the first
quantity to be determined. Once IB is known, the relationships of Eqs.
(12) through (14) can be applied to find the remaining quantities of
interest. The similarities in analysis will be immediately obvious as we
progress through the chapter. The equations for IB are so similar for a
number of configurations that one equation can be derived from another
simply by dropping or adding a term or two. The primary function of this
chapter is to develop a level of familiarity with the BJT transistor that
would permit a dc analysis of any system that might employ the BJT
amplifier.

159
3.7.2 Operating Point

The term biasing appearing in the title of this chapter is an all-inclusive

term for the application of dc voltages to establish a fixed level of current
and voltage. For transistor amplifiers the resulting dc current and voltage
establish an operating point on the characteristics that define the region
that will be employed for amplification of the applied signal. Since the
operating point is a fixed point on the characteristics, it is also called the
quiescent point (abbreviated Q-point). By definition, quiescent means
quiet, still, inactive. Fig. 3.21 shows a general output device
characteristic with four operating points indicated. The biasing circuit can
be designed to set the device operation at any of these points or others
within the active region. The maximum ratings are indicated on the
characteristics of Fig. 3.21 by a horizontal line for the maximum
collector current ICmax and a vertical line at the maximum collector-to-
emitter voltage VCEmax. The maximum power constraint is defined by the
curve PCmax in the same figure. At the lower end of the scales are the
cutoff region, defined by IB ≤ 0 μA, and the saturation region, defined by
VCE ≤ VCEsat.

The BJT device could be biased to operate outside these maximum

limits, but the result of such operation would be either a considerable
shortening of the lifetime of the device or destruction of the device.
Confining ourselves to the active region, one can select many different
operating areas or points. The chosen Q-point often depends on the
intended use of the circuit. Still, we can consider some differences among
the various points shown in Fig. 3.21 to present some basic ideas about
the operating point and, thereby, the bias circuit.

If no bias were used, the device would initially be completely off,

resulting in a Q-point at A—namely, zero current through the device (and
zero voltage across it). Since it is necessary to bias a device so that it can
respond to the entire range of an input signal, point A would not be
suitable. For point B, if a signal is applied to the circuit, the device will
vary in current and voltage from operating point, allowing the device to
react to (and possibly amplify) both the positive and negative excursions
of the input signal. If the input signal is properly chosen, the voltage and
current of the device will vary but not enough to drive the device into
cutoff or saturation. Point C would allow some positive and negative
variation of the output signal, but the peak-to- peak value would be

160
Fig. 3.21 The three regions active, saturation and cut-off for the transistor

limited by the proximity of VCE = 0V/IC = 0 mA. Operating at point C

also raises some concern about the nonlinearities introduced by the fact
that the spacing between IB curves is rapidly changing in this region. In
general, it is preferable to operate where the gain of the device is fairly
constant (or linear) to ensure that the amplification over the entire swing
of input signal is the same. Point B is a region of more linear spacing and
therefore more linear operation, as shown in Fig. 3.21. Point D sets the
device operating point near the maximum voltage and power level. The
output voltage swing in the positive direction is thus limited if the
maximum voltage is not to be exceeded. Point B therefore seems the best
operating point in terms of linear gain and largest possible voltage and
current swing. This is usually the desired condition for small-signal
amplifiers but not the case necessarily for power amplifiers. In this
discussion, we will be concentrating primarily on biasing the transistor
for amplification operation.
One other very important biasing factor must be considered. Having
selected and biased the BJT at a desired operating point, the effect of
temperature must also be taken into account. Temperature causes the
device parameters such as the transistor current gain (ac) and the

161
transistor leakage current (ICEO) to change. Higher temperatures result in
increased leakage currents in the device, thereby changing the operating
condition set by the biasing network. The result is that the network design
must also provide a degree of temperature stability so that temperature
changes result in minimum changes in the operating point. This
maintenance of the operating point can be specified by a stability factor,
S, which indicates the degree of change in operating point due to a
temperature variation. A highly stable circuit is desirable, and the stability
of a few basic bias circuits will be compared. For the BJT to be biased in
its linear or active operating region the following must be true:

1. The base–emitter junction must be forward-biased (p-region voltage

more positive), with a resulting forward-bias voltage of about 0.6 to 0.7
V.

2. The base–collector junction must be reverse-biased (n-region more

positive), with the reverse-bias voltage being any value within the
maximum limits of the device.

[Note that for forward bias the voltage across the p-n junction is p-
positive, while for reverse bias it is opposite (reverse) with n-positive.
This emphasis on the initial letter should provide a means of helping
memorize the necessary voltage polarity.]
Operation in the cutoff, saturation, and linear regions of the BJT
characteristic are provided as follows:

1. Linear-region operation:

Base–emitter junction forward biased

Base–collector junction reverse biased

2. Cutoff-region operation:
Base–emitter junction reverse biased
3. Saturation-region operation:
Base–emitter junction forward biased
Base–collector junction forward biased

3.7.3 Fixed –Bias Circuit

The fixed-bias circuit of Fig.3.22 provides a relatively straightforward
and simple introduction to transistor dc bias analysis. Even though the
network employs an npn transistor, the equations and calculations apply
equally well to a pnp transistor configuration merely by changing all
162
current directions and voltage polarities. The current directions of
Fig.3.22 are the actual current directions, and the voltages are defined by
the standard double-subscript notation. For the dc analysis the network
can be isolated from the indicated ac levels by replacing the capacitors
with an open circuit equivalent. In addition, the dc supply VCC can be
separated into two supplies (for analysis purposes only) as shown in Fig.
3.23 to permit a separation of input and output circuits. It also reduces
the linkage between the two to the base current I B. The separation is
certainly valid, as we note in Fig. 3.19 that VCC is connected directly to
RB and RC just as in Fig. 3.22.

Fig. 3.22 Base fixed bias circuit

So, we can shortly say for the circuit above ( Fig. 3.22 ):
This is common emitter (CE) configuration
* 1st step: Locate capacitors and replace them with an open circuit as in
Fig.3.23. Then proceed as in Fig.3.24

163
 Fig. 3.23

Fig.3.24 Dc equivalent step1 of the Fig.3.22 above

* 2nd step: Locate 2 main loops (Fig3,25 , 26, 27)

which;
-BE loop (input loop)
-CE loop(output loop)

164
Fig. 3.25 Dc equivalent step2 of the Fig.3.22 above

Fig. 3.26

165
 Fig. 3.27

3.8 Load-Line Analysis

The analysis thus far has been performed using a level of _ corresponding
with the resulting Q-point. We will now investigate how the network
parameters define the possible range of Q-points and how the actual Q-
point is determined. The network of Fig. 3.28a establishes an output
equation that relates the variables IC and VCE in the following manner:

VCE = VCC = IC RC (15)

The output characteristics of the transistor also relate the same two
variables IC and VCE as shown in Fig. Fig.3.28b.
In essence, therefore, we have a network equation and a set of
characteristics that employ the same variables. The common solution of
the two occurs where the constraints established by each are satisfied
simultaneously. In other words, this is similar to finding the solution of
two simultaneous equations: one established by the network and the other
by the device characteristics. The device characteristics of IC versus VCE
are provided in Fig. Fig. 3.28b. We must now superimpose the straight
line defined by Eq. (15) on the characteristics. The most direct method of
plotting Eq. (15) on the output characteristics is to use the fact that a
straight line is defined by two points. If we choose IC to be 0 mA, we are
specifying the horizontal axis as the line on which one point is located.
By substituting IC = 0 mA into Eq. (15), we find that:

166
VCE = VCC - (0) RC
and VCE = VCC for IC to be 0 mA (16)

This defining one point for the straight line as shown in Fig. 3.29.

Fig. 3.28 Load line analysis circuit and characteristics

If we now choose VCE to be 0 V, which establishes the vertical axis as the

line on which the second point will be defined, we find that IC is
determined by the following equation:
0 = VCC - IC RC

and IC = VCC / RC at VCE = 0 V (17)

as appearing on Fig. 3.26.

167
 Fig. 3.29

By joining the two points defined by Eqs. (16) and (17), the straight line
established by Eq. (15) can be drawn. The resulting line on the graph of
Fig. 3.26 is called the load line since it is defined by the load resistor RC.
By solving for the resulting level of IB, the actual Q-point can be
established as shown in Fig. 3.29.
If the level of IB is changed by varying the value of RB the Q-point
moves up or down the load line as shown in Fig. 3.30. If VCC is held fixed
and RC changed, the load line will shift as shown in Fig. 3.31. If IB is held
fixed, the Q-point will move as shown in the same figure. If RC is fixed
and VCC varied, the load line shifts as shown in Fig. 3.31. Change of Ib
gives the move of the point Q on the load line shown in Fig.3.32.

So , we summarize for Load line analysis:

-A fixed bias circuit with given values of VCC , RC and RB can be
analyzed ( means, determining the values of IBQ, ICQ and VCEQ) using the
concept of load line also.
- Here the input loop KVL equation is not used for the purpose of
analysis, instead, the output characteristics of the transistor used in the
given circuit and output loop KVL equation are made use of Fig2.30.
168
 Fig. 3.30

- Plot load line equation

VCE = VCC - IC RC

- IC (sat) occurs when transistor operating in saturation region

ICsat = = VCC / RC at VCE = 0

- VCE(off) occurs when transistor operating in cut-off region

VCE(OFF) = VCC - IC RC at IC = 0

169
 Fig. 3.31

Fig. 3.32
Example

Given the load line of Fig. 3.33 and the defined Q-point, determine the
required values of VCC , RC, and RB for a fixed-bias configuration.

170
 Fig. 3.33

Solution
From Fig. 4.16,

VCE = VCC = 20 V at IC = 0 mA

IC = VCC / RC at VCE = 0 V

and RC = VCC / IC = 20V / 10 mA = 2 KΩ

IB = ( VCC - VBE ) / RB

And RB =( VCC - VBE ) / IB = (20 V - 0.7 V) / 25 μ A = 772 kΩ

171
 QUESTIONS Questions

1. What are the three terminals of a bipolar transistor?

a. emitter, base, collector

b. T1, T2, T3
c. source, gate, drain
d. emitter, gate, collector

2. The arrow on the transistor symbol always points to what type of

material?

a. P-type
b. N-type
c. Base-type
d. PN-type

3. Bipolar transistors are classified as _________.

a. PPN and PIN devices

b. NPN and PNP
c. NNP and PPN devices
d. N-type and P-type

4. The schematic symbol of a bipolar PNP transistor is shown below as

______.

5. How many PN junctions are there in the bipolar transistor?

a. 0
b. 1
c. 2
d. 3
e. 4
6. What type of material is the base section of a PNP transistor?
172
a. P-type
b. N-type
c. Base-type
d. PN-type

7. Compared to the collector and emitter, the base section of a transistor

is _____.

a. very thick
b. very thin
c. very soft
d. very hard

8. In a transistor, the base current is ______ when compared to the

collector and emitter currents.

a. small
b. large
c. fast
d. slow

9. A bipolar transistor is constructed so that its base region is very thin

and _____.

a. heavily doped
b. doped the same as the collector
c. lightly doped
d. doped the same as the emitter

10. The collector current of a transistor is always __________.

a. much lower than its emitter current

b. lower than its base current
c. equal to the emitter current
d. equal to the emitter current minus base current

11. During normal operation of an NPN transistor, most electrons

entering the emitter terminal ____________.

a. leave the transistor through the collector terminal

b. leave the transistor through the base terminal

173
c. are absorbed by the transistor
d. none of the above

12. Which equation expresses the correct relationship between the base,
emitter, and collector currents?

a. IE = IB + β
b. IC = IB + IE
c. IE = IB + IC
d. IB = IE + IC

13. The ratio of collector current to base current is called ______.

a. rho
b. pi
c. omega
d. beta
e. alpha

14. When a transistor switch is in saturation, VCE is approximately equal

to ______.

a. Vcc
b. VB
c. 0.2 V
d. 0.7 V

15. When a transistor switching circuit is on, the collector current is

limited by __________.

a. the base current

150 Chapter 4 The Bipolar Transistor
b. the load resistance
c. the base voltage
d. the base resistance

16. When a transistor switch is cut off, VCE is approximately equal to

______.

a. Vcc
b. VB
c. 0.2 V

174
d. 0.7 V

17. When the transistor amplifier is biased properly for class-A operation,
the _______.

a. base/emitter junction is forward biased and the base/collector junction

is reverse biased
b. base/emitter junction is reverse biased and the base/collector junction
is reverse biased
c. base/emitter junction is forward biased and the base/collector junction
is forward biased
d. base/emitter junction is reverse biased and the base/collector junction
is forward biased

18. For class-A amplifier operation, the collector/base junction of the

transistor has to be ______.
a. an open circuit
b. a closed circuit
c. forward biased
d. reverse biased

19. The voltage gain of a transistor amplifier is equal to _______.

a. VB/VE
b. Vin/Vout
c. Vout/Vin
d. Vcc/Vc

20. The drawing of the relation between collector voltage and base
voltage in the common emitter circuit is:

21- The correct for the npn transistor is:

175
22- The used symbol for the pnp transistor is:

176
 Ch.4
FET and MOSFETs
Transistors

177
4-1 Introduction
The field-effect transistor (FET) is a three-terminal semiconductor
device used for a variety of applications that match, to a large extent,
those of the BJT transistor described in Chapters 3(used extensively in
digital and analog circuits). Although there are important differences
between the two types of devices, there are also many similarities that
will be pointed out in the sections to follow. FET is the second major
type of transistor. There are two general classes of FETs:
- The junction FETs (JFET
- The Metal Oxide Semiconductor FET (MOSFET)
The two types operate with the same idea that is : current control is
carried out using electric field. Sure there are some differences we
indicates at the moment. The most widely used FETs are Metal-Oxide-
Semiconductor FETs (or MOSFET). MOSFET (shortly also called MOS)
can be manufactured as:
- enhancement-type or
- depletion-type MOSFETs.
The primary difference between the two types of transistors is the fact
that the BJT transistor is a current-controlled device as depicted in Fig.
4.1a, while the FET transistor is a voltage-controlled device as shown in
Fig. 4.1b. In other words, the current IC in Fig. 4.1a is a direct function
of the level of IB. For the FET the current I will be a function of the
voltage VGS applied to the input circuit as shown in Fig. 4.1b. In each
case the current of the output circuit is being controlled by a parameter of
the input circuit—in one case a current level and in the other an applied
voltage.

Fig. 4.1 Difference between BJT and JFET

178
 FET operation depends upon the flow of majority carriers only . It is
therefore a unipolar (one type of carrier) device ( in bipolar BJT
conduction depends on the two types). It is less noisy than bipolar
device. Just as there are npn and pnp bipolar transistors, there are n-
channel and p-channel field-effect transistors. However, it is important to
keep in mind that the BJT transistor is a bipolar device—the prefix bi-
revealing that the conduction level is a function of two charge carriers,
electrons and holes. The FET is a unipolar device depending solely on
either electron (n-channel) or hole (p-channel) conduction.

The term field-effect in the chosen name deserves some explanation.

We are all familiar with the ability of a permanent magnet to draw metal
filings to the magnet without the need for actual contact. The magnetic
field of the permanent magnet has enveloped the filings and attracted
them to the magnet through an effort on the part of the magnetic flux
lines to be as short as possible. For the FET an electric field is established
by the charges present that will control the conduction path of the output
circuit without the need for direct contact between the controlling and
controlled quantities. There is a natural tendency when introducing a
second device with a range of applications similar to one already
introduced to compare some of the general characteristics of one versus
the other. One of the most important characteristics of the FET is its high
input impedance. At a level of 1 to several hundred megohms it far
exceeds the typical input resistance levels of the BJT transistor
configurations—a very important characteristic in the design of linear ac
amplifier systems. On the other hand, the BJT transistor has a much
higher sensitivity to changes in the applied signal. In other words, the
variation in output current is typically a great deal more for BJTs than
FETs for the same change in applied voltage. For this reason, typical ac
voltage gains for BJT amplifiers are a great deal more than for FETs. In
general, FETs are more temperature stable than BJTs, and FETs are
usually smaller in construction than BJTs, making them particularly
useful in integrated-circuit (IC) chips. The construction characteristics of
some FETs, however, can make them more sensitive to handling than
BJTs.
Two types of FETs will be introduced in this chapter: the junction
field-effect transistor (JFET) and the metal-oxide-semiconductor field-
effect transistor (MOSFET).
The MOSFET category is further broken down into:

- depletion and
- enhancement types, which are both described.

179
 The MOSFET transistor has become one of the most important devices
used in the design and construction of integrated circuits for digital
computers. Its thermal stability and other general characteristics make it
extremely popular in computer circuit design.
Once the FET construction and characteristics have been introduced,
the biasing arrangements will be covered. We begin firstly with JFET
then MOSDFET.

4.2 Construction and Characteristics of JFETs

4.2.1 Symbols
The graphic symbols for the n-channel and p-channel JFETs are provided
in Fig. 4.2. Note that the arrow is pointing in for the n-channel device of
Fig. 4.2a to represent the direction in which IG would flow if the p-n
junction were forward-biased. For the p-channel device (Fig 4.2b) the
only difference in the symbol is the direction of the arrow.

Fig.4.2 JFET circuit symbols

4.2.2 Construction
As indicated earlier, the JFET is a three-terminal device with one terminal
capable of controlling the current between the other two. In our
discussion of the BJT transistor the npn transistor was employed through
the major part of the analysis and design sections, with a section devoted
to the impact of using a pnp transistor. For the JFET transistor the n-

180
channel device will appear as the prominent device, with paragraphs and
sections devoted to the impact of using a p-channel JFET.
Practical construction of FET
The basic construction of the n-channel JFET is shown in Fig. 4.3.
Note that the major part of the structure is the n-type material that forms
the channel between the embedded layers of p-type material. The top of
the n-type channel is connected through an ohmic contact to a terminal
referred to as the drain (D), while the lower end of the same material is
connected through an ohmic contact to a terminal referred to as the source
(S). The two p-type materials are connected together and to the gate (G)
terminal. In essence, therefore, the drain and source are connected to the
ends of the n-type channel and the gate to the two layers of p-type
material. In the absence of any applied potentials the JFET has two p-n
junctions under no-bias conditions. The result is a depletion region at
each junction as shown in Fig. 4.3 that resembles the same region of a
diode under no-bias conditions. Recall also that a depletion region is that
region void of free carriers and therefore unable to support conduction
through the region.

Fig.4.3 Junction field-effect transistor (JFET).

181
Analogies are seldom perfect and at times can be misleading, but the
water analogy of Fig. 4.4 does provide a sense for the JFET control at the
gate terminal and the appropriateness of the terminology applied to the
terminals of the device. The source of water pressure can be likened to
the applied voltage from drain to source that will establish a flow of water
(electrons) from the spigot (source). The ―gate,‖ through an applied signal
(potential), controls the flow of water (charge) to the ―drain.‖ The drain
and source terminals are at opposite ends of the n-channel as introduced
in Fig. 4.3 because the terminology is defined for electron flow.

Fig.4.4 Water analogy for the JFET control mechanism.

4.2.3 Characteristics:
When :VGS = 0 V, VDS Some Positive Value

In Fig. 4.5 , a positive voltage VDS has been applied across the channel
and the gate has been connected directly to the source to establish the
condition VGS = 0 V.
The result is a gate and source terminal at the same potential and a
depletion region in the low end of each p-material similar to the
distribution of the no-bias conditions of Fig. 4.3.
The instant the voltage VDD (= VDS) is applied, the electrons will be
drawn to the drain terminal, establishing the conventional current I D with
the defined direction of Fig. 4.5. The path of charge flow clearly reveals
that the drain and source currents are equivalent (ID = IS). Under the
conditions appearing in Fig. 4.5, the flow of charge is relatively
uninhibited and limited solely by the resistance of the n-channel between

182
drain and source. Fig.4.6 displays practical FET structure using epitaxial
planar technology.

Fig. 4.5

Fig.4.6

183
 It is important to note that the depletion region is wider near the top of
both p-type materials. The reason for the change in width of the region is
best described through the help of Fig. 4.7. Assuming a uniform
resistance in the n-channel, the resistance of the channel can be broken
down to the divisions appearing in Fig. 4.7. The current ID will establish
the voltage levels through the channel as indicated on the same figure.
The result is that the upper region of the p-type material will be reverse
biased by about 1.5 V, with the lower region only reverse-biased by 0.5
V. Recall from the discussion of the diode operation that the greater the
applied reverse bias, the wider the depletion region—hence the
distribution of the depletion region as shown in Fig. 4.7. The fact that the
p-n junction is reverse-biased for the length of the channel results in a
gate current of zero amperes as shown in the same figure. The fact
that IG = 0 A is an important characteristic of the JFET.

4.2.4 Pinch-Off
As the voltage VDS is increased from 0 to a few volts, the current will
increase as determined by Ohm‘s law and the plot of ID versus VDS will
appear as shown in Fig. 4.8. The relative straightness of the plot reveals
that for the region of low values of VDS, the resistance is essentially
constant. As VDS increases and approaches a level referred to as VP in
Fig. 4.8, the depletion regions of Fig. 4.5 will widen, causing a noticeable
reduction in the channel width. The reduced path of conduction causes
the resistance to increase and the curve in the graph of Fig. 4.8 to occur.
The more horizontal the curve, the higher the resistance, suggesting that
the resistance is approaching ―infinite‖ ohms in the horizontal region. If
VDS is increased to a level where it appears that the two depletion regions
would ―touch‖ as shown in Fig. 4.9, a condition referred to as pinch-off
will result. The level of VDS that establishes this condition is referred to as
the pinch-off voltage and is denoted by VP as shown in Fig. 4.8. In
actuality, the term pinch-off is a misnomer in that it suggests the current
ID is pinched off and drops to 0 A. As shown in Fig. 4.8, however, this is
hardly the case— ID maintains a saturation level defined as IDSS in Fig.
4.8. In reality a very small channel still exists, with a current of very high
density. The fact that ID does not drop off at pinch-off and maintains the
saturation level indicated in Fig. 4.8 is verified by the following fact: The
absence of a drain current would remove the possibility of different
potential levels through the n-channel material to establish the varying
levels of reverse bias along the p-n junction. The result would be a loss of
the depletion region distribution that caused pinch-off in the first place.

184
Fig.4.7

Fig.4.8

185
 Fig.4.9

As VDS is increased beyond VP, the region of close encounter between

the two depletion regions will increase in length along the channel, but
the level of ID remains essentially the same. In essence, therefore, once
VDS > VP the JFET has the characteristics of a current source. As shown
in Fig. 10, the current is fixed at ID = IDSS, but the voltage VDS (for levels
>VP) is determined by the applied load.

Fig. 4.10 Current source equivalent for VGS = 0 V , VDS > VP.

186
The choice of notation IDSS is derived from the fact that it is the Drain-to-
Source current with a Short-circuit connection from gate to source. As we
continue to investigate the characteristics of the device we will find that:

IDSS is the maximum drain current for a JFET and is defined by the
conditions:

VGS = 0 V and VDS > |VP|.

Note in Fig. 4.8 that VGS = 0 V for the entire length of the curve. The
next few paragraphs will describe how the characteristics of Fig. 4.8 are
affected by changes in the level of VGS.

4.3 Current –voltage characteristics

We saw that both iG(gate current) and iB(bulk current /substrate) are zero.
Therefore, the current entering the drain must be equal to the current
leaving the source:

iS = iD (1)

An expression for the drain current iD can be defined by considering the

transport of charge in the channel, which is depicted for a small value of
vDS.
As the applied gate- to –source voltage changes, the iD versus vDS curve
changes. In Fig. 4. 8 above , the initial slope of iD versus vDS increase as
vGS increase. At saturation (for vGS = 0 V ) the drain becomes constant
when:
VDS > VDS(sat) and this region of the characteristics is called saturation
region. Also the figure shows that at pinch off :
- Any increase in VGS does not produce any increase in iD . The
voltage VG at pinch off is called VP.
- At saturation ID has maximum value called IDSS.
- At saturation, the channel ohmic resistance has its maximum value.

187
Since change of VGS gives change in iD versus vDS curve and also the
saturation voltage vDS (sat) is also function of VGS , so we can generate
the family of curves of n-channel enhancement mode MOSFETs.

Although the derivation of the current –voltage characteristics of the

MOSFETs is beyond the scope of this text, we can define the
relationships.

4.3.1 Nonsaturation (or Triode) Region:

This is the region for which vDS < vDS (sat) . The ideal current-voltage
characteristics in this region are described by the equation:

iD = Kn{ 2 (VGS - VTN ) VDS - V2DS } (2)

4.3.2 Saturation Region:

The ideal current-voltage characteristics when VGS > VTN are
described by the equation :
iD = Kn (VGS - VTN )2 (3)

In the saturation region, since the ideal drain current is independent of the
drain-to- source voltage, the incremental or small resistance is infinite.
We see that :

r0 = ∆ VDS /∆ iD | vGS = const = infinity (4)

The parameter Kn is called the conduction parameter for the n-channel

device and is given by:

Kn = W μn C0x / 2L (5)

Where ; C0x is the oxide capacitance per unit area. The capacitance is
given by :

C0x = ε0x / t0x

Where: t0x is the oxide thickness ( Fig.4.11 ) and ε0x is the oxide
permittivity. For silicon :

188
ε0x =(3.9)(8.85 x 10-14) F/cm.

Fig .4 .11

The parameter μn is the mobility of electrons in the inversion layer (

Fig.4.11 ). The channel width W and the channel length L are shown in
Fig.4.11. The oxide capacitance and carrier mobility are essentially
constants for a given fabrication technology. However, the geometry, or
width – to- length ratio W/L is a variable in the design of MOSFETs that
is used to produce specific current – voltage characteristics in MOSFET
circuits.

4.4 When :VGS < 0 V :

The voltage from gate to source, denoted VGS, is the controlling voltage
of the JFET. Just as various curves for IC versus VCE were established for
different levels of IB for the BJT transistor, curves of ID versus VDS for
various levels of VGS can be developed for the JFET. For the n-channel
device the controlling voltage VGS is made more and more negative from
its VGS = 0 V level. In other words, the gate terminal will be set at lower
and lower potential levels as compared to the source.
In Fig. 4.12 a negative voltage of -1 V has been applied between the
gate and source terminals for a low level of VDS. The effect of the applied
negative-bias VGS is to establish depletion regions similar to those
obtained with VGS = 0 V but at lower levels of VDS. Therefore, the result
of applying a negative bias to the gate is to reach the saturation level at a

189
lower level of VDS as shown in Fig. 4.13 for VGS = - 1 V. The resulting
saturation level for ID has been reduced and in fact will continue to
decrease as VGS is made more and more negative. Note also on Fig. 4.13
how the pinch- off voltage continues to drop in a parabolic manner as VGS
becomes more and more negative. Eventually, VGS when VGS = -VP will
be sufficiently negative to establish a saturation level that is essentially
0 mA, and for all practical purposes the device has been ―turned off.‖ In
summary:
The level of VGS that results in ID = 0 mA is defined by VGS = VP, with VP
being a negative voltage for n-channel devices and a positive voltage for
p-channel JFETs.
On most specification sheets the pinch-off voltage is specified as VGS
(off) rather than VP. A specification sheet will be reviewed later in the
chapter when the primary elements of concern have been introduced. The
region to the right of the pinch-off locus of Fig. 4.13 is the region
typically employed in linear amplifiers (amplifiers with minimum
distortion of the applied signal) and is commonly referred to as the:
constant-current, saturation, or linear amplification region.

Fig.4.12 Application of a negative voltage to the gate of a JFET.

190
 Fig. 4.13 n-Channel JFET characteristics with IDSS = 8 mA and
VP = -4 V.

4.4.1 Voltage-Controlled Resistor

The region to the left of the pinch-off locus of Fig. 4.13 is referred to as
the ohmic or voltage-controlled resistance region. In this region the JFET
can actually be employed as a variable resistor (possibly for an automatic
gain control system) whose resistance is controlled by the applied gate-to-
source voltage. Note in Fig. 4.13 that the slope of each curve and
therefore the resistance of the device between drain and source for VDS >
VP is a function of the applied voltage VGS. As VGS becomes more and
more negative, the slope of each curve becomes more and more
horizontal, corresponding with an increasing resistance level. The
following equation will provide a good first approximation to the
resistance level in terms of the applied voltage VGS.

rd = ro / [ 1 - VGS / VP]2 (6)

where ro is the resistance with VGS = 0 V and rd the resistance at a

particular level of VGS.
For an n-channel JFET with ro equal to 10 kΩ (VGS = 0, VP = - 6 V),
Eq. (6) will result in 40 kΩ at VGS =3 V.

191
4.5 p-Channel Devices

The p-channel JFET is constructed in exactly the same manner as the n-

channel device of Fig. 4.3, but with a reversal of the p- and n-type
materials as shown in Fig. 4.14.

Fig.4.14 p-Channel JFET

The defined current directions are reversed, as are the actual polarities for
the voltages VGS and VDS. For the p-channel device, the channel will be
constricted by increasing positive voltages from gate to source and the
double-subscript notation for VDS will result in negative voltages for VDS
on the characteristics of Fig. 4.15, which has an IDSS of 6 mA and a pinch-
off voltage of VGS = + 6 V. Do not let the minus signs for VDS confuse
you. They simply indicate that the source is at a higher potential than the
drain.

192
Fig.4.15 p-Channel JFET characteristics with IDSS = 6 mA and
VP = +6V.

Note at high levels of VDS that the curves suddenly rise to levels that
seem unbounded. The vertical rise is an indication that breakdown has
occurred and the current through the channel (in the same direction as
normally encountered) is now limited solely by the external circuit.
Although not appearing in Fig. 4.13 for the n-channel device, they do
occur for the n-channel device if sufficient voltage is applied. This region
can be avoided if the level of VDSmax is noted on the specification sheet
and the design is such that the actual level of VDS is less than this value
for all values of VGS.

From the above it is to be noted for the n-channel that:

-The maximum current is defined as IDSS and occurs when VGS = 0 V

and VDS ≥ |VP| as shown in Fig. 4.16 a.

-For gate-to-source voltages VGS less than (more negative than) the
pinch-off level, the drain current is 0 A (ID = 0 A) as appearing in Fig.
4.16 b.

-For all levels of VGS between 0 V and the pinch-off level, the current ID
will range between IDSS and 0 A, respectively, as reviewed by Fig. 4.16 c.

193
-For p-channel JFETs a similar list can be developed.

Fig. 4.16 (a) VGS = 0 V, ID = IDSS ; (b) cutoff (ID = 0 A) VGS less than the
pinch-off level; (c) ID exists between 0 A and IDSS for VGS less than or
equal to 0 V and greater than the pinch-off level.

194
4.6 Transfer Characteristics
For the BJT transistor the output current IC and input controlling current
IB were related by beta, which was considered constant for the analysis to
be performed. In equation form,

IC = f(IB) = β IB (7)

It it is to be noted in this relation that :

- IB is a control variable
- Β is constant

Also in this equation, a linear relationship between IC and IB. Double the
level of IB and IC will increase by a factor of two also.

Unfortunately, this linear relationship does not exist between the output
and input quantities of a JFET. The relationship between ID and VGS is
defined by Shockley’s equation:

ID = IDSS [ 1 – (VGS / Vp )]2 (8)

Where : IDSS , Vp are constants while VGS is control variable. The square
term of the equation will result in a nonlinear relationship between ID and
VGS, producing a curve that grows exponentially with decreasing
magnitudes of VGS For the dc analysis to be performed, a graphical rather
than mathematical approach will in general be more direct and easier to
apply. The graphical approach, however, will require a plot of Eq. (8) to
represent the device and a plot of the network equation relating the same
variables. The solution is defined by the point of intersection of the two
curves. It is important to keep in mind when applying the graphical
approach that the device characteristics will be unaffected by the network
in which the device is employed. The network equation may change
along with the intersection between the two curves, but the transfer curve
defined by Eq. (8) is unaffected. In general, therefore:

The transfer characteristics defined by Shockley’s equation are

unaffected by the network in which the device is employed.
195
The transfer curve can be obtained using Shockley‘s equation or from the
output characteristics of Fig. 4.13. In Fig. 4.17 two graphs are provided,

Fig. 4.17 Obtaining the transfer curve from the drain characteristics.

with the vertical scaling in mill -amperes for each graph. One is a plot of
ID versus VDS, while the other is ID versus VGS. Using the drain
characteristics on the right of the ―y‖ axis, a horizontal line can be drawn
from the saturation region of the curve denoted VGS = 0 V to the ID axis.
The resulting current level for both graphs is IDSS. The point of
intersection on the ID versus VGS curve will be as shown since the vertical
axis is defined as VGS = 0 V .

In review:

When :VGS = 0 V , ID = IDSS.

When VGS = Vp = - 4 V, the drain current is zero milli-amperes, defining

another point on the transfer curve. That is:

196
When VGS = Vp , ID = 0 mA.

Before continuing, it is important to realize that the drain characteristics

relate one output (or drain) quantity to another output (or drain)
quantity—both axes are defined by variables in the same region of the
device characteristics. The transfer characteristics are a plot of an output
(or drain) current versus an input-controlling quantity. There is therefore
a direct ―transfer‖ from input to output variables when employing the
curve to the left of Fig. 4.17. If the relationship were linear, the plot of
ID versus VGS would result in a straight line between IDSS and VP.
However, a parabolic curve will result because the vertical spacing
between steps of VGS on the drain characteristics of Fig. 4.17 decreases
noticeably as VGS becomes more and more negative. Compare the
spacing between VGS = 0 V and VGS = - 1 V to that between VGS = -3 V
and pinch-off. The change in VGS is the same, but the resulting change
in ID is quite different.
If a horizontal line is drawn from the VGS = - 1 V curve to the ID axis
and then extended to the other axis, another point on the transfer curve
can be located. Note that VGS = - 1 V on the bottom axis of the transfer
curve with ID = 4.5 mA. Note in the definition of ID at VGS = 0 V and -1
V that the saturation levels of ID are employed and the ohmic region
ignored. Continuing with VGS = - 2 V and -3 V, the transfer curve can be
completed. It is the transfer curve of ID versus VGS that will receive
extended use in the analysis and not the drain characteristics of Fig. 4.17.

Shortly we can summarize the steps of plotting the JFET Transfer Curve
as follows :

Using IDSS and Vp (VGS(off)) values found in a specification sheet, the

transfer curve can be plotted according to these three steps:

Step 1

ID = IDSS [ 1 – (VGS / Vp )]2

Solving for VGS = 0 V and ID= IDSS P

Step 2

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 ID = IDSS [ 1 – (VGS / Vp )]2

Solving for VGS = Vp (VGS(off)), ID= 0A

Step 3
Solving for VGS = 0 V to Vp ,

ID = IDSS [ 1 – (VGS / Vp )]2

4.7 Circuit Configurations for FET

Fig.4. 18 shows the three ways in which FET( junction type or depletion
and enhancement) can be connected in the circuit:
- common –source ( CS )
- common –Drain ( CD )
- common –Gate ( CG )
These configuration shown in the figure are for p-channel JFET

Fig.4. 18.

4.8 Important Relationships (Analogy between JFET and

BJT):

198
A number of important equations and operating characteristics have been
introduced in the last few sections that are of particular importance for the
analysis to follow for the dc and ac configurations. In an effort to isolate
and emphasize their importance, they are repeated below next to a
corresponding equation for the BJT transistor. The JFET equations
are defined for the configuration of Fig. 4.19a, while the BJT equations
relate to Fig. 4.19b.

Fig. 4.19 (a) JFET versus (b) BJT.

(9)

4.9 Thermal Effect

Here it is to be noted that : Rise of temperature in BJT makes it loses its
job as a transistor and the increase of power consumption (collector side

199
in general) which is due to current increase , rises temperature more. This
is called thermal runaway which can damage the normal transistor. In
FET this phenomena (thermal runaway ) does not occur Since power
consumption decreases with temperature rise ( because drain current
decreases with temperature rise .

4.10 The Metal Oxide Semiconductor Transistor (MOSFET)

(MOSFET (shortly MOS) is without doubt the most commercially
successful solid-state device. It is the primary component in high-density
VLSI chips, including microprocessors and memories.
At the heart of the MOSFET is the MOS capacitor, formed by a metallic
gate electrode insulated from the semiconductor by an insulating oxide
layer. The potential on the gate controls the carrier concentration in the
semiconductor region directly beneath the gate; three regions of operation
of the MOS capacitor were identified: accumulation, depletion,
and inversion.
A MOSFET is formed when two pn junctions are added to the
semiconductor region of the MOS capacitor. The junctions act as the
source and drain terminals of the MOS transistor and provide a ready
supply of carriers for the channel region of the MOSFET. The source and
drain junctions must be kept reverse-biased at all times in order to isolate
the channel from the substrate.
MOS transistors can be fabricated with either n- or p-type channel
regions and are referred to as NMOS or PMOS transistors, respectively.
In addition, MOSFETs can be fabricated as either enhancement-mode or
depletion-mode devices.
For an enhancement-mode device, a gate-source voltage exceeding the
threshold voltage must be applied to the transistor to establish a
conducting channel between source and drain.
In the depletion-mode device, a channel is built into the device during
its fabrication, and a voltage must be applied to the transistor‘s gate to
quench conduction.
As mentioned in the begging of this chapter the JFET uses pn junctions
to control the resistance of the conducting channel region. The gate-
source voltage modulates the width of the depletion layers surrounding
the gate channel junctions and thereby changes the width of the channel
region. A JFET can be fabricated with either n- or p-type channel regions,
but because of its structure, the JFET is inherently a depletion-mode
device.

200
 Both the MOSFET and JFET are symmetrical devices. The source and
drain terminals of the device are actually determined by the voltages
applied to the terminals. For a given geometry and set of voltages, the n-
channel transistor will conduct two to three times the current of the p-
channel device because of the difference between the electron and hole
mobilities in the channel.

4.11 The MOS Capacitor

An understanding of the qualitative behavior of the MOS capacitor
provides a basis for understanding operation of the MOSFET. At the
heart of the MOSFET is the MOS capacitor structure depicted in Fig.
4.20 a. The MOS capacitor is used to induce charge at the interface
between the semiconductor and oxide. The top electrode of the MOS
capacitor is formed of a low-resistivity material, typically aluminum or
heavily doped polysilicon (polycrystalline silicon). We refer to this
electrode as the gate (G) for reasons that become apparent shortly. A thin
insulating layer, typically silicon dioxide, isolates the gate from the
substrate or body—the semiconductor region that acts as the second
electrode of the capacitor. Silicon dioxide is a stable, high-quality
electrical insulator readily formed by thermal oxidation of the silicon
substrate. The ability to form this stable high-quality insulator is one of
the basic reasons that silicon is the dominant semiconductor material
today. The semiconductor region may be n- or p-type, as depicted in Fig.
4.20a. It is to be noted that when apply voltage to the gate terminal , the
resistance between the source and drain is the same resistance between
the two terminals of two diodes connected back –to back as in Fig .4.20
b, of course this means the resistance is very high (specially silicon
fabrication).
The semiconductor forming the bottom electrode of the capacitor has a
substantial resistivity and a limited supply of holes and electrons.
Because the semiconductor can therefore be depleted of carriers, as
discussed in Chapter 2, the capacitance of this structure is a nonlinear
function of voltage. Figure 4.2 shows the conditions in the region of the
substrate immediately below the gate electrode for three different bias
conditions: accumulation, depletion, and inversion.

201
 (a)

(b)
Fig. 4.20

When negative voltage is applied to the gate as in Fig.4.21 . The

Fig.4.21a shows parallel plate capacitor (top plate at a negative voltage
with respect to bottom plate) where , as seen , negative charges exist on
the top plate while positive charges exist on the bottom plate and an
electric field field is induced between the two plates.

A MOS capacitor with a p-type semiconductor substrate is shown in Fig.

4.21b. The top metal terminal is also called the gate , is at negative
voltage with respect to bottom plate) . The equilibrium distribution of
charge in the MOS capacitor with this particular applied voltage is shown
in Fig.4.21c. An accumulation layer of positively charged holes in the
oxide-semiconductor junction corresponds to positive charge on the
bottom plate of the MOS capacitor.

202
 Fig.4.22a shows the same MOS capacitor, but with the polarity of the
applied voltage is reversed. A positive charge now exists on the top metal
plate and the induced electric field is in the opposite direction as shown.

Fig.4.21

Fig.4.22

203
In this case if the electric field penetrates the semiconductor , holes in the
p-type material will experience a force away from the oxide-
semiconductor interface. As the holes are pushed away from the interface
space charge region is created , due to the fixed acceptor impurity atoms.
The negative charge in the induced depletion region corresponds to the
negative charge in the bottom plate of the MOS capacitor. Fig.4.22 b
shows the equilibrium distribution of charge in the MOS capacitor with
this applied voltage.

When a large positive voltage is applied to the gate , the magnitude of the
induced electric field increases. Minority carrier electrons are attracted to
the oxide-semiconductor interface, as shown in fig.4.22c. This region of
minority carrier electrons is called an electron inversion layer. The
magnitude of the charge in the inversion layer is a function of the applied
gate voltage.

The same basic charge distribution can be obtained in a MOS capacitor

with the n-type semiconductor substrate. Fig.4.23 a shows this MOS
capacitor structure , with a positive voltage applied to the top gate
terminal. A positive charge is created on the top gate and an electric field
is induced in the direction shown. In this situation, an accumulation layer
of electrons is induced in the n-type semiconductor. Fig.4.23 b shows the
case when a negative voltage is applied to the gate terminal. A positive
space charge region is induced in the n-type substrate by the induced
electric field. When a large negative voltage is applied, a region of
positive charge is created at the oxide-semiconductor interface as shown
in Fig.4.23c. This region of minority carrier holes is called a hole
inversion layer. The magnitude of the positive charge in the inversion
layer is a function of the applied gate voltage.

Fig.4.23
204
 The term enhanced mode means that a voltage must applied to the gate
to create an inversion layer. For the MOS capacitor with a p-type
substrate , a positive gate voltage must be applied to create the electron
inversion layer, for the MOS capacitor with an n-type substrate, a
negative gate voltage must be applied to create the hole inversion layer.

4.12 n- Channel Enhanced-Mode MOSFET

4.12.1 Basic Construction
A MOSFET is formed by adding two heavily doped n-type (n+)
diffusions to the cross section of Fig. 4.24, resulting in the structure in
Fig. 4.25. The diffusions provide a supply of electrons that can readily
move under the gate as well as terminals that can be used to apply a
voltage and cause a current in the transistor.

Fig.4.24 MOS capacitor structure on p-type silicon.

Figure 4.25 shows a planar view, cross section, and circuit symbol of an
n-channel MOSFET, usually called an NMOS transistor, or
NMOSFET. The central region of the MOSFET is the MOS capacitor
discussed above, and the top electrode of the capacitor is called the gate

205
of the MOSFET. The two heavily doped n-type regions (n+ regions),
called the source (S) and drain (D), are formed in the p-type substrate
aligned with the edge of the gate. The source and drain provide a supply
of carriers so that the inversion layer can rapidly form in response to the
gate voltage. The substrate of the NMOS transistor represents a fourth
device terminal and is referred to synonymously as the substrate
terminal, or the body terminal (B).

The terminal voltages and currents for the NMOS device are also
defined in Fig. 4.25(b). The drain current iD, source current iS, gate
current iG, and body current iB are all defined, with the positive direction
of each current indicated for an NMOS transistor. The important terminal
voltages are the gate-source voltage:

vGS = vG −vS

the drain-source voltage :

vDS = vD −vS

and the source-bulk voltage :

vSB = vS − vB.

These voltages are all positive during normal operation of the

NMOSFET.

Note that the source and drain regions form pn junctions with the
substrate. These two junctions are kept reverse-biased at all times to
provide isolation between the junctions and the substrate as well as
between adjacent MOS transistors. Thus, the bulk voltage must be less
than or equal to the voltages applied to the source and drain terminals to
ensure that these pn junctions are properly reverse-biased.
The semiconductor region between the source and drain regions
directly below the gate is called the channel region(no channel exist but
the area of channel which will be formed) of the FET, and two
dimensions of critical import are defined in Fig. 4.25. L represents the

206
Fig. 4.25(a) NMOS transistor structure; (b) cross section; and (c) circuit
symbol.

channel length, which is measured in the direction of current in the

channel. W is the channel width, which is measured perpendicular to the
direction of current. Choosing the values for W and L are an important
aspect of the digital and analog IC designer‘s task.
Note in Fig. 4.25 the absence of a channel between the two n-doped
regions (only channel region exists but channel appear during operation).
This is the primary difference between the construction of depletion-type
(explained later) and enhancement-type MOSFETs—the absence of a
channel as a constructed component of the device. The SiO2 layer is
present to isolate the gate metallic platform from the region between the
drain and source, but now it is simply separated from a section of the p-
type material. In summary, therefore, the construction of an
enhancement-type MOSFET is quite similar to that of the depletion-type

207
MOSFET, except for the absence of a channel between the drain and
source terminals.

4.12.2 Basic Operation

Let us try to develop a qualitative understanding of what we might expect
by referring to Fig. 4. 26. In the figure, the source, drain, and body of the
NMOSFET are all grounded.
For a dc gate-source voltage, vGS = VGS, well below the threshold
voltage VTN, as in Fig. 4.26(a), back-to-back pn junctions exist between
the source and drain, and only a small leakage current can flow between
these two terminals. For VGS near but still below threshold, a depletion
region forms beneath the gate and merges with the depletion regions of
the source and drain, as indicated in Fig. 4.26(b). The depletion region is
devoid of free carriers, so a current still does not appear between the
source and drain. Finally, however, when the gate-channel voltage
exceeds the threshold voltage VTN, as in Fig. 4.26(c), electrons flow in
from the source and drain to form an inversion layer that connects the n+
source region to the n+ drain. A resistive connection, the channel, exists
between the source and drain terminals.

If a positive voltage is now applied between the drain and source

terminals, electrons in the channel inversion layer will drift in the electric
field, creating a current in the terminals. Positive current in the NMOS
transistor enters the drain terminal, travels down the channel, and exits
the source terminal, as indicated by the polarities in Fig. 4.25(b). The gate
terminal is insulated from the channel; thus, there is no dc gate current,
and iG = 0. The drain-bulk and source-bulk (and induced channel-to-
bulk) pn junctions must be reverse-biased at all times to ensure that only
a small reverse-bias leakage current exists in these diodes. This current is
usually negligible with respect to the channel current iD and is neglected.
Thus we assume that iB = 0.

In the device in Fig. 4.26, a channel must be induced by the applied

gate voltage for conduction to occur. The gate voltage ―enhances‖ the
conductivity of the channel; this type of MOSFET is termed an
enhancement-mode device. Later in this chapter we identify an
additional type of MOSFET called a depletion-mode device.

208
 Figure 4.26 (a) VGS = VTN. (b) VGS < VTN. (c) VGS > VTN.

4.13 Characteristics of Enhanced-Mode MOSFET:

To study i-v characteristics of Enhanced-Mode MOSFET, let us see Fig.
4.27 both VDS and VGS have been set at some positive voltage greater than
0 V, establishing the drain and gate at a positive potential with respect to
the source. The positive potential at the gate will pressure the holes (since
like charges repel) in the p-substrate along the edge of the SiO2 layer to
leave the area and enter deeper regions of the p-substrate, as shown in the
figure. The result is a depletion region near the SiO2 insulating layer void

209
of holes. However, the electrons in the p-substrate (the minority carriers
of the material) will be attracted to the positive gate and accumulate in
the region near the surface of the SiO2 layer. The SiO2 layer and its
insulating qualities will prevent the negative carriers from being absorbed
at the gate terminal. As VGS increases in magnitude, the concentration of
electrons near the SiO2 surface increases until eventually the induced n-
type region can support a measurable flow between drain and source. The

Figure 4.27 Channel formation in the n-channel enhancement type

MOSFET.

level of VGS that results in the significant increase in drain current is

called the threshold voltage and is given the symbol VT. On specification
sheets it is referred to as VGS (Th), although VT is less unwieldy and will
be used in the analysis to follow. Since the channel is nonexistent with
VGS = 0 V and ―enhanced‖ by the application of a positive gate-to-source
voltage, this type of MOSFET is called an enhancement-type MOSFET.
Both depletion- and enhancement-type MOSFETs have enhancement-
type regions, but the label was applied to the latter since it is its only
mode of operation.

210
As VGS is increased beyond the threshold level, the density of free carriers
in the induced channel will increase, resulting in an increased level of
drain current. However, if we hold VGS constant and increase the level of
VDS, the drain current will eventually reach a saturation level as occurred
for the JFET and depletion-type MOSFET. The leveling off of ID is due
to a pinching-off process depicted by the narrower channel at the drain
end of the induced channel as shown in Fig. 4.28. Applying Kirchhoff‘s

Fig. 4.28 Change in channel and depletion region with increasing level
of VDS for a fixed value of VGS.

voltage law to the terminal voltages of the MOSFET of Fig. 4.28, we find
that :

VDG = VDS - VGS (10)

If VGS is held fixed at some value such as 8 V and VDS is increased from 2
to 5 V, the voltage VDG [by Eq. (10)] will drop from -6 to -3 V and the
gate will become less and less positive with respect to the drain. This

211
reduction in gate-to-drain voltage will in turn reduce the attractive forces
for free carriers (electrons) in this region of the induced channel, causing
a reduction in the effective channel width. Eventually, the channel will be
reduced to the point of pinch-off and a saturation condition will be
established as described earlier for the JFET and depletion-type
MOSFET. In other words, any further increase in VDS at the fixed value
of VGS will not affect the saturation level of ID until breakdown
conditions are encountered.
The drain characteristics of Fig. 4.29 reveal that for the device of Fig.
4.28 with VGS = 8 V, saturation occurred at a level of VDS = 6 V. In fact,
the saturation level for VDS is related to the level of applied VGS by:

Fig. 4.29 Drain characteristics of an n-channel enhancement-type

MOSFET with VT = 2 V and k = 0.278 x 10-3 A/V2.

VDSsat = VGS - VT (11)

Obviously, therefore, for a fixed value of VT, then the higher the level of
VGS, the more the saturation level for VDS, as shown in Fig. 4.28 by the
locus of saturation levels.

212
For the characteristics of Fig. 4.28 the level of VT is 2 V, as revealed by
the fact that the drain current has dropped to 0 mA. In general, therefore:

For values of VGS less than the threshold level, the drain current of
an enhancement- type MOSFET is 0 mA.

Fig. 4.29 clearly reveals that as the level of VGS increased from VT to 8
V, the resulting saturation level for ID also increased from a level of 0 to
10 mA. In addition, it is quite noticeable that the spacing between the
levels of VGS increased as the magnitude of VGS increased, resulting in
ever-increasing increments in drain current.
For levels of VGS > VT, the drain current is related to the applied gate-to-
source voltage by the following nonlinear relationship:

ID = k(VGS - VT)2 (12)

Again, it is the squared term that results in the nonlinear (curved)

relationship between ID and VGS. The k term is a constant that is a
function of the construction of the device. The value of k can be
determined from the following equation [derived from Eq. (5.13)] where
ID(on) and VGS (on) are the values for each at a particular point on the
characteristics of the device.

k = ID(on) / [VGS(on) -VT ]2 (13)

Substituting ID(on) = 10 mA when VGS(on) = 8 V from the characteristics of

Fig. 4.29 yields;

k = ( 10 mA) / ( 8V – 2 V )2 = ( 10 mA) / ( 6 V )2 =( 10 mA) /36 V2

= 0.278 x 10-3 A/V2
and a general equation for ID for the characteristics of Fig. 4.29 results in:

ID = 0.278 x 10-3(VGS - 2 V)2

Substituting VGS = 4 V, we find that:

ID = 0.278 x 10-3 (4 V - 2 V)2 = 0.278 x 10-3 (2)2

= 0.278 x 10-3(4) = 1.11 mA

213
as verified by Fig. 4.29. At VGS = VT, the squared term is 0 and ID= 0 mA.
For the dc analysis of enhancement-type MOSFETs to appear in Chapter
6, the transfer characteristics will again be the characteristics to be
employed in the graphical solution. In Fig. 4.30 the drain and transfer
characteristics have been set side by side to describe the transfer process
from one to the other. Essentially, it proceeds as introduced earlier for the
JFET. In this case, however, it must be remembered that the drain current
is 0 mA for VGS = VT. At this point a measurable current will result for ID
and will increase as defined by Eq. (12). Note that in defining the points
on the transfer characteristics from the drain characteristics, only the
saturation levels are employed, thereby limiting the region of operation to
levels of VDS greater than the saturation levels as defined by Eq. (11).

Fig.4.30 Sketching the transfer characteristics for an n-channel

enhancement type MOSFET from the drain characteristics

4.14 Depletion Type MOSFET

As noted in the chapter introduction, there are two types of FETs: JFETs
and MOSFETs. MOSFETs are further broken down into depletion type
and enhancement type. The terms depletion and enhancement define their
basic mode of operation, while the label MOSFET stands for metal-
oxide-semiconductor-field-effect transistor. Since there are differences in
the characteristics and operation of each type of MOSFET, they are
covered in separate sections. In this section we examine the depletion-
214
type MOSFET, which happens to have characteristics similar to those of
a JFET between cutoff and saturation at IDSS but then has the added
feature of characteristics that extend into the region of opposite polarity
for VGS.

4.14.1 Basic Construction

The basic construction of the n-channel depletion-type MOSFET is

provided in Fig. 4.31. A slab of p-type material is formed from a silicon
base and is referred to as the substrate. It is the foundation upon which
the device will be constructed. In some cases the substrate is internally
connected to the source terminal. However, many discrete devices
provide an additional terminal labeled SS, resulting in a four-terminal
device, such as that appearing in Fig. 4.31. The source and drain
terminals are connected through metallic contacts to n-doped regions
linked by an n-channel as shown in the figure. The gate is also connected
to a metal contact surface but remains insulated from the n-channel by a
very thin silicon dioxide (SiO2) layer. SiO2 is a particular type of
insulator referred to as a dielectric that sets up opposing (as revealed by
the prefix di-) electric fields within the dielectric when exposed to an
externally applied field. The fact that the SiO2 layer is an insulating layer
reveals the following fact:
There is no direct electrical connection between the gate terminal and
the channel of a MOSFET.

In addition:
It is the insulating layer of SiO2 in the MOSFET construction that
accounts for the very desirable high input impedance of the device.

In fact, the input resistance of a MOSFET is often that of the typical

JFET, even though the input impedance of most JFETs is sufficiently
high for most applications. The very high input impedance continues to
fully support the fact that the gate current (IG) is essentially zero amperes
for dc-biased configurations.

215
 Fig. 4.31 n-Channel depletion-type MOSFET.

The reason for the label metal-oxide-semiconductor FET is now fairly

obvious: metal for the drain, source, and gate connections to the proper
surface—in particular, the gate terminal and the control to be offered by
the surface area of the contact, the oxide for the silicon dioxide insulating
layer, and the semiconductor for the basic structure on which the n- and
p-type regions are diffused. The insulating layer between the gate and
channel has resulted in another name for the device: insulated gate FET
or IGFET, although this label is used less and less in current literature.

4.14.2 Basic Operation and Characteristics

In Fig. 4.32 the gate-to-source voltage is set to zero volts by the direct
connection from one terminal to the other, and a voltage V DS is applied
across the drain-to-source terminals. The result is an attraction for the
positive potential at the drain by the free electrons of the n-channel and a
current similar to that established through the channel of the JFET. In
fact, the resulting current with VGS = 0 V continues to be labeled IDSS, as
shown in Fig. 4.33.

216
Fig. 4.32 n-Channel depletion-type MOSFET with VGS = 0 V and an
applied voltage VDD.

Fig. 4.33 Drain and transfer characteristics for an n-channel depletion-

type MOSFET.

217
In Fig. 4.34, VGS has been set at a negative voltage such as -1 V. The
negative potential at the gate will tend to pressure electrons toward the p-
type substrate (like charges repel) and attract holes from the p-type
substrate (opposite charges attract) as shown in Fig. 4.34. Depending on
the magnitude of the negative bias established by VGS, a level of
recombination between electrons and holes will occur that will reduce the
number of free electrons in the n-channel available for conduction. The
more negative the bias, the higher the rate of recombination. The
resulting level of drain current is therefore reduced with increasing
negative bias for VGS as shown in Fig. 4.33 for VGS = -1 V, -2 V, and so
on, to the pinch-off level of -6 V. The resulting levels of drain current and
the plotting of the transfer curve proceeds exactly as described for the
JFET.

Fig. 4.34 Reduction in free carriers in channel due to a negative

potential at the gate terminal

218
For positive values of VGS, the positive gate will draw additional
electrons (free carriers) from the p-type substrate due to the reverse
leakage current and establish new carriers through the collisions resulting
between accelerating particles. As the gate-to-source voltage continues to
increase in the positive direction, Fig. 4.33 reveals that the drain current
will increase at a rapid rate for the reasons listed above. The vertical
spacing between the VGS = 0 V and VGS = +1 V curves of Fig. 4.33 is a
clear indication of how much the current has increased for the 1-V change
in VGS. Due to the rapid rise, the user must be aware of the maximum
drain current rating since it could be exceeded with a positive gate
voltage. That is, for the device of Fig. 4.33, the application of a voltage
VGS = +4 V would result in a drain current of 22.2 mA, which could
possibly exceed the maximum rating (current or power) for the device. As
revealed above, the application of a positive gate-to-source voltage has
―enhanced‖ the level of free carriers in the channel compared to that
encountered with VGS = 0 V. For this reason the region of positive gate
voltages on the drain or transfer characteristics is often referred to as the
enhancement region, with the region between cutoff and the saturation
level of IDSS referred to as the depletion region.
It is particularly interesting and helpful that Shockley‘s equation will
continue to be applicable for the depletion-type MOSFET characteristics
in both the depletion and enhancement regions. For both regions, it is
simply necessary that the proper sign be included with VGS in the
equation and the sign be carefully monitored in the mathematical
operations.

Example
Sketch the transfer characteristics for an n-channel depletion-type
MOSFET with IDSS = 10 mA and VP= -4 V.

Solution
At VGS = 0 V, ID = IDSS = 10 mA

VGS = VP = - 4 V, ID = 0 mA

VGS = VP /2 = - 4 v/ 2 = - 2v , ID = IDSS / 4= 10 mA /4 = 2.5 mA

219
and at ID = IDSS /2 , VGS = 0.3 VP = 0.3 (-4 V) = - 1.2 V

all of which appear in Fig. 4.35.

Before plotting the positive region of VGS, keep in mind that ID increases
very rapidly with increasing positive values of VGS. In other words, be
conservative with the choice of values to be substituted into Shockley‘s
equation. In this case, we will try +1 V as follows:

ID = IDSS [ 1 – (VGS / VP )2 ]

= 10 mA [ 1- ( + 1V /-4 V) = 10 mA [ 1 + 0.25] 2 = 10 mA (1.5625)

≡ 15.63 mA

which is sufficiently high to finish the plot.

Fig. 4.35 Transfer characteristics for an n-channel depletion type

MOSFET with IDSS = 10 mA and VP = - 4 V.
220
4.15 p-Channel Depletion-Type MOSFET
The construction of a p-channel depletion-type MOSFET is exactly the
reverse of that appearing in Fig. 4.36. That is, there is now an n-type
substrate and a p-type channel, as shown in Fig. 4.36a. The terminals
remain as identified, but all the voltage polarities and the current
directions are reversed, as shown in the same figure. The drain
characteristics would appear exactly as in Fig. 4.33 but with VDS having
negative values, ID having positive values as indicated (since the defined
direction is

Fig. 4.36 p-Channel depletion-type MOSFET with IDSS = 6 mA and VP =

+ 6 V.

direction is now reversed), and VGS having the opposite polarities as

shown in Fig. 4.36 c. The reversal in VGS will result in a mirror image
(about the ID axis) for the transfer characteristics as shown in Fig. 4.36b.
In other words, the drain current will increase from cutoff at VGS =VP in
the positive VGS region to IDSS and then continue to increase for
increasingly negative values of VGS. Shockley‘s equation is still
applicable and requires simply placing the correct sign for both VGS and
VP in the equation.

4.15.1 Symbols

221
The graphic symbols for an n- and p-channel depletion-type MOSFET are
provided in Fig. 4.37. Note how the symbols chosen try to reflect the
actual construction of the device. The lack of a direct connection (due to
the gate insulation) between the gate and channel is represented by a
space between the gate and the other terminals of the symbol. The
vertical line representing the channel is connected between the drain and
source and is ―supported‖ by the substrate. Two symbols are provided for
each type of channel to reflect the fact that in some cases the substrate is
externally available while in others it is not. For most of the analysis to
follow the substrate and source will be connected and the lower symbols
will be employed.

Fig. 4.37 Graphic symbols for (a) n-channel depletion-type MOSFETs

and (b) p-channel depletion-type MOSFETs.

4.16 Biasing the NMOS Field-Effect Transistor

As stated before, the MOS circuit designer has the flexibility to choose
the circuit topology and W/L ratios of the devices in the circuit, and to a
lesser extent, the voltages applied to the devices.
222
 We have found that the MOSFET has three regions of operation: cutoff,
triode (on state), and saturation. For circuit applications, we want to
establish a well-defined quiescent operating point, or Q-point, for the
MOSFET in a particular region of operation. The Q-point for the
MOSFET is represented by the dc values (ID, VDS) that locate the
operating point on the MOSFET output characteristics. [In reality, we
need the three values (ID, VDS, VGS), but two are enough if we know the
region of operation of the device.]
For binary logic circuits investigated in detail in Part II of this text, the
transistor acts as an ―on-off‖ switch, and the Q-point is set to be in either
the cutoff region (―off‖) or the triode region (―on‖).
To analyze circuits containing MOSFETs, we must first assume a
region of operation, just as we did to analyze diode circuits . We must
know the gate-source voltage VGS to calculate the drain current ID. Then,
once we know ID, we can find VDS from the constraints of Kirchhoff‘s
voltage law. Thus our most frequently used analysis approach will be to
first find VGS and then to use its value to find the value of ID. ID will then
be used to calculate VDS

Menu for Bias Analysis

1. Assume a region of operation (Most often the saturation region)
2. Use circuit analysis to find VGS
3. Use VGS to calculate ID, and ID to determine VDS
4. Check the validity of the operating region assumptions
5. Change assumptions and analyze again if necessary

When making bias calculations for analysis or design, it is useful to

remember that an NMOS enhancement-mode device that is operating
with VDS = VGS will always be in the pinch-off region. The same is true
for an enhancement-mode PMOS transistor with VDS = VSG.

To demonstrate this result, it is easiest to keep the signs straight by

considering an NMOS device with dc bias. For pinch-off, it is required
that:

VDS ≥ VGS − VTN

But if VDS = VGS , this condition becomes

VDS ≥ VDS − VTN or VTN ≥ 0

223
which is always true if VTN is a positive number. VTN > 0 corresponds to
an NMOS enhancement mode device. Thus an enhancement-mode device
operating with VDS = VGS is always in the saturation region! Similar
arguments hold true for enhancement-mode PMOS devices operating
with VSD = VSG.

Example: for Constant Gate-Source Voltage Bias:

A basic bias circuit for the NMOS transistor is shown in Fig. 4.38, in
which dc voltage source
VGG is used to establish a fixed gate-source bias for the MOSFET, source
VDD supplies drain current to the NMOS transistor through resistor RD,
and the value of RD determines VDS. This
circuit is used to introduce a number of concepts related to biasing, but
we shall find that it is not a very useful circuit in practical applications.

Fig. 4.38 Constant gate-voltage bias using a voltage divider

Problem
Find the quiescent operating point Q-point (ID, VDS) for the MOSFET in
the fixed gate bias circuit in Fig. 4.38.

Solution

Known Information and Given Data: Circuit schematic in Fig. 4.38

with VDD = 10 V, VGG = 10 V, R1 = 300 kΩ, R2 = 700 kΩ, RD = 100 kΩ,
VTN = 1 V, Kn = 25 mA/V2,
IG = 0, and IB = 0
Unknowns: ID, VDS, and VGS

224
Approach: We can find the Q-point using the mathematical model for
the NMOS transistor. We must assume a region of operation, determine
the Q-point, and then see if the resulting Q-point is consistent with the
assumed region of operation.
Assumptions: We will assume that the MOSFET is pinched-off:
ID = (Kn/2)(VGS − VTN)2.
Remember, we ignore λ in hand bias calculations. This assumption
simplifies the mathematics because ID is then modeled as being
independent of VDS.
Analysis:
From the drain current expression and given data, we see that if we first
find VGS, then we can use it to find ID. First label the variables in the
circuit including ID, VDS, and VGS.
Then to simplify the analysis, we replace the gate-bias network consisting
of VGG, R1, and R2

Figure 4.39 Simplified MOSFET bias circuit.

with its Th´evenin equivalent circuit as in Fig. 4.39 in which

VEQ = VGG [ R1/ (R1 + R2)] = 3 V and :

REQ = R2 R1/ (R1 + R2) = 210 kΩ

We apply Kirchhoff‘s voltage law (KVL) to the loop containing the gate-
source terminals of the device (referred to here as the input loop):

225
VEQ = IG REQ + VGS (14)

But, we know that IG = 0 for the MOSFET, so that VGS = VEQ = 3 V. We

can now find ID using the transistor parameters from Fig. 4.38:

ID = (Kn/2)(VGS − VTN)2 = (1/2) x 25 x10-6 [µ A/V2](3-1) 2 V2= 50 µA

To determine VDS we write a loop equation including the drain-source

terminals of the device (referred to here as the output loop):

VDD = ID RD + VDS (15)

Again substituting the values from Fig. 4.39,

VDS = 10V − (50 × 10−6 A)(105 Ω) = 5.00V

Check of Results: We have VDS =5 V and VGS − VTN = 2 V. Since VDS

exceeds VGS − VTN,
the transistor is indeed pinched-off and in the saturation region. Thus, the
Q-point is (50.0 µA, 5.00 V) with VGS = 3 V.

Discussion:
Although this circuit introduces a number of concepts related to biasing,
it is not a very useful circuit in practical applications because the Q-point
is very sensitive to variations in the values of the transistor parameters. If
the value of VGS is fixed in the drain current expression, then ID varies in
direct proportion to Kn and depends on the square of changes in VTN.

4.17 Load Line Analysis

The Q-point for the MOSFET circuit in Fig. 4.39 can also be found
graphically with a load-line method very similar to the one used for
analysis of diode circuits before. The graphical approach helps us
visualize the operating point of the device and its location relative to the
boundaries between the cutoff, triode and pinch-off regions of operation.

Problem
Use load line analysis to locate the Q-point for the MOSFET in the fixed
gate bias circuit in Fig. 4.39.

226
Solution
Known Information and Given Data: Circuit schematic in Fig. 4.39
with VDD = 10 V, VEQ = 3V, REQ = 210 kΩ, RD = 100 kΩ, VTN = 1V,
Kn = 25 µA/V2, IG = 0, and IB = 0

Unknowns: Q-point = (ID, VDS)

Approach:
We need to find an equation for the load line, ID = f (VDS), so that it can
be plotted on the output i -v characteristics. The Q-point can then be
located on the output characteristics.
Equation (4.46) represents the load line for this MOSFET circuit and is
repeated here:
VDD = ID RD + VDS

Assumptions:
We have already found VGS = 3V using the techniques in the above
example .

Analysis:

For the values for the circuit in Fig. 4.39, the load line equation becomes

10 = 105 ID + VDS

Just as for the diode circuits before, the load line is constructed by finding
two points on the line: for VDS = 0, ID = 100 µA, and for ID = 0, VDS = 10
V. The resulting line is drawn on the output characteristics of the
MOSFET in Fig. 4.40. The family of NMOS curves intersects the load
line at many different points (actually infinitely many since each possible
gate voltage corresponds to a different curve). The gate-source voltage is
the parameter that determines which of the intersection points is the
actual Q-point. In this circuit, we already found VGS = 3V; the Q-point is
indicated by the circle in the Fig. 4.40. Reading the values from the graph
yields:

VDS = 5 V and ID = 50 µA.

Check of Results:

This is the same Q-point that we found using our mathematical model for
the MOSFET.

227
Discussion:
From the graph, we can immediately see that the Q-point is in the
saturation region of the transistor output characteristics. The Q-point is
fairly well centered in the saturation region of operation, and the drain-
source voltage is 1.5 V greater than that required to saturate the device.
Although we will seldom actually solve bias problems using graphical
techniques, it is very useful to visualize the location of the Q-point in
terms of the load line on the output characteristics as in Fig. 4.40. We can
readily see if the device is operating in the triode or saturation regions as
well as how far the operating point is from the boundaries between the
various regions of operation.

Figure 4.40 Load line for the circuit in Figs. 4.38 and 4.39.

228
 Ch.5
Operational Amplifier
OP-AMP

229
5-1 Introduction
An operational amplifier is a high-gain direct-coupled amplifier that is
normally used in feedback connections. If the amplifier characteristics are
satisfactory, the transfer function of the amplifier with feedback can often
be controlled primarily by the stable and well-known values of passive
feedback elements.
It is a very high gain differential amplifier with high input impedance
and low output impedance. Typical uses of the operational amplifier are
to provide voltage amplitude changes (amplitude and polarity),
oscillators, filter circuits, and many types of instrumentation circuits. An
op-amp contains a number of differential amplifier stages to achieve a
very high voltage gain.
The term operational amplifier evolved from original applications in
analog computation where these circuits were used to perform various
mathematical operations such as summation and integration. Because of
the performance and economic advantages of available units, present
applications extend far beyond the original ones, and modern operational
amplifiers are used as general purpose analog data-processing elements.

5.2. Symbols and Schematic

Fig.5.1 shows the symbol used to represent an operational amplifier.
The two inputs are the inverting (V-) and non-inverting (V+) terminals,

Fig.5.1 Op-amp Symbol

230
and the output is Vout. The supplies are discussed further in the pages
ahead.
The op-amp can be thought of as a ―black box‖ having two inputs and
one output as seen in Fig.5.2

Fig.5.2 Block diagram of an operational amplifier

The op-amp can also be represented as a dependent voltage source

(Vdep) as in Fig.5.3, having an output impedance (Zoutput) and input
impedance (Zinput). The input impedance is so high that no current can
flow between the input terminals, but the output impedance is very low.
The supply voltages provide the power necessary for the high gain and
amplification and are viewed here as the dependent voltage source.

Fig.5.3. Equivalent view of an op-amp

231
The circuitry that makes up an op-amp consists of transistors, resistors,
diodes, and a couple capacitors. In general, these components are
combined to achieve within the op-amp two stages of differential
amplifiers and a common-collector amplifier.
In an effort to simplify the operational amplifier, one must not forget that
the internal circuitry of an op-amp is more than just a ―black box‖. All
operational amplifiers are integrated circuits (ICs), and Fig.5. 4 illustrates
the components that work together to achieve what we know to be an op-
amp.

Fig.5.4. Internal circuitry of an op-amp

5.3 Various input and output Forms:

232
5.3.1 Single-Ended Input
Single-ended input operation results when the input signal is connected to
one input with the other input connected to ground. Fig.5.2 shows the
signals connected for this operation. In Fig. 5.5a, the input is applied to
the plus input (with minus input at ground), which results in an output
having the same polarity as the applied input signal. Fig.5.2b shows an
input signal applied to the minus input, the output then being opposite in
phase to the applied signal.

Fig.5.5 Single-ended operation.

233
5.3.2 Double-Ended (Differential) Input
In addition to using only one input, it is possible to apply signals at each
input—this being a double-ended operation. Fig.5.6a shows an input, Vd,
applied between the two input terminals (recall that neither input is at
ground), with the resulting amplified output in phase with that applied
between the plus and minus inputs. Fig.5.3b shows the same action
resulting when two separate signals are applied to the inputs, the
difference signal being Vi1 - Vi2.

Fig.5.6 Double-ended (differential) operation.

234
5.3.3 Double-Ended Output

While the operation discussed so far had a single output, the op-amp can
also be operated with opposite outputs, as shown in Fig. 5.7. An input
applied to either input will result in outputs from both output terminals,
these outputs always being opposite in polarity. Fig.5.8 shows a single-
ended input with a double-ended output. As shown, the signal applied to
the plus input results in two amplified outputs of opposite polarity.
Fig.5.9 shows the same operation with a single output measured
between output terminals (not with respect to ground). This difference
output signal is Vo1 - Vo2. The difference output is also referred to as a
floating signal since neither output terminal is the ground (reference)
terminal. Notice that the difference output is twice as large as either Vo1
or Vo2 since they are of opposite polarity and subtracting them results in
twice their amplitude [i.e., 10 V - (-10 V) = 20 V]. Fig.5.10 shows a
differential input, differential output operation. The input is applied
between the two input terminals and the output taken from between the
two output terminals. This is fully differential operation.

Fig.5.7 Double-ended output.

235
Fig.5.8 Double-ended output with single-ended input.

Fig.5.9 Double-ended output.

236
5.4. Kirchhoff’s Current Law applied to Op-amps

An operational amplifier circuit can be analyzed with the use of a well-

accepted observation known as Kirchhoff‘s Current Law (KCL). KCL
simply states that the currents entering a node are equal in magnitude to
the currents leaving that same node. A node is any junction wherein two
or more two-terminal components meet. Consider Fig.5.10 for
clarification.

Fig.5.10 KCL defined

In this case,: 20mA + 40mA = 60mA.

The principle of KCL is the heart of node voltage analysis. The purpose
of node voltage analysis is to find the voltage value at a certain node(s).
This is done by representing the currents entering and leaving the node by
their Ohm‘s law equivalent (i.e. I=V/R). KCL and node voltage analysis
apply to all electrical circuits including operational amplifiers. As an
example of op-amp electrical circuits ,Fig.5.11 shows a common non-
inverting op-amp circuit that will be repeated later.

237
 Fig.5.11. KCL and op-amps

The number (1) indicates the main node of significance. At this node, a
current is assumed to leave the inverting terminal (V-) of the op-amp and
go through Ri to ground. Another current is assumed to feed from the
output back to the inverting input through resistor Rf. The third current (i-
) feeds into the inverting terminal, but i- always equals

zero. In fact, there are two important assumptions that concern op-amps
when it comes to KCL circuit analysis:

Two very important assumptions:

1) i− = i+ = 0

2) V + = V –

In Fig.5.12, i- equals zero, so If equals Ii. The voltage drops are across
the resistor, so the voltage value of the side to which the current is
flowing is subtracted from the side that the current is coming from (or the
side of higher potential). See the equations below:

238
 If = Ii
(Vout – V-)/ Rf = [ (V-) – Gnd ] / Ri

The voltage source is connected directly to V+, so V+ = Vs = V- , and

Gnd always equals zero.

(Vout – VS)/ Rf = VS / Ri
Vout – VS = VS Rf / Ri
(Vout / VS ) – (VS / VS ) = Rf / Ri
(Vout / VS ) = 1 + ( Rf / Ri)

Simplifying further, we have determined the output voltage (Vout) to

input voltage source (Vs) relationship. Op-amps can be accurately
described by simply recognizing that i+ = i- = 0, and V+ = V- , and then
correctly applying KCL.

5.5 . Input/output Impedance

Two positive aspects of operational amplifiers are that they have a very
high input impedance and a very low output impedance. A high input
impedance is a good thing because the surrounding circuit in which the
op-amp is a part sees the op-amp as having a large resistance, so nearly
all of the voltage will be dropped across it, instead of, for example, it
being dropped across the internal resistance of a preceding source. In
relation, a low output impedance is like having a low internal resistance,
so all of the output voltage leaving the op-amp will be dropped across the
subsequent circuitry or load and not very much of it will be lost across
the internal resistance of the op-amp. A reasonable output impedance
value could be between 0-100 Ω, while an input impedance could be
around 1 MΩ.

239
5.6 Common-Mode Operation and Common-Mode
Rejection

When the same input signals are applied to both inputs, common-mode
operation results, as shown in Fig. 5.12. Ideally, the two inputs are
equally amplified, and since they result in opposite polarity signals at the
output, these signals cancel, resulting in 0-V output. Practically, a small
output signal will result.

Fig. 5. 12 Common-mode operation.

5.6.1 Common-Mode Rejection

A significant feature of a differential connection is that the signals which
are opposite at the inputs are highly amplified, while those which are
common to the two inputs are only slightly amplified—the overall
operation being to amplify the difference signal while rejecting the
common signal at the two inputs. Since noise (any unwanted input signal)
is generally common to both inputs, the differential connection tends to
provide attenuation of this unwanted input while providing an amplified
output of the difference signal applied to the inputs. This operating
feature, referred to as common-mode rejection, is discussed more fully in
the next section.

240
5.7 Differential and Common Mode Operation
One of the more important features of a differential circuit connection, as
provided in an op-amp, is the circuit‘s ability to greatly amplify signals
that are opposite at the two inputs, while only slightly amplifying signals
that are common to both inputs. An op-amp provides an output
component that is due to the amplification of the difference of the signals
applied to the plus and minus inputs and a component due to the signals
common to both inputs. Since amplification of the opposite input signals
is much greater than that of the common input signals, the circuit
provides a common mode rejection as described by a numerical value
called the common-mode rejection ratio (CMRR).

5.7.1 Differential Inputs

When separate inputs are applied to the op-amp, the resulting difference
signal is the difference between the two inputs.

Vd = Vi1 - Vi2 (5.1)

5.7.2 Common Inputs

When both input signals are the same, a common signal element due to
the two inputs can be defined as the average of the sum of the two
signals.

Vc = (1/2)(Vi1 + Vi2) (5.2)

5.7.3 Output Voltage

Since any signals applied to an op-amp in general have both in-phase and
out-of phase components, the resulting output can be expressed as

Vo = AdVd + AcVc (5.3)

Where Vd = difference voltage given by Eq. (5.1)
Vc = common voltage given by Eq. (5.2)
Ad = differential gain of the amplifier
Ac = common-mode gain of the amplifier

241
5.7.4 Opposite Polarity Inputs

If opposite polarity inputs applied to an op-amp are ideally opposite

signals, Vi1 = -Vi2 = Vs , the resulting difference voltage is:

Eq. (5.1): Vd = Vi1 - Vi2 = Vs - (-Vs) = 2Vs

while the resulting common voltage is:

Eq. (5.2): Vc = (1/2)(Vi1 + Vi2) = (1/2)[ Vs + (-Vs )] = 0

so that the resulting output voltage is :

Eq. (5.3): Vo = AdVd + AcVc = Ad (2Vs) + 0 = 2 Ad Vs

This shows that when the inputs are an ideal opposite signal (no common
element), the output is the differential gain times twice the input signal
applied to one of the inputs.

5.7.5 Same Polarity Inputs

If the same polarity inputs are applied to an op-amp, Vi1 = Vi2= Vs, the
resulting difference voltage is:

Eq. (5.1): Vd = Vi1 - Vi2 = Vs - Vs = 0

while the resulting common voltage is:

Eq. (5.2): Vc = (1/2)(Vi1 + Vi2) = (1/2)( Vs + Vs) = Vs

so that the resulting output voltage is:

Eq. (5.3): Vo = AdVd + AcVc = Ad (0) + Ac Vs = Ac Vs

This shows that when the inputs are ideal in-phase signals (no difference
signal), the output is the common-mode gain times the input signal, Vs,
which shows that only common-mode operation occurs.

5.7.6 Common-Mode Rejection

242
The solutions above provide the relationships that can be used to measure
Ad and Ac in op-amp circuits.

1. To measure Ad: Set Vi1 = - Vi2 = Vs = 0.5 V, so that

Eq. (5.1): Vd = Vi1 - Vi2= (0.5 V – (-0.5 V) = 1 V

and Eq. (5.2): Vc = (1/2)(Vi1 + Vi2) = (1/2)( 0.5 V + ( -0.5 V ) = 0V

Under these conditions the output voltage is:

Eq. (5.3): Vo = AdVd + AcVc = Ad( 1 V ) + Ac( 0) = Ad

Thus, setting the input voltages Vi1 = - Vi2 = 0.5 V results in an output
voltage numerically equal to the value of Ad.

2. To measure Ac: Set Vi1 = Vi2 = Vs = 1 V , so that

Eq. (5.1): Vd = (Vi1 - Vi2) = (1 V - 1 V) = 0 V

and Eq. (5.2): Vc = (1/2)(Vi1 + Vi2) = (1/2)( 1 V + 1 V) = 1 V

Under these conditions the output voltage is :

Eq. (5.3): Vo = AdVd + AcVc = Ad( 0 V) + Ac( 1 V) = Ac

Thus, setting the input voltages Vi1 = Vi2 = 1 V results in an output

voltage numerically equal to the value of Ac .

5.7.7.Common-Mode Rejection Ratio

Having obtained Ad and Ac (as in the measurement procedure discussed
above), we can now calculate a value for the common-mode rejection
ratio (CMRR), which is defined by the following equation:

CMRR = Ad / Ac (4)

The value of CMRR can also be expressed in logarithmic terms as

243
CMRR (log) = 20 log10 (Ad / Ac ) (dB) (5)

It should be clear that the desired operation will have Ad very large with
Ac very small. That is, the signal components of opposite polarity will
appear greatly amplified at the output, whereas the signal components
that are in phase will mostly cancel out so that the common-mode gain,
Ac, is very small. Ideally, the value of the CMRR is infinite. Practically,
the larger the value of CMRR, the better the circuit operation.

We can express the output voltage in terms of the value of CMRR as

follows:
Eq. (5.3): Vo = AdVd + AcVc = AdVd [ 1 + (AcVc / AdVd)]

Using Eq. (5.4), we can write the above as :

Vo = AdVd [ 1 + ( 1/CMRR)(Vc / Vd)] (6)

Even when both Vd and Vc components of signal are present, Eq. (5.6)
shows that for large values of CMRR, the output voltage will be due
mostly to the difference signal, with the common-mode component
greatly reduced or rejected. Some practical examples should help clarify
this idea.

Example

Calculate the CMRR for the circuit measurements shown in Fig. 5.13.

244
Fig. 5.13 Differential and common-mode operation: (a) differential-
mode; (b) common-mode.
Solution
From the measurement shown in Fig. 5.13a, using the procedure in step 1
above, we obtain:

Ad = Vo /Vd = 8 V / 1 mV = 8000

The measurement shown in Fig. 5.13b, using the procedure in step 2

above, gives us :

Ac=Vo / Vc = 12 mV / 1 mV = 12

Using Eq. (5.4), the value of CMRR is :

CMRR = Ad / Ac = 8000/12 = 666.7

245
which can also be expressed as:

CMRR (log) = 20 log10 (Ad / Ac ) = 20 log10 666.7 = 56.48 dB.

5.8 Operational Amplifier (Op-Amp) Basics

An operational amplifier is a very high gain amplifier having very high
input impedance (typically a few megohms) and low output impedance
(less than 100 Ω). The basic circuit is made using a difference amplifier
having two inputs (plus and minus) and at least one output. Fig.5.14
shows a basic op-amp unit. As discussed earlier, the plus (+) input
produces an output that is in phase with the signal applied, while an

Fig.5.14. Basic op-amp.

input to the minus (-) input results in an opposite polarity output. The ac
equivalent circuit of the op-amp is shown in Fig. 5.15a. As shown, the
input signal applied between input terminals sees an input impedance, Ri,
typically very high. The output voltage is shown to be the amplifier gain
times the input signal taken through an output impedance, Ro, which is
typically very low. An ideal op-amp circuit, as shown in Fig. 5.15b,
would have infinite input impedance, zero output impedance, and an
infinite voltage gain (Fig.5.16 illustrates this).

246
Fig. 5.15 Ac equivalent of op-amp circuit: (a) practical; (b) ideal.

Fig.5.16

5.8.1 Basic Op-Amp

The basic circuit connection using an op-amp is shown in Fig. 5.17. The
circuit shown provides operation as a constant-gain multiplier. An input
signal, V1, is applied through resistor R1 to the minus input. The output is
then connected back to the same minus input through resistor Rf. The plus
input is connected to ground. Since the signal V1 is essentially applied to

247
the minus input, the resulting output is opposite in phase to the input
signal.

Fig. 5.17 Basic op-amp connection.

VO/ V1 = - Rf / R1 (7)

The result, in Eq. (7), shows that the ratio of overall output to input
voltage is dependent only on the values of resistors R1 and Rf —provided
that Av is very large.

5.8.2 Unity Gain

If : Rf = R1 , the gain is:

voltage gain = - Rf / R1 = - 1

so that the circuit provides a unity voltage gain with 180° phase
inversion. If Rf is exactly R1 , the voltage gain is exactly 1.

5.8.3 Constant Magnitude Gain

248
If Rf is some multiple of R1 , the overall amplifier gain is a constant. For
example, if :Rf = 10 R1, then:

voltage gain = - Rf / R1 = - 10

and the circuit provides a voltage gain of exactly 10 along with an 180°
phase inversion from the input signal. If we select precise resistor values
for Rf and R1, we can obtain a wide range of gains, the gain being as
accurate as the resistors used and is only slightly affected by temperature
and other circuit factors.

5.8.4 Virtual Ground

The output voltage is limited by the supply voltage of, typically, a few
volts. As stated before, voltage gains are very high. If, for example,
Vo= -10 V and Av = 20,000, the input voltage would then be:

Vi = - Vo/ AV = 10 V / 20,000 = 0.5 mV

If the circuit has an overall gain (Vo /V1) of, say, 1, the value of V1
would then be 10 V. Compared to all other input and output voltages, the
value of Vi is then small and may be considered 0 V.
Note that although Vi = 0 V, it is not exactly 0 V. (The output voltage is
a few volts due to the very small input Vi times a very large gain Av.)
The fact that Vi = 0 V leads to the concept that at the amplifier input there
exists a virtual short circuit or virtual ground.
The concept of a virtual short implies that although the voltage is
nearly 0 V, there is no current through the amplifier input to ground. Fig.
5.18 depicts the virtual ground concept. The heavy line is used to indicate
that we may consider that a short exists with Vi = 0 V but that this is a
virtual short so that no current goes through the short to ground. Current
goes only through resistors R1 and Rf as shown.
Using the virtual ground concept, we can write equations for the current
I as follows:

I = V1/ R1 = - VO/ Rf

which can be solved for VO/ V1:

VO/ V1 = - Rf / R1

249
 Fig.5.18 Virtual ground in an op-amp.

The virtual ground concept, which depends on Av being very large,

allowed a simple solution to determine the overall voltage gain. It should
be understood that although the circuit of Fig.5.18 is not physically
correct, it does allow an easy means for determining the overall voltage
gain.

5.9 Practical OP-AMP Circuits

The op-amp can be connected in a large number of circuits to provide
various operating characteristics. In this section, we cover a few of the
most common of these circuit connections.

5.9.1 Inverting Amplifier

The most widely used constant-gain amplifier circuit is the inverting
amplifier, as shown in Fig. 5.19. The output is obtained by multiplying
the input by a fixed or constant gain, set by the input resistor (R1) and
feedback resistor (Rf)—this output also being inverted from the input.
Using Eq. (7) we can write:

VO = - V1 Rf / R1

250
 Fig. 5.19 Inverting constant-gain multiplier.

Fig.5.20 illustrates the steps of analysis of the inverting op-amp circuit

where the circled numbers indicate the order of the analysis process.

Fig.5.20

Example
251
If the circuit of Fig. 5.19 has R1 = 100 kΩ and Rf = 500 kΩ, what output
voltage results for an input of V1 = 2 V?

Solution

VO = - V1 Rf / R1

= - (500 kΩ / 100 kΩ ) (2 V )

= - 10 V.

5.9.2 Noninverting Amplifier

The connection of Fig. 5.21a shows an op-amp circuit that works as a

noninverting amplifier or constant-gain multiplier. It should be noted that
the inverting amplifier connection is more widely used because it has
better frequency stability. To determine the voltage gain of the circuit, we
can use the equivalent representation shown in Fig. 5.21b. Note that the
voltage across R1 is V1 since Vi = 0 V. This must be equal to the output
voltage, through a voltage divider of R1 and Rf , so that :

V1 = VO [R1/( R1 + Rf )]

which results in:

VO /V1 = ( R1 + Rf ) /R1 = 1 + Rf /R1 (8)

Fig. 5.22 illustrates the steps of analysis of the Noninverting op-amp

circuit where the circled numbers indicate the order of the analysis
process.

252
Fig. 5.21 Noninverting constant-gain multiplier.

Fig. 5.22
253
Example

Calculate the output voltage of a noninverting amplifier (as in Fig. 5.21)

for values of V1 = 2 V, Rf = 500 kΩ, and R1= 100 kΩ.

Solution

VO /V1 = ( R1 + Rf ) /R1

= 1 + Rf /R1

VO = V1 [1 + ( Rf /R1 )]

= (2 V ) [ 1 + (500 kΩ /100 kΩ)]

= 6(2 V )

= + 12 V

5.9.3 Summing Amplifier

Probably the most used of the op-amp circuits is the summing amplifier
circuit shown in Fig. 5.23a. The circuit shows a three-input summing
amplifier circuit, which provides a means of algebraically summing
(adding) three voltages, each multiplied by a constant-gain factor. Using
the equivalent representation shown in Fig. 5.23b. Generally , the output
voltage can be expressed in terms of the inputs as we proceed :

Generally :

i= v1/R1 + v2/R2 +……….+ vn/Rn

The output voltage :

vo = - Rf i = - [v1(Rf / R1 ) + v2(Rf / R1 ) ) + ………+ vn(Rf / Rn ) ]

:‫ فإن العالقت األخيرة لجهد الخرج تصبح كما يأتي‬R1 = R2=……= Rn ‫إذا كان‬

254
vo = - (Rf / R1) ( (v1 + v2 + ………+ vn )

For the circuit shown in Fig. 5.23:

VO = - [(V1 Rf / R1) + (V2 Rf / R2) +(V3 Rf / R3)]

In other words, each input adds a voltage to the output multiplied by its
separate constant-gain multiplier. If more inputs are used, they each add
an additional component to the output.

Fig. 5.23

255
Fig. 5.24 illustrates the steps of analysis of the Noninverting op-amp
circuit where the circled numbers indicate the order of the analysis
process.

Fig. 5.24

Example
Calculate the output voltage of an op-amp summing amplifier for the
circuit of summing op-amp shown in Fig.5.25 if :

R1 = R2 = R3 = R4 = 33 KΩ

256
Solution:

Fig.5.25

R1 = R2 = R3 = R4

VO = - (V1 + V2 + V3)

= - ( 0.5 + 1 + 0.3 ) = - 1.8 V

5.9.4 Integrator
So far, the input and feedback components have been resistors. If the
feedback component used is a capacitor, as shown in Fig. 5.26a, the
resulting connection is called an integrator. The virtual-ground
equivalent circuit (Fig.5.26b) shows that an expression for the voltage
257
between input and output can be derived in terms of the current I, from
input to output. Recall that virtual ground means that we can consider
the voltage at the junction of R and XC to be ground (since Vi = 0 V) but
that no current goes into ground at that point. The capacitive impedance
can be expressed as:

XC= 1/ jɷ C = 1 /sC

Fig. 5.26 Integrator.

258
Where s = jɷ is in the Laplace notation(Laplace notation allows
expressing differential or integral operations which are part of calculus in
algebraic form using the operator s).. Solving for Vo / V1 yields:

I = V1 /R = - Vo/ XC = - Vo/(1/sC) = - sC Vo

Vo/ V1 = -1/sCR (9)

The expression above can be rewritten in the time domain as:

Vo(t) = -(1/RC) ʃ V1 (t) dt (10)

Equation (10) shows that the output is the integral of the input, with an
inversion and scale multiplier of 1/RC. The ability to integrate a given
signal provides the analog computer with the ability to solve differential
equations and therefore provides the ability to electrically solve analogs
of physical system operation.
The integration operation is one of summation, summing the area under
a waveform or curve over a period of time. If a fixed voltage is applied as
input to an integrator circuit, Eq. (10) shows that the output voltage grows
over a period of time, providing a ramp voltage. Equation (10) can thus
be understood to show that the output voltage ramp (for a fixed input
voltage) is opposite in polarity to the input voltage and is multiplied by
the factor 1/RC. While the circuit of Fig. 5.26 can operate on many
varied types of input signals, the following examples will use only a fixed
input voltage, resulting in a ramp output voltage.
As an example, consider an input voltage, V1= 1 V, to the integrator
circuit of Fig. 5.27 a. The scale factor of 1/RC is:

-1/RC = 1 / (1 MΩ )(1 µ F) = -1

so that the output is a negative ramp voltage as shown in Fig. 5.27b. If the
scale factor is changed by making R = 100 kΩ, for example, then:

-1/RC = 1 / (100 kΩ )(1 µ F) = -10

and the output is then a steeper ramp voltage, as shown in Fig. 5.27c.

259
Fig. 5.27 Operation of integrator with step input.

260
More than one input may be applied to an integrator, as shown in Fig.
5.28, with the resulting operation given by:

Vo(t) = -[(1/R1C) ʃ V1 (t) dt +(1/R2C) ʃ V2 (t) dt +(1/R3C) ʃ V3 (t) dt]

(11)

An example of a summing integrator as used in an analog computer is

given in Fig. 5.28. The actual circuit is shown with input resistors and
feedback capacitor, whereas the analog-computer representation indicates
only the scale factor for each input.

Fig. 5.28 (a) Summing-integrator circuit; (b) component values; (c)

analog computer ,integrator-circuit representation.
261
5.9.5 Differentiator
A differentiator circuit is shown in Fig. 5.29. While not as useful as the
circuit forms covered above, the differentiator does provide a useful
operation, the resulting relation for the circuit being:

Vo(t) = - RC [dV1(t)/dt] (12)

where the scale factor is -RC.

Fig. 5.29 Differentiator circuit.

5.10 OP-AMP Specifications—DC OFFSET Parameters

We should become familiar with some of the parameters used to define

the operation of the OP-AMP. These specifications include both dc and
transient or frequency operating features, as covered next.

5.10.1 Offset Currents and Voltages

262
While the op-amp output should be 0 V when the input is 0 V, in actual
operation there is some offset voltage at the output. For example, if one
connected 0 V to both op-amp inputs and then measured 26 mV(dc) at the
output, this would represent 26 mV of unwanted voltage generated by the
circuit and not by the input signal. Since the user may connect the
amplifier circuit for various gain and polarity operations, however, the
manufacturer specifies an input offset voltage for the op-amp. The output
offset voltage is then determined by the input offset voltage and the gain
of the amplifier, as connected by the user.
The output offset voltage can be shown to be affected by two separate
circuit conditions. These are: (1) an input offset voltage, VIO, and (2) an
offset current due to the difference in currents resulting at the plus (+) and
minus (-) inputs.

5.10.2 Input OFFSET Voltage, VIO

The manufacturer‘s specification sheet provides a value of VIO, for the
op-amp. To determine the effect of this input voltage on the output,
consider the connection shown in Fig. 5.30. Using Vo = AVi, we can
write:

Vo = AVi = A [VIO - Vo R1 /(R1 + Rf)]

Solving for Vo, we get :

Vo = AVi = VIO A/ { 1+ A[ R1 /(R1 + Rf)]}

≈ VIO A/ { A[ R1 /(R1 + Rf)]}

from which we can write:

Vo(offset) = VIO (R1 + Rf)/ R1 (13)

Equation (13) shows how the output offset voltage results from a
specified input offset voltage for a typical amplifier connection of the op-
amp.

263
Fig. 5.30 Operation showing effect of input offset voltage, VIO.

Example
Calculate the output offset voltage of the circuit in Fig. 5.31. The op-amp
spec lists VIO= 1.2 mV.

Solution:

Vo(offset) = VIO (R1 + Rf)/ R1

= (1.2 mV) [ (2kΩ + 150kΩ)/2kΩ]

= 91.2 mV

264
 Fig. 5.31 Op-amp example connection

5.10.3 Output Offset Voltage Due To Input Offset Current, IIO

An output offset voltage will also result due to any difference in dc bias
currents at both inputs. Since the two input transistors are never exactly
matched, each will operate at a slightly different current. For a typical op-
amp connection, such as that shown in Fig. 5.32, an output offset voltage
can be determined as follows. Replacing the bias currents through the
input resistors by the voltage drop that each develops, as shown in Fig.
5.33, we can determine the expression for the resulting output voltage.
Using superposition, the output voltage due to input bias current I+IB,
denoted by V+o, is:

V+o = I+IB RC [ 1 + (Rf/ R1)]

while the output voltage due to only I-IB denoted by V-o , is:

V-o = I-IB R1 (- Rf/ R1)

265
 Fig. 5.32 Op-amp connection showing input bias currents.

Fig. 5.33 Redrawn circuit of Fig. 5.32

for a total output offset voltage of

Vo(offset due to I+IB and I-IB) = I+IB RC [ 1 + (Rf/ R1)] - I-IB R1(Rf/ R1)
( 14 )
266
Since the main consideration is the difference between the input bias
currents rather than each value, we define the offset current IIO by:

IIO = I+IB - I-IB

Since the compensating resistance RC is usually approximately equal to

the value of R1, using RC = R1 in Eq. (14) we can write

Vo(offset ) = I+IB ( R1 + Rf ) - I-IB Rf

= I+IB Rf - I-IB Rf

= Rf (I+IB - I-IB )

resulting in:

Vo(offset due IIO) = IIO Rf (15)

Example
Calculate the offset voltage for the circuit of Fig. 5.31 for op-amp
specification listing
IIO = 100 nA.

Solution

Vo(offset due IIO) = IIO Rf

= (100 nA)(150 kΩ) = 15 mV

5.10.4 Total OFFSET Due To VIO and IIO

Since the op-amp output may have an output offset voltage due to both
factors covered above, the total output offset voltage can be expressed as:

|Vo(total offset)| =|Vo(offset due to VIO)| + |Vo(offset due to IIO)|

(16)

267
The absolute magnitude is used to accommodate the fact that the offset
polarity may be either positive or negative.

Example
Calculate the total offset voltage for the circuit of Fig. 5.34 for an op-amp
with specified values of input offset voltage, VIO = 4 mV and input offset
current IIO =150 nA.

Fig. 5.34 Op-amp circuit

Solution

The offset due to VIO is:

Vo(offset) = VIO (R1 + Rf)/ R1

= ( 4 mV) [( 5k Ω + 500 k Ω )/(5k Ω)]

= 404 mV
Vo(offset due IIO) = IIO Rf

= (150 nA)(500 kΩ) = 75 mV

resulting in a total offset

268
|Vo(total offset)| =|Vo(offset due to VIO)| + |Vo(offset due to IIO)| =

= 404 mV + 75 mV = 479 mV

269
 Ch. 6
Digital Electronics

270
6.1 Analogue Versus Digital
There are two basic ways of representing the numerical values of the
various physical quantities with which we constantly deal in our day-to-
day lives. One of the ways, referred to as analogue, is to express the
numerical value of the quantity as a continuous range of values between
the two expected extreme values. For example, the temperature of an
oven settable anywhere from 0 to 100 °C may be measured to be 65 °C or
64.96 °C or 64.958 °C or even 64.9579 °C and so on, depending upon the
accuracy of the measuring instrument. Similarly, voltage across a certain
component in an electronic circuit may be measured as 6.5 V or 6.49 V or
6.487 V or 6.4869 V. The underlying concept in this mode of
representation is that variation in the numerical value of the quantity is
continuous and could have any of the infinite theoretically possible values
between the two extremes.
The other possible way, referred to as digital, represents the numerical
value of the quantity in steps of discrete values. The numerical values are
mostly represented using binary numbers. For example, the temperature
of the oven may be represented in steps of 1 °C as 64 °C, 65 °C, 66 °C
and so on.
To summarize, while an analogue representation gives a continuous
output, a digital representation produces a discrete output. Analogue
systems contain devices that process or work on various physical
quantities represented in analogue form. Digital systems contain devices
that process the physical quantities represented in digital form.
Digital techniques and systems have the advantages of being relatively
much easier to design and having higher accuracy, programmability,
noise immunity, easier storage of data and ease of fabrication in
integrated circuit form, leading to availability of more complex functions
in a smaller size. The real world, however, is analogue. Most physical
quantities – position, velocity, acceleration, force, pressure, temperature
and flow rate, for example – are analogue in nature. That is why analogue
variables representing these quantities need to be digitized or discretized
at the input if we want to benefit from the features and facilities that come
with the use of digital techniques. In a typical system dealing with
analogue inputs and outputs, analogue variables are digitized at the input
with the help of an analogue-to-digital converter block and reconverted
back to analogue form at the output using a digital-to-analogue converter
block. Analogue-to-digital and digital-to-analogue converter circuits are
discussed at length in the latter part of the book. In the following sections
we will discuss various number systems commonly used for digital
representation of data.

271
6.2 Introduction to Number Systems

We will begin our discussion on various number systems by briefly

describing the parameters that are common to all number systems. An
understanding of these parameters and their relevance to number systems
is fundamental to the understanding of how various systems operate.
Different characteristics that define a number system include the number
of independent digits used in the number system, the place values of the
different digits constituting the number and the maximum numbers that
can be written with the given number of digits. Among the three
characteristic parameters, the most fundamental is the number of
independent digits or symbols used in the number system. It is known as
the radix or base of the number system. The decimal number system with
which we are all so familiar can be said to have a radix of 10 as it has 10
independent digits, i.e. 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9.
Similarly, the binary number system with only two independent digits,
0 and 1, is a radix-2 number system. The octal and hexadecimal number
systems have a radix (or base) of 8 and 16 respectively. We will see in the
following sections that the radix of the number system also determines
the other two characteristics. The place values of different digits in the
integer part of the number are given by r0, r1, r2, r3 and so on, starting with
the digit adjacent to the radix point. For the fractional part, these are r−1,
r−2, r−3 and so on, again starting with the digit next to the radix point.
Here, r is the radix of the number system. Also, maximum numbers that
can be written with n digits in a given number system are equal to rn.

6.3 Decimal Number System

The decimal number system is a radix-10 number system and therefore

has 10 different digits or symbols. These are 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9.
All higher numbers after ‗9‘ are represented in terms of these 10 digits
only. The process of writing higher-order numbers after ‗9‘ consists in
writing the second digit (i.e. ‗1‘) first, followed by the other digits, one by
one, to obtain the next 10 numbers from ‗10‘ to ‗19‘. The next 10
numbers from ‗20‘ to ‗29‘ are obtained by writing the third digit (i.e.
‗2‘) first, followed by digits ‗0‘ to ‗9‘, one by one. The process continues
until we have exhausted all possible two-digit combinations and reached
‗99‘. Then we begin with three-digit combinations. The first three-digit

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number consists of the lowest two-digit number followed by ‗0‘ (i.e.
100), and the process goes on endlessly.
The place values of different digits in a mixed decimal number, starting
from the decimal point, are 100, 101, 102 and so on (for the integer part)
and 10−1, 10−2, 10−3 and so on (for the fractional part).
The value or magnitude of a given decimal number can be expressed as
the sum of the various digits multiplied by their place values or weights.
As an illustration, in the case of the decimal number 3586.265, the integer
part (i.e. 3586) can be expressed as:

3586 = 6×100 +8×101+5×102 +3×103 = 6+80+500+3000 = 3586

and the fractional part can be expressed as:

265 = 2×10−1+6×10−2 +5×10−3 = 0.2+0.06+0.005 = 0.265

We have seen that the place values are a function of the radix of the
concerned number system and the position of the digits. We will also
discover in subsequent sections that the concept of each digit having a
place value depending upon the position of the digit and the radix of the
number system is equally valid for the other more relevant number
systems.

6.4 Binary Number System

The binary number system is a radix-2 number system with ‗0‘ and ‗1‘ as
the two independent digits. All larger binary numbers are represented in
terms of ‗0‘ and ‗1‘. The procedure for writing higher order binary
numbers after ‗1‘ is similar to the one explained in the case of the decimal
number system.
For example, the first 16 numbers in the binary number system would be
:
0, 1, 10, 11, 100, 101, 110, 111, 1000, 1001, 1010, 1011, 1100, 1101,
1110 and 1111.
The next number after 1111 is 10000, which is the lowest binary number
with five digits. This also proves the point made earlier that a maximum
of only 16 (= 24) numbers could be written with four digits. Starting from
the binary point, the place values of different digits in a mixed binary
number are 20, 21, 22 and so on (for the integer part) and 2−1, 2−2, 2−3 and
so on (for the fractional part).

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Bit is an abbreviation of the term ‗binary digit‘ and is the smallest unit of
information. It is either ‗0‘ or ‗1‘. A byte is a string of eight bits. The byte
is the basic unit of data operated upon as a single unit in computers. A
computer word is again a string of bits whose size, called the ‗word
length‘ or ‗word size‘, is fixed for a specified computer, although it may
vary from computer to computer. The word length may equal one byte,
two bytes, four bytes or be even larger. Fig.6.1 displays the binary
umbers positions and its weights and decimal equivalent.

Fig.6.1

Example 6.1
Consider an arbitrary number system with the independent digits as 0, 1
and X. What is the radix of this number system? List the first 10 numbers
in this number system.
Solution
• The radix of the proposed number system is 3.
• The first 10 numbers in this number system would be 0, 1, X, 10, 11,
1X, X0, X1, XX and 100.

6.4.1 Advantages

Logic operations are the backbone of any digital computer, although

solving a problem on computer could involve an arithmetic operation too.

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The introduction of the mathematics of logic by George Boole laid the
foundation for the modern digital computer. He reduced the mathematics
of logic to a binary notation of ‗0‘ and ‗1‘. As the mathematics of logic
was well established and had proved itself to be quite useful in solving
all kinds of logical problem, and also as the mathematics of logic (also
known as Boolean algebra) had been reduced to a binary notation, the
binary number system had a clear edge over other number systems for use
in computer systems.
Yet another significant advantage of this number system was that all
kinds of data could be conveniently represented in terms of 0s and 1s.
Also, basic electronic devices used for hardware implementation could be
conveniently and efficiently operated in two distinctly different modes.
For example, a bipolar transistor could be operated either in cut-off or in
saturation very efficiently.
Lastly, the circuits required for performing arithmetic operations such as
addition, subtraction, multiplication, division, etc., become a simple affair
when the data involved are represented in the form of 0s and 1s.

6.5 Octal Number System

The octal number system has a radix of 8 and therefore has eight distinct
digits. All higher-order numbers are expressed as a combination of these
on the same pattern as the one followed in the case of the binary and
decimal number systems described in Sections 1.3 and 1.4. The
independent digits are 0, 1, 2, 3, 4, 5, 6 and 7. The next 10 numbers that
follow ‗7‘, for example, would be 10, 11, 12, 13, 14, 15, 16, 17, 20 and
21. In fact, if we omit all the numbers containing the digits 8 or 9, or
both, from the decimal number system, we end up with an octal number
system. The place values for the different digits in the octal number
system are 80, 81, 82 and so on (for the integer part) and 8−1, 8−2, 8−3 and
so on (for the fractional part).

6.6 Hexadecimal Number System

The hexadecimal number system is a radix-16 number system and its 16

basic digits are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E and F. The place
values or weights of different digits in a mixed hexadecimal number are
160, 161, 162 and so on (for the integer part) and 16−1, 16−2, 16−3 and so on

275
(for the fractional part). The decimal equivalent of A, B, C, D, E and F
are 10, 11, 12, 13, 14 and 15 respectively, for obvious reasons.
The hexadecimal number system provides a condensed way of
representing large binary numbers stored and processed inside the
computer. One such example is in representing addresses of different
memory locations. Let us assume that a machine has 64K of memory.
Such a memory has 64K (= 216 = 65 536) memory locations and needs
65 536 different addresses. These addresses can be designated as 0 to 65
535 in the decimal number system and 00000000 00000000 to 11111111
11111111 in the binary number system. The decimal number system is
not used in computers and the binary notation here appears too
cumbersome and inconvenient to handle. In the hexadecimal number
system, 65 536 different addresses can be expressed with four digits from
0000 to FFFF. Similarly, the contents of the memory when represented in
hexadecimal form are very convenient to handle.

6.7 Finding the Decimal Equivalent

The decimal equivalent of a given number in another number system is

given by the sum of all the digits multiplied by their respective place
values. The integer and fractional parts of the given number should be
treated separately. Binary-to-decimal, octal-to-decimal and hexadecimal-
to-decimal conversions are illustrated below with the help of examples.

6. 7.1 Binary-to-Decimal Conversion

The decimal equivalent of the binary number (1001.0101)2 is determined

as follows:

• The integer part = 1001

• The decimal equivalent = 1 × 20 + 0 × 21 + 0 × 22 + 1 × 23 = 1 + 0 + 0
+8=9
• The fractional part = .0101
• Therefore, the decimal equivalent = 0 × 2−1 + 1 × 2−2 + 0 × 2−3 + 1 × 2−4
= 0 + 0.25 + 0 + 0.0625 = 0.3125
• Therefore, the decimal equivalent of (1001.0101)2
= 9.3125

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(1)Addition rule in binary system:

0+1=1
1+0=1
0+0=0
1+1=0 1 carry

e.g: (111) 2 + (11) 2 = ( 10101 ) 2

( 7 )10 + (3) 10 = (10 ) 10

(2)subtraction rule in binary system

1-0=1
0-0=0
1-1=0
0 - 1 = 1 borrow 1 from the next more significant bit

e.g: (111) 2 - (11) 2 = ( 00100 ) 2

( 7 )10 - (3) 10 = (4 ) 10

6.7.2 Octal-to-Decimal Conversion

The decimal equivalent of the octal number (137.21)8 is determined as

follows:
• The integer part = 137
• The decimal equivalent = 7 × 80 + 3 × 81 + 1 × 82 = 7 + 24 + 64 = 95
The fractional part = .21
• The decimal equivalent = 2 × 8−1 + 1 × 8−2 = 0.265
• Therefore, the decimal equivalent of (137.21)8
= (95.265)10

6.7.3 Hexadecimal-to-Decimal Conversion

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The decimal equivalent of the hexadecimal number (1E0.2A)16 is
determined as follows:
• The integer part = 1E0
• The decimal equivalent = 0 × 160 + 14 × 161 + 1 × 162 = 0 + 224 + 256
= 480
• The fractional part = 2A
• The decimal equivalent = 2 × 16−1 + 10 × 16−2 = 0.164
• Therefore, the decimal equivalent of (1E0.2A)16
= (480.164)10

Example 6.2
Find the decimal equivalent of the following binary numbers expressed in
the 2‘s complement format:
(a) 00001110;
(b) 10001110.

Solution
(a) The MSB bit is ‗0‘, which indicates a plus sign.
The magnitude bits are 0001110.
The decimal equivalent = 0×20 +1×21+1×22 +1×23+0×24 +0×25+0×26
= 0+2+4+8+0+0+0 = 14
Therefore, 00001110 represents +14
(b) The MSB bit is ‗1‘, which indicates a minus sign
The magnitude bits are therefore given by the 2‘s complement of
0001110, i.e. 1110010
The decimal equivalent = 0×20 +1×21+0×22 +0×23+1×24 +1×25
+1×26
= 0+2+0+0+16+32+64 = 114
Therefore, 10001110 represents −114

6.8 Decimal-to-Binary Conversion

As outlined earlier, the integer and fractional parts are worked on

separately. For the integer part, the binary equivalent can be found by
successively dividing the integer part of the number by 2 and recording
the remainders until the quotient becomes ‗0‘. The remainders written in
reverse order constitute the binary equivalent. For the fractional part, it is
found by successively multiplying the fractional part of the decimal
number by 2 and recording the carry until the result of multiplication

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is ‗0‘. The carry sequence written in forward order constitutes the binary
equivalent of the fractional part of the decimal number. If the result of
multiplication does not seem to be heading towards zero in the case of the
fractional part, the process may be continued only until the requisite
number of equivalent bits has been obtained. This method of decimal–
binary conversion is popularly known as the double-dabble method. The
process can be best illustrated with the help of an example.

Example 6.3
We will find the binary equivalent of (13.375)10.

Solution
• The integer part = 13

Divisor Dividend Remainder

2 13 —
2 6 1
2 3 0
2 1 1
— 0 1

• The binary equivalent of (13)10 is therefore (1101)2

• The fractional part = .375
• 0.375 × 2 = 0.75 with a carry of 0
• 0.75 × 2 = 0.5 with a carry of 1
• 0.5 × 2 = 0 with a carry of 1
• The binary equivalent of (0.375)10
= (.011)2
• Therefore, the binary equivalent of (13.375)10
= (1101.011)2

Example For change of fraction number:

a) Binary equivalent
0.6875
2 x
------------
1.3750

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 2 x
------------
0.7500
2 X
---------------------------
1 . 500
2x
---------------------
1.000
0

(.6875)10 = (.1 0 1 1 )2

6.9 Decimal-to-Octal Conversion

The process of decimal-to-octal conversion is similar to that of decimal-

to-binary conversion. The progressive division in the case of the integer
part and the progressive multiplication while working on the fractional
part here are by ‗8‘ which is the radix of the octal number system. Again,
the integer and fractional parts of the decimal number are treated
separately. The process can be best illustrated with the help of an
example.

Example 6.4
We will find the octal equivalent of (73.75)10

Solution
• The integer part = 73
Divisor Dividend Remainder
8 73 —
8 9 1
8 1 1
— 0 1

The octal equivalent of (73)10 = (111)8

• The fractional part = 0.75

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• 0.75 × 8 = 0 with a carry of 6
• The octal equivalent of (0.75)10 = (.6)8
• Therefore, the octal equivalent of (73.75)10 = (111.6)8

6.10 Decimal-to-Hexadecimal Conversion

The process of decimal-to-hexadecimal conversion is also similar. Since
the hexadecimal number system has a base of 16, the progressive division
and multiplication factor in this case is 16. The process is illustrated
further with the help of an example.

Example 6.5
Let us determine the hexadecimal equivalent of (82.25)10

Solution
• The integer part = 82
Divisor Dividend Remainder
16 82 —
16 5 2
— 0 5

The hexadecimal equivalent of (82)10 = (52)16

• The fractional part = 0.25
• 0.25 × 16 = 0 with a carry of 4
• Therefore, the hexadecimal equivalent of (82.25)10 = (52.4)16

6.11 Binary–Octal and Octal–Binary Conversions

An octal number can be converted into its binary equivalent by replacing

each octal digit with its three-bit binary equivalent as in Fig.6.2 . We
take the three-bit equivalent because the base of the octal number system
is 8 and it is the third power of the base of the binary number system, i.e.
2. All we have then to remember is the three-bit binary equivalents of the
basic digits of the octal number system. A binary number can be
converted into an equivalent octal number by splitting the integer and
fractional parts into groups of three bits, starting from the binary point on
both sides. The 0s can be added to complete the outside groups if needed.

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 Fig.6.2

Example 6.6

Let us find the binary equivalent of (374.26)8 and the octal equivalent of
(1110100.0100111)2_
Solution
• The given octal number = (374.26)8
• The binary equivalent = (011 111 100.010 110)2
= 011111100.010110)2
• Any 0s on the extreme left of the integer part and extreme right of the
fractional part of the equivalent binary number should be omitted.
Therefore, (011111100.010110)2 = (11111100.01011)2
• The given binary number = (1110100.0100111)2
• (1110100.0100111)2 = (1 110 100.010 011 1)2
= (001 110 100.010 011 100)2= (164.234)8

6.12 Hex–Binary and Binary–Hex Conversions

A hexadecimal number can be converted into its binary equivalent by
replacing each hex digit with its four-bit binary equivalent as in Fig.6.3 .
We take the four-bit equivalent because the base of the hexadecimal

282
number system is 16 and it is the fourth power of the base of the binary
number system. All we have then to remember is the four-bit binary
equivalents of the basic digits of the hexadecimal number system. A
given binary number can be converted into an equivalent hexadecimal
number by splitting the integer
and fractional parts into groups of four bits, starting from the binary point
on both sides. The 0s can be added to complete the outside groups if
needed.

Fig. 6.3

Example 6.7

Let us find the binary equivalent of (17E.F6)16 and the hex equivalent of
(1011001110.011011101)2.

Solution
• The given hex number = (17E.F6)16
• The binary equivalent = (0001 0111 1110.1111 0110)2
= (000101111110.11110110)2
= (101111110.1111011)2
• The 0s on the extreme left of the integer part and on the extreme right of
the fractional part have been omitted.
• The given binary number = (1011001110.011011101)2
= (10 1100 1110.0110 1110 1)2

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• The hex equivalent = (0010 1100 1110.0110 1110 1000)2
= (2CE.6E8)16

6.13 Hex–Octal and Octal–Hex Conversions

For hexadecimal–octal conversion, the given hex number is firstly
converted into its binary equivalent which is further converted into its
octal equivalent. An alternative approach is firstly to convert the given
hexadecimal number into its decimal equivalent and then convert the
decimal number into an equivalent octal number. The former method is
definitely more convenient and straightforward. For octal–hexadecimal
conversion, the octal number may first be converted into an equivalent
binary number and then the binary number transformed into its hex
equivalent. The other option is firstly to convert the given octal number
into its decimal equivalent and then convert the decimal number into its
hex equivalent. The former approach is definitely the preferred one. Two
types of conversion are illustrated in the following example.

Example 6.8
Let us find the octal equivalent of (2F.C4)16 and the hex equivalent of
(762.013)8.

Solution
• The given hex number = (2F.C4)16.
• The binary equivalent = (0010 1111.1100 0100)2 =
=(00101111.11000100)2 = (101111.110001)2
= (101 111.110 001)2= (57.61)8.
• The given octal number = (762.013)8.
• The octal number = (762.013)8 = (111 110 010.000 001 011)2
= (111110010.000001011)2
= (0001 1111 0010.0000 0101 1000) 2
= (1F2.058)16.

6.14. Introduction to Boolean Algebra

Boolean algebra, quite interestingly, is simpler than ordinary algebra. It is
also composed of a set of symbols and a set of rules to manipulate these

284
symbols. However, this is the only similarity between the two. The
differences are many. These include the following:
1. In ordinary algebra, the letter symbols can take on any number of
values including infinity. In Boolean algebra, they can take on either of
two values, that is, 0 and 1.
2. The values assigned to a variable have a numerical significance in
ordinary algebra, whereas in its Boolean counterpart they have a logical
significance.
3. While ‗.‘ and ‗+‘ are respectively the signs of multiplication and
addition in ordinary algebra, in Boolean algebra ‗.‘ means an AND
operation and ‗+‘ means an OR operation. For instance, A+B in ordinary
algebra is read as A plus B, while the same in Boolean algebra is read as
A OR B.
a) X AND Y = X.Y
X Y X AND Y

0 1 0

1 0 0

1 1 1

0 0 0

b) X OR Y = X +Y
X Y X OR Y

0 1 1

1 0 1

1 1 1

0 0 0

c)NOT X:

285
 X NOT X

0 1

1 0

4. More specifically, Boolean algebra captures the essential properties of

both logic operations such as AND, OR and NOT and set operations such
as intersection, union and complement. As an illustration, the logical
assertion that both a statement and its negation cannot be true has a
counterpart in set theory, which says that the intersection of a subset and
its complement is a null (or empty) set.
5. Boolean algebra may also be defined to be a set A supplied with two
binary operations of logical AND (A), logical OR (V), a unary operation
of logical NOT (￢) and two elements, namely logical FALSE (0) and
logical TRUE (1). This set is such that, for all elements of this set, the
postulates or axioms relating to the associative, commutative,
distributive, absorption and complementation properties of these elements
hold good. These postulates are described in the following pages.

6.14.1 Variables, Literals and Terms in Boolean Expressions

Variables are the different symbols in a Boolean expression. They may
take on the value ‗0‘ or ‗1‘. For instance, in expression (6.1), A, B and C
are the three variables. In expression (6.2), P, Q, R and S are the
variables:

A'+A.B+A.C' +A'.B.C (6.1)

(P +Q) .(R+S).(P +Q+R) (6.2)

The complement of a variable is not considered as a separate variable.

Each occurrence of a variable or its complement is called a literal. In
expressions (6.1) and (6.2) there are eight and seven literals respectively.
A term is the expression formed by literals and operations at one level.
Expression (6.1) has five terms including four AND terms and the OR
term that combines the first-level AND terms.

6.14.2 Equivalent and Complement of Boolean Expressions

286
Two given Boolean expressions are said to be equivalent if one of them
equals ‗1‘ only when the other equals ‗1‘ and also one equals ‗0‘ only
when the other equals ‗0‘. They are said to be the complement of each
other if one expression equals ‗1‘ only when the other equals ‗0‘, and vice
versa. The complement of a given Boolean expression is obtained by
complementing each literal, changing all ‗.‘ to ‗+‘ and all ‗+‘ to ‗.‘, all 0s
to 1s and all 1s to 0s. The examples below give some Boolean
expressions and their complements:

Given Boolean expression A'.B+A.B' (6.3)

Corresponding complement (A+B').(A+B) (6.4)

Given Boolean expression

(A+B).(A'+B') (6.5)

Corresponding complement A'.B'+A.B (6.6)

When O Red with its complement the Boolean expression yields a ‗1‘,
and when AND Red with its complement it yields a ‗0‘. The ‗.‘ sign is
usually omitted in writing Boolean expressions and is implied merely by
writing the literals in juxtaposition. For instance, A.B would normally be
written as AB.

6.14.3 Dual of a Boolean Expression

The dual of a Boolean expression is obtained by replacing all ‗.‘

operations with ‗+‘ operations, all ‗+‘ operations with ‗.‘ operations, all
0s with 1s and all 1s with 0s and leaving all literals unchanged.
The examples below give some Boolean expressions and the
corresponding dual expressions:

Given Boolean expression A'.B+A.B' (6.7)

Corresponding dual (A'+B).(A+B') (6.8)

Given Boolean expression (A+B).(A'+B') (6.9)

Corresponding dual A.B + A'.B' (6.10)

Duals of Boolean expressions are mainly of interest in the study of

Boolean postulates and theorems. Otherwise, there is no general
relationship between the values of dual expressions. That is, both of them
may equal ‗1‘ or ‗0‘. One may even equal ‗1‘ while the other equals ‗0‘.
287
The fact that the dual of a given logic equation is also a valid logic
equation leads to many more useful laws of Boolean algebra. The
principle of duality has been put to ample use during the discussion on
postulates and theorems of Boolean algebra.

6.15 Postulates of Boolean Algebra

The following are the important postulates of Boolean algebra:

1. 1.1 = 1 , 0+0 = 0.
2. 1.0 = 0.1 = 0 , 0+1 = 1+0 = 1.
3. 0.0 = 0 , 1+1 = 1.
4. 1' = 0 and 0' = 1.

Many theorems of Boolean algebra are based on these postulates, which

can be used to simplify Boolean expressions. These theorems are
discussed in the next section.

6.16Theorems of Boolean Algebra

288
289
290
6.17 Logic Gates

The logic gate is the most basic building block of any digital system,
including computers. Each one of the basic logic gates is a piece of
hardware or an electronic circuit that can be used to implement some
basic logic expression. While laws of Boolean algebra could be used to
do manipulation with binary variables and simplify logic expressions,
these are actually implemented in a digital system with the help of
electronic circuits called logic gates. The three basic logic gates are the
OR gate, the AND gate and the NOT gate.

6.17.1 OR Gate
An OR gate performs an O Ring operation on two or more than two logic
variables. The OR operation on two independent logic variables A and B
is written as Y = A+B and reads as Y equals A OR B and not as A plus B.
An OR gate is a logic circuit with two or more inputs and one output. The
output of an OR gate is LOW only when all of its inputs are LOW. For all
other possible input combinations, the output is HIGH. This statement
when interpreted for a positive logic system means the following.
The output of an OR gate is a logic ‗0‘ only when all of its inputs are at
logic ‗0‘. For all other possible input combinations, the output is a logic
‗1‘. Fig. 6.4 shows the circuit symbol and the truth table of a two-input
OR gate. The operation of a two-input OR gate is explained by the logic
expression

Y = A+B

291
As an illustration, if we have four logic variables and we want to know
the logical output of (A+ B+C +D), then it would be the output of a four-
input OR gate with A, B, C and D as its inputs (Fig.6.5).

Fig. 6.4 Two-input OR gate.

(Fig.6.5) (a) Three-input OR gate, (b) four-input OR gate and (c) the
truth table of a three-input OR gate.

292
Fig. 6.5(a) and (b) show the circuit symbol of three-input and four-input
OR gates. Figure 4.4(c) shows the truth table of a three-input OR gate.
Logic expressions explaining the functioning of three input and four-
input OR gates are Y = A+B+C and Y = A+B+C +D.

Example
How would you hardware-implement a four-input OR gate using two-
input OR gates only?

Solution
Fig.6.6(a) shows one possible arrangement of two-input OR gates that
simulates a four-input OR gate. A, B, C and D are logic inputs and Y3 is
the output. Figure 6.6(b) shows another possible arrangement. In the case
of Fig. 6.6(a), the output of OR gate 1 is Y1 = (A+B). The second

Fig.6.6

OR gate produces the output Y 2 = (Y 1+C) = (A+B+C). Similarly, the

output of OR gate 3 is Y3 = (Y 2+D) = (A+B+C+D0. In the case of Fig.
6.6(b), the output of OR gate 1 is Y 1 = (A+B0.
The second OR gate produces the output Y2 = 9C +D0. Output Y 3 of the
third OR gate is given by
9Y 1+Y20 = (A+B+C +D).

6.17.2 AND Gate

An AND gate is a logic circuit having two or more inputs and one output.
The output of an AND gate is HIGH only when all of its inputs are in the
HIGH state. In all other cases, the output is LOW. When interpreted for a
positive logic system, this means that the output of the AND gate is a
logic ‗1‘ only when all of its inputs are in logic ‗1‘ state. In all other
cases, the output is logic ‗0‘. The logic symbol and truth table of a two-

293
input AND gate are shown in Figs 6.7(a) and (b) respectively. Fig. 6.8(a)
and (b) show the logic symbols of three-input and four-input AND

Figs 6.7 Two-input AND gate.

Fig. 6.8

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gates respectively. Fig.6.8(c) gives the truth table of a four-input AND
gate. The AND operation on two independent logic variables A and B is
written as Y = A_B and reads as Y equals A AND B and not as A
multiplied by B. Here, A and B are input logic variables and Y is the
output. An AND gate performs an AND operation:
• for a two-input AND gate, Y = A.B
• for a three-input AND gate, Y = A.B.C
• for a four-input AND gate, Y = A.B.C.D.
If we interpret the basic definition of OR and AND gates for a negative
logic system, we have an interesting observation. We find that an OR gate
in a positive logic system is an AND gate in a negative logic system.
Also, a positive AND is a negative OR.

6.17.3 NOT Gate

A NOT gate is a one-input, one-output logic circuit whose output is
always the complement of the input. That is, a LOW input produces a
HIGH output, and vice versa. When interpreted for a positive logic
system, a logic ‗0‘ at the input produces a logic ‗1‘ at the output, and vice
versa. It is also known as a ‗complementing circuit‘ or an ‗inverting
circuit‘ Fig.6.9 shows the circuit symbol and the truth table.
The NOT operation on a logic variable X is denoted as X' . That is, if X
is the input to a NOT circuit, then its output Y is given by Y = X' and
reads as Y equals NOT X. Thus, if X = 0 , Y = 1 and if X = 1,Y = 0.

Fig.6.9 (a) Circuit symbol of a NOT circuit and (b) the truth table of a
NOT circuit

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6.17.4 EXCLUSIVE-OR Gate
The EXCLUSIVE-OR gate, commonly written as EX-OR gate, is a two-
input, one-output gate. Fig.6.10(a) and (b) respectively show the logic
symbol and truth table of a two-input EX-OR gate. As can be seen from
the truth table, the output of an EX-OR gate is a logic ‗1‘ when the inputs
are unlike and a logic ‗0‘ when the inputs are like. Although EX-OR
gates are available in integrated circuit form only as two-input gates,
unlike other gates which are available in multiple inputs also, multiple-

Fig.6.10 (a) Circuit symbol of a two-input EXCLUSIVE-OR gate, (b) the

truth table of a two-input EXCLUSIVE-OR gate and (c) the truth table of
a four-input EXCLUSIVE-OR gate.

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input EX-OR logic functions can be implemented using more than one
two-input gates. The truth table of a multiple-input EX-OR function can
be expressed as follows. The output of a multiple-input EX-OR logic
function is a logic ‗1‘ when the number of 1s in the input sequence is odd
and a logic ‗0‘ when the number of 1s in the input sequence is even,
including zero. That is, an all 0s input sequence also produces a logic ‗0‘
at the output. Fig.6.10(c) shows the truth table of a four-input EX-OR
function. The output of a two-input EX-OR gate is expressed by:
Y = (A⊕B0 = A'B+AB'

6.17.5 NAND Gate

NAND stands for NOT AND. An AND gate followed by a NOT circuit
makes it a NAND gate [Fig. 6.11(a)]. Figure 4.15(b) shows the circuit
symbol of a two-input NAND gate. The truth table of a NAND gate is
obtained from the truth table of an AND gate by complementing the
output entries [Fig. 6.11(c)]. The output of a NAND gate is a logic ‗0‘
when all its inputs are a logic ‗1‘. For all other input combinations, the
output is a logic ‗1‘. NAND gate operation is logically expressed as:

Fig.6.11 (a) Two-input NAND implementation using an AND gate and a NOT circuit,
(b) the circuit symbol of a two-input NAND gate and (c) the truth table of a two-input
NAND gate.

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6.17.6 NOR Gate
NOR stands for NOT OR. An OR gate followed by a NOT circuit makes
it a NOR gate [Fig. 6.12(a)]. The truth table of a NOR gate is obtained
from the truth table of an OR gate by complementing the output entries.
The output of a NOR gate is a logic ‗1‘ when all its inputs are logic ‗0‘.
For all other input combinations, the output is a logic ‗0‘. The output of a
two-input NOR gate is logically expressed as:

Fig.6.12 (a) Two-input NOR implementation using an OR gate and a

NOT circuit, (b) the circuit symbol of a two-input NOR gate and (c) the
truth table of a two-input NOR gate.

6.17.7 EXCLUSIVE-NOR Gate

EXCLUSIVE-NOR (commonly written as EX-NOR) means NOT of EX-
OR, i.e. the logic gate that we get by complementing the output of an EX-
OR gate. Fig.6.13 shows its circuit symbol along with its truth table. The
truth table of an EX-NOR gate is obtained from the truth table of an EX-
OR gate by complementing the output entries. Logically,:

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The output of a two-input EX-NOR gate is a logic ‗1‘ when the inputs are
like and a logic ‗0‘ when they are unlike. In general, the output of a
multiple-input EX-NOR logic function is a logic ‗0‘ when the number of
1s in the input sequence is odd and a logic ‗1‘ when the number of 1s in
the input sequence is even including zero. That is, an all 0s input
sequence also produces a logic ‗1‘ at the output.

Fig.6.13 (a) Circuit symbol of a two-input EXCLUSIVE-NOR gate and

(b) the truth table of a two-input EXCLUSIVE-NOR gate.

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Solved Examples

1-Draw the Circuit that Achieve the following Expression:

Solution:

Fig. 6.14

2-Draw the Circuit that Achieve the following Expression:

Solution:

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 Fig. 6.15

3-Draw the Circuit that Achieve the following Expression:

Solution

Fig. 6.16

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4-Draw the Circuit that Achieve the following Expression:

Solution

Fig. 6.17

5-Draw the Circuit that Achieve the following Expression:

Solution

Fig. 6.18

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6-Draw the Circuit that Achieve the following Expression:

Solution

Fig. 6.19

7-Draw the Circuit that Achieve the following Expressions:

Solutions

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 Fig. 6.20

8-Draw the Circuit that Achieve the following Expressions:

Solutions

304
 Fig. 6.21

6.18 Minimization by Karnaugh Maps

• What is a Karnaugh map?

– 3 Variable Example:

– A grid of squares
– Each square represents one minterm
• eg: top-left represents , bottom-right represents
– The minterms are ordered according to Gray code
• only one variable changes between adjacent squares
– Squares on edges are considered adjacent to squares on opposite
edges

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– Karnaugh maps become clumsier to use with more than 4 variables

6.18.1 Filling out a Karnaugh Map

• Write the Boolean expression in SOP form(Sum-of-products form

• For each product term, write a 1 in all the squares which are included in
the term, 0 elsewhere
– canonical form: one square
– one term missing: two adjacent squares
– two terms missing: 4 adjacent squares

Example

– hence they can be combined into just BC

– normally indicated by grouping the adjacent squares to be
Combined.

Adjacent Pairs
– The same idea extends to pairs of pairs.

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The following examples illustrates the simplifications using
Karnaugh Map using the following steps:

Complete Simplification Process

1. Construct the K map and place 1s and 0s in the squares

according to the truth table.

2. Group the isolated 1s which are not adjacent to any other

1s. (single loops)

3. Group any pair which contains a 1 adjacent to only one

other 1. (double loops)

4. Group any octet even if it contains one or more 1s that have

already been grouped.

5. Group any quad that contains one or more 1s that have not
already been grouped, making sure to use the minimum number of
groups.

6. Group any pairs necessary to include any 1s that have not

yet been grouped, making sure to use the minimum number of groups.

7. Form the OR sum of all the terms generated by each group.

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308
309
6.19. Flip-Flop and Introductory Sequential Logic

We now turn to digital circuits which have states which change in time,
usually according to an external clock. The flip-flop is an important
element of such circuits. It has the interesting property of memory: It can
be set to a state which is retained until explicitly reset.

6.19.1 Simple Latches

The following 3 Figures are equivalent representations of a simple circuit.
In general these are called flip-flops. Specially, these examples are called
SR ("set-reset") flip-flops, or SR latches.

Fig.6.22

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 Fig.6.23

For the truth table shown in Fig.6.23 ,the state described by the last row
is clearly problematic, since Q and Q' should not be the same value.
Thus, the S = R = 1 inputs should be avoided. From the truth table, we
can develop a sequence such as the following:

1. R = 0, S = 1 Q = 1 (set)
2. R = 0, S = 0 Q = 1 (Q = 1 state retained: \memory")
3. R = 1, S = 0 Q = 0 (reset)
4. R = 0, S = 0 Q = 0 (Q = 0 state retained)

In alternative language, the _rst operation \writes" a true state into one bit
of memory. It can subsequently be \read" until it is erased by the reset
operation of the third line.

Fig.6.24 shows alternative representation of SR Latch.

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 Fig.6.24

6.19.2 Clocked Flip-flops

We will soon get used to the idea of a clock as an essential element of
digital circuitry. When we speak of a clock signal, we mean a sequence of
evenly spaced digital high and low signals proceeding at a fixed
frequency. That is, the clock is a continuous sequence of square wave
pulses. There are a number of reasons for the importance of the clock.
Clearly it is essential for doing any kind of counting or timing operation.
But, its most important role is in providing synchronization to the digital
circuit. Each clock pulse may represent the transition to a new digital
state of a so-called \state machine" (simple processor) we will soon
encounter. Or a clock pulse may correspond to the movement of a bit of
data from one location in memory to another. A digital circuit coordinates
these various functions by the synchronization provided by a single clock
signal which is shared throughout the circuit. A more sophisticated
example of this concept is the clock of a computer, which we have come
to associate with processing speed (e.g. 330 MHz for typical current
generation commercial processors.)
We can include a clock signal to our simple SR flip-flop, as shown in
Fig. 6.25. The truth table, given below, follows directly from our previous
SR flip-flop, except now we include a label for the nth clock pulse for the
inputs and the output. This is because the inputs have no effect unless
they coincide with a clock pulse. (Note that a specified clock pulse
conventionally refers to a HIGH level.) As indicated in the truth table, the
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inputs Sn = Rn = 0 represent the flip-flop memory state. Significantly, one
notes that the interval between clock pulses also corresponds to the
"retain previous state" of the flip-flop. Hence the information encoded
by the one bit of flip-flop memory can only be modified in
synchronization with the clock.

Fig. 6.25

We are now set to make a subtle transition for our next version of the
clocked flip-flop. The flip-flop memory is being used to retain the state
between clock pulses. In fact, the state set up by the S and R inputs can be
represented by a single input we call "data", or D. This is shown in Fig.
6.26. Note that we have explicitly eliminated the bad S = R = 1 state with
this configuration. We can override this data input and clock
synchronization scheme by including the "jam set" (S) and "jam reset" (R)
inputs shown in Fig. 15. These function just as before with the unclocked
SR flip-flop. Note that these \jam" inputs go by various names. So

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sometimes the set is called "preset" and reset is called "clear", for
example.

Fig. 6.26

A typical timing diagram for this flip-flop is given in Fig.6.27. Note that
the jam reset signal R overrides any action of the data or clock inputs.

Fig.6.27

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Fig.6.28 shows clocked D Flip-Flop that triggers only on positive- going
transitions and waveforms with its truth table..

Fig.6.28

6.19.3 J-K Flip-Flop (contains Master–Slave Flip-Flops)

This flip-flop can be obtained from the SR Flip-Flop by developing two

AND gates. Data input J and output Q' are applied to the first And gate
which output feed S, so S = JQ'. Similarly data input K and output Q
applied to the second AND gate, so R = KQ. Fig.6.29 shows the symbolic
and truth table for this flop-flip while Fig.6.30 shows details of the its
structure and Fig.6.31 illustrates the waveforms.

315
Fig.6.29

316
 Fig.6.30

Fig.6.31

6.19.4 Toggle Flip-Flop (T Flip-Flop)

The output of a toggle flip-flop, also called a T flip-flop, changes state
every time it is triggered at its T input, called the toggle input. That is, the
output becomes ‗1‘ if it was ‗0‘ and ‗0‘ if it was ‗1‘. This type as it is
clear , change the state with each clock pulse , so it works as a toggle
switch, if J = K = 1 , then Qn+1 = Q'n , therefore J-K flip-flop is coferted
with such conditions to T-Flip-Flop.

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6.20 Counters and Registers

Counters and registers belong to the category of MSI sequential logic

circuits. They have similar architecture, as both counters and registers
comprise a cascaded arrangement of more than one flip-flop with or
without combinational logic devices. Both constitute very important
building blocks of sequential logic, and different types of counter and
register available in integrated circuit (IC) form are used in a wide range
of digital systems. While counters are mainly used in counting
applications, where they either measure the time interval between two
unknown time instants or measure the frequency of a given signal,
registers are primarily used for the temporary storage of data present at
the output of a digital circuit before they are fed to another digital circuit.
We are all familiar with the role of different types of register used inside
a microprocessor, and also their use in microprocessor-based
applications. Because of the very nature of operation of registers, they
form the basis of a very important class of counters called shift counters.

6.20.1 Ripple (Asynchronous) Counter

A ripple counter is a cascaded arrangement of flip-flops where the output

of one flip-flop drives the clock input of the following flip-flop. The
number of flip-flops in the cascaded arrangement depends upon the
number of different logic states that it goes through before it repeats the
sequence, a parameter known as the modulus of the counter.
In a ripple counter, also called an asynchronous counter or a serial
counter, the clock input is applied only to the first flip-flop, also called
the input flip-flop, in the cascaded arrangement. The clock input to any
subsequent flip-flop comes from the output of its immediately preceding
flip-flop. For instance, the output of the first flip-flop acts as the clock
input to the second flip-flop, the output of the second flip-flop feeds the
clock input of the third flip-flop and so on. In general, in an arrangement
of n flip-flops, the clock input to the nth flip-flop comes from the output
of the (n−1)th flip-flop for n>1. Fig.6.32 shows the generalized block
schematic arrangement of an n-bit binary ripple counter.
As a natural consequence of this, not all flip-flops change state at the
same time. The second flip-flop can change state only after the output of
the first flip-flop has changed its state. That is, the second flip-flop would
change state a certain time delay after the occurrence of the input clock
pulse owing to the fact that it gets its own clock input from the output of

318
the first flip-flop and not from the input clock. This time delay here
equals the sum of propagation delays of two flip-flops, the first and the
second flip-flops. In general, the nth flip-flop will change state only after
a delay equal to n times the propagation delay of one flip-flop. The term
‗ripple counter‘ comes from the mode in which the clock information
ripples through the counter. It is also called an ‗asynchronous counter‘ as
different flip-flops comprising the counter do not change state in
synchronization with the input clock.

Fig.6.32 Generalized block schematic of n-bit binary ripple counter.

In a counter like this, after the occurrence of each clock input pulse, the
counter has to wait for a time period equal to the sum of propagation
delays of all flip-flops before the next clock pulse can be applied. The
propagation delay of each flip-flop, of course, will depend upon the logic
family to which it belongs.

6.20.2 Synchronous Counter

In a synchronous counter, also known as a parallel counter, all the flip-

flops in the counter change state at the same time in synchronism with the
input clock signal. The clock signal in this case is simultaneously applied
to the clock inputs of all the flip-flops. The delay involved in this case is
equal to the propagation delay of one flip-flop only, irrespective of the
number of flip-flops used to construct the counter. In other words, the
delay is independent of the size of the counter.

6.20.3 Binary Ripple Counter – Operational Basics

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The operation of a binary ripple counter can be best explained with the
help of a typical counter of this type. Fig.6.33(a) shows a four-bit ripple
counter implemented with negative edge-triggered J-K flip-flops wired as
toggle flip-flops. The output of the first flip-flop feeds the clock input of
the second, and the output of the second flip-flop feeds the clock input of
the third, the output of which in turn feeds the clock input of the fourth
flip-flop. The outputs of the four flip-flops are designated as Q0 , Q1, Q2
and Q3 . Fig.6.33(b) shows the waveforms appearing at Q0, Q1, Q2 and
Q3 outputs as the clock signal goes through successive cycles of trigger
pulses. The counter functions as follows:

Fig.6.33 Four-bit binary ripple counter.

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 Let us assume that all the flip-flops are initially cleared to the ‗0‘ state.
On HIGH-to-LOW transition of the first clock pulse, Q0 goes from ‗0‘ to
‗1‘ owing to the toggling action. As the flip-flops used are negative edge-
triggered ones, the ‗0‘ to ‗1‘ transition of Q0 does not trigger flip-flop
FF1. FF1, along with FF2 and FF3, remains in its ‗0‘ state. So, on the
occurrence of the first negative-going clock transition, Q0 = 1, Q1 = 0, Q2
= 0 and Q3 = 0.
On the HIGH-to-LOW transition of the second clock pulse, Q0 toggles
again. That is, it goes from ‗1‘ to ‗0‘. This ‗1‘ to ‗0‘ transition at the Q0
output triggers FF1, the output Q1 of which goes from ‗0‘ to ‗1‘. The Q2
and Q3 outputs remain unaffected. Therefore, immediately after the
occurrence of the second HIGH-to-LOW transition of the clock signal, Q0
= 0, Q1 = 1, Q2 = 0 and Q3 = 0. On similar lines, we can explain the logic
status of Q0, Q1, Q2 and Q3 outputs immediately after subsequent clock
transitions. The logic status of outputs for the first 16 relevant (HIGH-to-
LOW in the present case) clock signal transitions is summarized in Table
1.

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 Thus, we see that the counter goes through 16 distinct states from
0000 to 1111 and then, on the occurrence of the desired transition of the
sixteenth clock pulse, it resets to the original state of 0000 from where it
had started. In general, if we had N flip-flops, we could count up to 2N
pulses before the counter resets to the initial state. We can also see from
the Q0, Q1, Q2 and Q3 waveforms, as shown in Fig. 6.33(b), that the
frequencies of the Q0, Q1, Q2 and Q3 waveforms are f/2,f/4, f/8 and f/16
respectively. Here, f is the frequency of the clock input. This implies that
a counter of this type can be used as a divide-by-2N circuit, where N is
the number of flip-flops in the counter chain. In fact, such a counter
provides frequency-divided outputs of f/2N , f/2N−1, f/2N−2, f/2N−3, _ _ _ ,
f/2 at the outputs of the Nth, (N− 1)th, (N − 2)th, (N− 3)th, _ _ _ , first
flip-flops. In the case of a four-bit counter of the type shown in Fig.
6.33(a), outputs are available at f/2 from the Q0 output, at f/4 from the Q1
output, at f/8 from the Q2 output and at f/16 from the Q3 output. It may
be noted that frequency division is one of the major applications of
counters.

6.20.4 Synchronous (or Parallel) Counters

Ripple counters discussed thus far in this chapter are asynchronous in

nature as the different flip-flops comprising the counter are not clocked
simultaneously and in synchronism with the clock pulses. The total
propagation delay in such a counter, as explained earlier, is equal to the
sum of propagation delays due to different flip-flops. The propagation
delay becomes prohibitively large in a ripple counter with a large count.
On the other hand, in a synchronous counter, all flip-flops in the counter
are clocked simultaneously in synchronism with the clock, and as a
consequence all flip-flops change state at the same time. The propagation
delay in this case is independent of the number of flip-flops used.
Since the different flip-flops in a synchronous counter are clocked at
the same time, there needs to be additional logic circuitry to ensure that
the various flip-flops toggle at the right time. For instance, if we look at
the count sequence of a four-bit binary counter shown in Table II, we find
that flip-flop FF0 toggles with every clock pulse, flip-flop FF1 toggles
only when the output of FF0 is in the ‗1‘ state, flip-flop FF2 toggles only
with those clock pulses when the outputs of FF0 and FF1 are both in the
logic ‗1‘ state and flip-flop FF3 toggles only with those clock pulses
when Q0,Q1and Q2 are all in the logic ‗1‘ state. Such logic can be easily
implemented with AND gates. Fig.6.34(a) shows the schematic
arrangement of a four-bit synchronous counter. The timing waveforms

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are shown in Fig.6.34(b). The diagram is self-explanatory. As an
example, ICs 74162 and 74163 are four-bit synchronous counters, with
the former being a decade counter and the latter a binary counter.

A synchronous counter that counts in the reverse or downward sequence

can be constructed in a similar manner by using complementary outputs
of the flip-flops to drive the J and K inputs of the following flip-flops.
Refer to the reverse or downward count sequence as given in Table. III.
As is evident from the table, FF0 toggles with every clock pulse, FF1
toggles only when Q0 is logic ‗0‘, FF2 toggles only when both Q0 and
Q1 are in the logic ‗0‘ state and FF3 toggles only when Q0, Q1 and Q2
are in the logic ‗0‘ state.
Referring to the four-bit synchronous UP counter of Fig. 6.34(a), if the
J and K inputs of flip-flop FF1 are fed from the Q0 output instead of the
Q0 output, the inputs to the two-input AND gate are Q0 and Q1 instead
of Q0 and Q1, and the inputs to the three-input AND gate are Q0, Q1 and
Q2 instead of Q0, Q1 and Q2_, we get a counter that counts in reverse
order. In that case it becomes a four-bit synchronous DOWN counter.

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Fig. 6.34 Four-bit synchronous counter.

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6.20.5 UP/DOWN Counters
Counters are also available in integrated circuit form as UP/DOWN
counters, which can be made to operate as either UP or DOWN counters.
As outlined in Section.6.20. 4 above, an UP counter is one that counts
upwards or in the forward direction by one LSB every time it is clocked.
A four-bit binary UP counter will count as 0000, 0001, 0010, 0011, 0100,
0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111,
0000, 0001, _ _ _ and so on. A DOWN counter counts in the reverse
direction
or downwards by one LSB every time it is clocked. The four-bit binary
DOWN counter will count as 0000, 1111, 1110, 1101, 1100, 1011, 1010,
1001, 1000, 0111, 0110, 0101, 0100, 0011, 0010, 0001, 0000, 1111, _ _ _
and so on.
Some counter ICs have separate clock inputs for UP and DOWN
counts, while others have a single clock input and an UP/DOWN control
pin. The logic status of this control pin decides the counting mode. As an
example, ICs 74190 and 74191 are four-bit UP/DOWN counters in the
TTL family with a single clock input and an UP/DOWN control pin.
While IC 74190 is a BCD decade counter, IC 74191 is a binary counter.
Also, ICs 74192 and 74193 are four-bit UP/DOWN counters in the TTL
family, with separate clock input terminals for UP and DOWN counts.
While IC 74192 is a BCD decade counter, IC 74193 is a binary counter.
Fig.6.35 shows a three-bit binary UP/DOWN counter. This is only one
possible logic arrangement. As we can see, the counter counts upwards
when UP control is logic ‗1‘ and DOWN control is logic ‗0‘. In this case

325
the clock input of each flip-flop other than the LSB flip-flop is fed from
the normal output of the immediately preceding flip-flop. The counter
counts downwards when the UP control input is logic ‗0‘ and DOWN
control is logic ‗1‘. In this case, the clock input of each flip-flop other
than the LSB flip-flop is fed from the complemented output of the
immediately preceding flip-flop. Fig.6.36 shows another possible
configuration for a three-bit binary ripple
UP/DOWN counter. It has a common control input. When this input is in
logic ‗1‘ state the counter counts downwards, and when it is in logic ‗0‘
state it counts upwards.

Fig.6.35 Four-bit UP/DOWN counter.

Fig.6.36 Three-bit UP/DOWN counter with a common clock input.

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6.21 Shift Register
A shift register is a digital device used for storage and transfer of data.
The data to be stored could be the data appearing at the output of an
encoding matrix before they are fed to the main digital system for
processing or they might be the data present at the output of a
microprocessor before they are fed to the driver circuitry of the output
devices. The shift register thus forms an important link between the main
digital system and the input/output channels. The shift registers can also
be configured to construct some
special types of counter that can be used to perform a number of
arithmetic operations such as subtraction, multiplication, division,
complementation, etc. The basic building block in all shift registers is the
flipflop, mainly a D-type flip-flop. Although in many of the commercial
shift register ICs their internal circuit diagram might indicate the use of
R-S flip-flops, a careful examination will reveal that these R-S flip-flops
have been wired as D flip-flops only.
The storage capacity of a shift register equals the total number of bits
of digital data it can store, which in turn depends upon the number of flip-
flops used to construct the shift register. Since each flip-flop can store
one bit of data, the storage capacity of the shift register equals the number
of flip-flops used. As an example, the internal architecture of an eight-bit
shift register will have a cascade arrangement of eight flip-flops.
Based on the method used to load data onto and read data from shift
registers, they are classified as serial-in serial-out (SISO) shift registers,
serial-in parallel-out (SIPO) shift registers, parallel-in serial-out (PISO)
shift registers and parallel-in parallel-out (PIPO) shift registers.
Fig.6.37 shows a circuit representation of the above-mentioned four
types of shift register.

327
 Fig.6.37 Circuit representation of shift registers.

6.21.1 Serial-In Serial-Out Shift Register

Fig.6.38 shows the basic four-bit serial-in serial-out shift register
implemented using D flip-flops. The circuit functions as follows. A reset
applied to the CLEAR input of all the flip-flops resets their Q outputs to
0s. Refer to the timing waveforms of Fig.6.39. The waveforms shown
include the clock pulse train, the waveform representing the data to be
loaded onto the shift register and the Q outputs of different flip-flops.
The flip-flops shown respond to the LOW-to-HIGH transition of the
clock pulses as indicated by their logic symbols. During the first clock
transition, the QA output goes from logic ‗0‘ to logic ‗1‘.
The outputs of the other three flip-flops remain in the logic ‗0‘ state as
their D inputs were in the logic ‗0‘ state at the time of clock transition.
During the second clock transition, the QA output goes from logic ‗1‘ to
logic ‗0‘ and the QB output goes from logic ‗0‘ to logic ‗1‘, again in
accordance with the logic status of the D inputs at the time of relevant
clock transition.
Thus, we have seen that a logic ‗1‘ that was present at the data input
prior to the occurrence of the first clock transition has reached the QB

328
output at the end of two clock transitions. This bit will reach the QD
output at the end of four clock transitions. In general, in a four-bit shift
register of the type shown in Fig. Fig.6.38, a data bit present at the data
input terminal at the time of the nth clock transition reaches the QD
output at the end of the (n+4)th clock transition. During the fifth and
subsequent clock transitions, data bits continue to shift to the right, and at
the end of the eighth clock transition the shift register is again reset to all
0s. Thus, in a four-bit serial-in serial-out shift register, it takes four clock
cycles to load the data bits and another four cycles to read the data bits
out of the register. The contents of the register for the first eight clock
cycles are summarized in Table 4. We can see that the register is loaded
with the four-bit data in four clock cycles, and also that the stored four-bit
data are read out in the subsequent four clock cycles.

Fig.6.38 Serial-in, serial-out shift register.

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 Fig.6.39. Timing waveforms for the shift register of Fig. 6.38.

6.21.2 Serial-In Parallel-Out Shift Register

A serial-in parallel-out shift register is architecturally identical to a serial-
in serial-out shift register except that in the case of the former all flip-flop
outputs are also brought out on the IC terminals. Fig.6.40 shows the logic
diagram of a typical serial-in parallel-out shift register. In fact, the logic
diagram shown in Fig. 6.40 is that of IC 74164, a popular eight-bit serial-
in parallel-out shift register. The gated serial inputs A and B control the
incoming serial data, as a logic LOW at either of the inputs inhibits entry
of new data and also resets the first flip-flop to the logic LOW level at the
next clock pulse. Logic HIGH at either of the inputs enables the other
input, which then determines the state of the first flip-flop.
Data at the serial inputs may be changed while the clock input is HIGH
or LOW, and the register responds to LOW-to-HIGH transition of the
clock. Fig.6.41 shows the relevant timing waveforms.

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 Fig.6.40 Logic diagram of IC 74164.

Fig.6.41 Timing waveforms of IC 74164.

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6.21.3 Parallel-In Serial-Out Shift Register
We will explain the operation of a parallel-in serial-out shift register with
the help of the logic diagram of a practical device available in IC form.
Fig.6.42 shows the logic diagram of one such shift register. The logic
diagram is that of IC 74166, which is an eight-bit parallel/serial-in, serial-
out shift register belonging to the TTL family of devices.
The parallel-in or serial-in modes are controlled by a SHIFT/LOAD
input. When the SHIFT/LOAD input is held in the logic HIGH state, the
serial data input AND gates are enabled and the circuit behaves like a
serial-in serial-out shift register. When the SHIFT/LOAD input is held in
the logic LOW state, parallel data input AND gates are enabled and data
are loaded in parallel, in synchronism with the next clock pulse. Clocking
is accomplished on the LOW-to-HIGH transition of the clock pulse via
a two-input NOR gate. Holding one of the inputs of the NOR gate in the
logic HIGH state inhibits the clock applied to the other input. Holding an
input in the logic LOW state enables the clock to be applied to the other
input. An active LOW CLEAR input overrides all the inputs, including
the clock, and resets all flip-flops to the logic ‗0‘ state. The timing
waveforms shown in Fig.6.43 explain both serial-in, serial-out as well as
parallel-in, serial-out operations.

6.21.4 Parallel-In Parallel-Out Shift Register

The hardware of a parallel-in parallel-out shift register is similar to that of
a parallel-in serial-out shift register. If in a parallel-in serial-out shift
register the outputs of different flip-flops are brought out, it becomes a
parallel-in parallel-out shift register. In fact, the logic diagram of a
parallel-in parallel-out shift register is similar to that of a parallel-in
serial-out shift register. As an example, IC 74199 is an eight-bit parallel-
in parallel-out shift register. Fig.6.44 shows its logic diagram. We can
see that the logic diagram of IC 74199 is similar to that of IC 74166
mentioned in the previous section, except that in the case of the former
the flip-flop outputs have been brought out on the IC terminals.

6.21.5 Bidirectional Shift Register

A bidirectional shift register allows shifting of data either to the left or to
the right. This is made possible with the inclusion of some gating logic
having a control input. The control input allows shifting of data either to
the left or to the right, depending upon its logic status.

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Fig.6.42 Logic diagram of 74166.

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Fig.6.43 Timing waveforms of IC 74166.

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Fig.6.44 Logic diagram of IC 74199.

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6.21.6 Universal Shift Register
A universal shift register can be made to function as any of the four types
of register discussed in previous sections. That is, it has serial/parallel
data input and output capability, which means that it can function as
serial-in serial-out, serial-in parallel-out, parallel-in serial out and
parallel-in parallel-out shift registers.

6.22 Memories and Processors

6.22.1 Memory Terminology

We will not discuss the topic of data storage technologies per sec. We are
mostly interested here in the question of how data storage can be
effectively organized. The important common element of the memories
we will study is that they are random access memories, or RAM. This
means that each bit of information can be individually stored or retrieved
| with a valid input address. This is to be contrasted with sequential
memories in which bits must be stored or retrieved in a particular
sequence, for example with data storage on magnetic tape. Unfortunately
the term RAM has come to have a more specific meaning: A memory for
which bits can both be easily stored or retrieved ("written to" or "read
from"). Here is a rundown on some terms:
_ RAM. In general, refers to random access memory. All of the devices
we are considering to be "memories" (RAM, ROM, etc.) are random
access. The term RAM has also come to mean memory which can be both
easily written to and read from. There are two main technologies used for
RAM:
1.) Static RAM. These essentially are arrays of flip-flops. They can be
fabricated
in ICs as large arrays of tint flip-flops.) "SRAM" is intrinsically
somewhat faster than dynamic RAM.
2.) Dynamic RAM. Uses capacitor arrays. Charge put on a capacitor will
produce a HIGH bit if its voltage V = Q/C exceeds the threshold for the
logic standard in use. Since the charge will "leak" off through the
resistance of the connections in times of order ≈ 1 m sec, the stored
information must be continuously refreshed (hence the term "dynamic").
Dynamic RAM can be fabricated with more bits per unit area in an IC
than static RAM. Hence, it is usually the technology of choice for most
large-scale IC memories.
- ROM. Read-only memory. Information cannot be easily stored. The idea
is that bits are initially defined and are never changed thereafter. As an
example, it is generally prudent for the instructions used to initialize a

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computer upon initial power-up to be stored in ROM. The following
terms refer to versions of ROM for which the stored bits can be over-
written, but not easily.
_ PROM. Programmable ROM. Bits can be set on a programming bench
by burning "fusible links," or equivalent. This technology is also used for
programmable array logic (PALs), which we will briefly discuss in class.
_ EPROM. ROM which can be erased using ultraviolet light.
_ EEPROM. ROM which can be erased electronically. A few other points
of terminology:
- As you know, a bit is a binary digit. It represents the smallest element of
information.
_ A byte is 8 bits. _ A "K" of memory is 210 = 1024 bits (sometimes
written KB). And a megabit (MB) is 1K x 1K bits.
- RAM is organized into many data \words" of some prescribed length.
For example, a RAM which has 8K = 8192 memory locations, with each
location storing a data word of "width" 16 bits, would be referred to as a
RAM of size 8K x 16. The total storage capacity of this memory would
therefore be 128KB, or simply a "128K" memory.
(With modern very large scale integration (VLSI) technology, a typical
RAM IC might be ≈ 16 MB.
- Besides the memory "size," the other important specification for
memory is the access time. This is the time delay between when a valid
request for stored data is sent to a memory and when the corresponding
bit of data appears at the output. A typical access time, depending upon
the technology of the memory, might be ≈ 10 ns.

6.22.2 Memory Configuration

As stated above, the term 'memory" refers to a particular way of
organizing information by random access | which is distinct from the less
specific term "data storage." Fig.6.45 shows how an 8-bit RAM (8 x 1) is
organized. (This is a very small memory, but illustrates the concepts.)
Our RAM consists of three main components: an 8-bit multiplexer, an 8-
bit demultiplexer, and 8 bits of storage. The storage shown consists of
edge-triggered D-type flip-flops. Hence, this is evidently a \static RAM."
(There is no fundamental reason for using edge-triggered flip-flops. They
could just as easily be level-triggered, like the simple "clocked" S-R flip-
flop of Fig. 6.45.)

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 Fig. 6.45. An 8 x 1 bit RAM.

6.22.3 Generalization to Microprocessors

A state machine with zero input bits can perform a counter-like function,
but not more: its next state is limited to be a function only of the present
state. A single input bit can be used to "program" the state machine to
behave in one of two possible ways for each present state, as we
discussed, for example, with the up/down counter, or the example in the
preceeding section. On the other hand, with n inputs, the machine can
perform 2n different operations. So, for example, with n = 8 the machine
can perform one of 256 different operations on each clock cycle. This
tremendous potential and flexibility. The input bits can themselves be
sequenced | stored externally in a specific sequence which is then applied
step by step to the state machine inputs on successive clock cycles. Such
a stored sequence of operations is a program and the 256 operations
represent the programming operations. In Fig.6.46we have essentially
configured a simple microprocessor (Figs.6.46 to 49). The inputs and
outputs would need to be connected to buses (via 3-state buffers where
appropriate), which in turn are also connected to memories which store
the program and any output or input data. The buses would also be
connected to various input/output devices, mass storage devices, etc.

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Fig.6.46

Fig.6.47

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Fig.6.48

Fig.6.9

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References
-Millman .J. and Halkias, C.C. " Integrated Electronics" Graw-
Hill company , 2005
-A.Sedra and Smith " Microelectronic circuits- fifth Edition ,
Oxford University press,Inc.2004.
- Collin, R.E , Foundation for Microwave Engineering, "Gunn
diode - Oscillator" Mc.Graw-Hill Book Company 2003.
-Saber.M.A "Analog and digital Signal processing" Dar –al
Nashr for universities. PP 1- 472 2003.
- Saber.M.A "Communication Electronics in Audios and
Videos PP 1- 410 , Dar –al Nashr for universities. 2003.
- Saber.M.A " Microwave Solid States, PP 1- 430 , Nashr for
universities. 2003.

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