IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO.
3, MARCH 2012
A Fully-Integrated High-Power Linear CMOS
Power Amplifier With a Parallel-Series
Combining Transformer
Jihwan Kim, Member, IEEE, Woonyun Kim, Member, IEEE, Hamhee Jeon, Student Member, IEEE,
Yan-Yu Huang, Member, IEEE, Youngchang Yoon, Member, IEEE, Hyungwook Kim, Member, IEEE,
Chang-Ho Lee, Senior Member, IEEE, and Kevin T. Kornegay, Senior Member, IEEE
Abstract—In this paper, a linear CMOS power amplifier (PA)
with high output power (34-dBm saturated output power) for
high data-rate mobile applications is introduced. The PA incor-
porates a parallel combination of four differential PA cores to
generate high output power with good efficiency and linearity.
To implement an efficient on-chip power combiner in a small
form-factor, we propose a parallel-series combining transformer
(PSCT), which mitigates drawbacks and limitations of conven-
tional power-combining transformers such as a series combining
transformer (SCT) and a parallel combining transformer (PCT).
Using the proposed PSCT, a two-stage class-AB PA is designed
and fabricated in a 0.18- m CMOS technology. The PA achieves a
of 31.5 dBm, a of 34 dBm, and a of 23.5 dBm
with a peak PAE of 34.9% (peak drain efficiency of 41%) at
the operating frequency of 2.4 GHz. A detailed analysis of the
proposed PSCT is introduced along with comparisons to the
conventional monolithic power-combining transformers. A design
methodology of the integrated CMOS PA is also presented.
Index Terms—CMOS, high power, parallel combining, power
amplifier, power-combining, series combining, transformer,
WiMAX.
I. INTRODUCTION
C MOS PAs have been gaining increasing interests from the
wireless communication IC industry due to their low de-
velopment cost and potential suitability for integration with sil-
icon transceivers. From early generations of cellular applications
(e.g., GSM/GPRS) to high data-rate applications with moderate
transmission power levels (e.g., IEEE 802.11 a/g/n WLAN),
the territory of applications for CMOS PAs has been rapidly
Manuscript received May 31, 2011; revised December 05, 2011; accepted De-
cember 06, 2011. Date of publication February 06, 2012; date of current version
February 23, 2012. This paper was approved by Associate Editor Jan Craninckx.
J. Kim and Y.-Y. Huang were with the Georgia Electronics Design Center,
Georgia Institute of Technology, Atlanta, GA 30332 USA, and are now with
Intel Corporation, Hillsboro, OR 97124 USA (e-mail: jihwan.kim@intel.com).
H. Jeon was with the Georgia Electronics Design Center, Georgia Institute of
Technology, Atlanta, GA 30332 USA, and is now with TriQuint Semiconductor,
Hillsboro, OR 97124 USA.
W. Kim, Y. Yoon, and C.-H. Lee were with the Georgia Electronics Design
Center, Georgia Institute of Technology, Atlanta, GA 30332 USA, and are now
with Qualcomm Inc., San Diego, CA 92121 USA.
H. Kim was with the Georgia Electronics Design Center, Georgia Institute of
Technology, Atlanta, GA 30332 USA, and is now with Qualcomm Inc., Santa
Clara, CA 95051 USA.
K. T. Kornegay is with the Georgia Electronics Design Center, Georgia In-
stitute of Technology, Atlanta, GA 30332 USA.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2011.2180977
0018-9200/$31.00 © 2012 IEEE
Authorized licensed use limited to: ETH BIBLIOTHEK ZURICH. Downloaded on October 12,2020 at 10:34:53 UTC from IEEE Xplore. Restrictions apply.
599
expanded with help of novel design techniques that overcome
diverse issues and challenges of the silicon CMOS technology
[1]–[9]. Recently, CMOS PAs have even demonstrated their
suitability for more advanced wireless communication standards
such as 4G WiMAX, showing good achievements in output
power, efficiency, and linearity [10]–[14]. However, it is still
challenging to implement fully-integrated high-performance
CMOS PAs that can compete with PAs implemented in III-V
compound semiconductor technologies (e.g., GaAs/InP/InGaP),
thus more sophisticated design techniques are required.
In PA designs for high data-rate mobile communications,
it is of fundamental importance to reach high output power
level maintaining good power efficiency and linearity. Due to
a high peak-to-average power ratio (PAPR) of OFDM-based
modulation schemes, an average output power level of PAs must
be backed off from the peak output power level by a significant
amount. With considerations of non-ideality of CMOS PAs in
terms of AM-AM and AM-PM distortions (which are caused
by nonlinear device capacitances, output resistances, and/or
transconductances), the amount of power back-off must be
around 8 dB to preserve the integrity of the modulated signal [8],
[13], [14]. Therefore, a flat gain-response of the PA up to 30 to
31 dBm (i.e., output referred of greater than 30 dBm) is
required to meet linearity specifications at the average output
power level of around 23 dBm in a long-range mobile communi-
cation environment such as WiMAX. If a margin for additional
losses due to a front-end switch and an antenna is taken into
account, the required output power level is further increased.
To implement such high-power PAs in a CMOS technology
maintaining good power efficiency and linearity, power-com-
bining techniques have been widely used to mitigate design is-
sues caused by intrinsic nonlinear characteristics of MOSFET
devices and/or poor performance of passive devices in silicon
technology [3], [4]. Specifically, the necessity of using an exces-
sively large single PA core cell requiring a small load impedance
value can be avoided by assembling smaller sub-PA cells in par-
allel, which leads to less parasitic issues to handle and reduced
loss at the output matching network (or the power combiner)
due to lower impedance transformation ratio. The key question
is then how we can implement the low-loss monolithic power
combiner in a small form-factor that can be easily integrated
with the parallel PA cores in a CMOS technology.
In recent years, transformer-based power combiners have at-
tained particular attention for implementations of single-chip
600 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 3, MARCH 2012

Fig. 1. Equivalent circuit models of the conventional power-combining transformers. (a) SCT. (b) PCT.

high-power CMOS PAs. [5]–[11]. Two different types of mono-
lithic power-combining transformers that have been success-
fully used thus far are series combining transformers (SCTs)
[5]–[8] and parallel combining transformers (PCTs) [9]–[11].
Although the reported high-power CMOS PAs using these trans-
formers achieved good performances, there are still design is-
sues and limitations especially when the transformers are used
to combine more than three parallel PAs to generate watt-level
output power. For example, the SCT combining four PAs occu-
pies considerable chip area. Due to its nature of serial connec-
tion in the secondary side, the large size tends to cause higher
loss. The PCT with four primary inductors is not feasible to
physically implement because even distribution of the magnetic
coupling and the inductances among multiple primary inductors
coupled to a shared secondary inductor is difficult to achieve.
In this paper, we propose a hybrid-type power-combining
transformer that mitigates the design limitations of the con-
ventional transformers. We investigate the characteristics of the

Authorized licensed use limited to: ETH BIBLIOTHEK ZURICH. Downloaded on October 12,2020 at 10:34:53 UTC from IEEE Xplore. Restrictions apply.
KIM et al.: A FULLY-INTEGRATED HIGH-POWER LINEAR CMOS POWER AMPLIFIER WITH A PARALLEL-SERIES COMBINING TRANSFORMER 601

Fig. 2. Analyzed characteristics of the SCT and the PCT. (a) Efficiency of the SCT with and varying . (b) Efficiency of the PCT with and varying
. (c) Efficiency of the SCT with and varying . (d) Efficiency of the PCT with and varying . (e) with , and varying
. (b) with , and varying .

SCT and the PCT focusing on the impedance transformation
ratio, the efficiency, and the power transmission capability, and
show that the proposed transformer is an appropriate solution
for integration with four parallel PA cores to generate 33 dBm
combined output power. A two-stage class-AB CMOS PA with
the proposed power-combining technique for WiMAX appli-
cations is designed and demonstrated. This paper is organized
as follows. In Section II, the conventional power-combining
transformers are analyzed and compared from the perspective
of a high-power PA design. The hybrid-type power-combining

Authorized licensed use limited to: ETH BIBLIOTHEK ZURICH. Downloaded on October 12,2020 at 10:34:53 UTC from IEEE Xplore. Restrictions apply.
602 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 3, MARCH 2012

transformer, a parallel-series combining transformer (PSCT), is where

introduced in Section III along with analysis on its characteris-
(4)
tics and comparisons to other types of power-combining trans-
formers. Section IV presents a design example of the PSCT- The input current at each primary inductor ( ) of the SCT is
based high-power CMOS PA in detail. Measurement results and derived from (4) as
conclusions are described in Sections V and VI, respectively.
(5)
II. CONVENTIONAL POWER-COMBINING TRANSFORMERS:
SCTS AND PCTS Thus, we can obtain the equation for the impedance at each input
terminal of the SCT as
A. Characteristics of Power-Combining Transformers
Typical characteristics of the transformer-based power com-
biners can be represented by their transformed input impedance
and efficiency. Design equations for these characteristics of the
single-input/single-output transformer were derived in [15] in- (6)
cluding the finite coupling effect and frequency dependency. For the PCT shown in Fig. 1(b), the same approach can be
We can further extend its derivation to obtain equations for the used to derive as follows:
transformed input impedance ( ) and the efficiency ( ) of the
multi-input/single-output transformers (e.g., the SCT and the (7)
PCT). In equivalent models shown in Fig. 1 [11], [16], , , (8)
and can be functions of and (turn ratio) if we set
(quality factor) values for the primary and the secondary induc- (9)
tors to a constant value (i.e., , , and
). Assuming that the primary and the secondary in- (10)
ductors have same values, the input impedances can be de-
rived from the relation between input currents and voltages in
(11)
both transformers. Setting the impedance of each primary in-
ductor (excluding the mutual inductance) and the secondary in-
ductor of the SCT as
(1)
(2)
(12)
where is the coupling factor between the primary and the sec-
ondary inductors, the input voltage at each primary inductor of Furthermore, using the relation between the primary current
the SCT [in Fig. 1(a)] is given as ( ) and the secondary current ( ), the efficiencies of the SCT
and the PCT can be expressed as (13)–(14), shown at the bottom
(3) of the page, where was substituted by . Therefore, we

(13)

(14)

Authorized licensed use limited to: ETH BIBLIOTHEK ZURICH. Downloaded on October 12,2020 at 10:34:53 UTC from IEEE Xplore. Restrictions apply.
KIM et al.: A FULLY-INTEGRATED HIGH-POWER LINEAR CMOS POWER AMPLIFIER WITH A PARALLEL-SERIES COMBINING TRANSFORMER
Fig. 3. Optimal primary inductance values of the SCT and the PCT with
varying at 2.4 GHz ( , , and ).
can observe the dependency of the input impedance and the effi-
ciency of the power-combining transformers on various design
parameters: the physical turn ratio ( ), the number of primary
input terminals ( ), the coupling factor ( ), the quality factor
( ), and the inductance of the primary inductor ( ). Analyzed
efficiency and input impedance characteristics of the SCT and
the PCT with varying and are presented in Fig. 2 (
and were used for the calculation). When a fixed
is used (e.g., ), both transformers have decreasing effi-
ciencies with increasing at high region (i.e., high op-
erating frequency range if remains constant). Similarly, the
efficiencies of the transformers are degraded as increases for
a fixed . This is because the larger or translates to the
larger series resistance to dissipate power. It is interesting to no-
tice that this tendency is not preserved at lower region (or
lower frequency range) due to effects of frequency-dependent
mutual inductances and non-ideal couplings. Therefore, more
careful analysis is required to characterize the performance of
the transformers for the specific number of combining inputs
and the target frequency.
Particularly, the equations for the efficiency provides useful
information if we assume that , , , and values are pre-de-
termined. That is, the optimal value of which maximizes
the efficiencies of both transformers for specific operating fre-
quency can be obtained as
(15)
(16)
Interestingly, the optimal primary inductance value for both
transformers is inversely proportional to , , and , while it
is negligibly affected by and . The calculated for
the SCT and the PCT at the frequency of 2.4 GHz is presented
in Fig. 3.
Authorized licensed use limited to: ETH BIBLIOTHEK ZURICH. Downloaded on October 12,2020 at 10:34:53 UTC from IEEE Xplore. Restrictions apply.
603
B. Power-Combining Transformers for High-Power PA
Designs
In this section, we discuss the performance comparison of the
conventional transformers associated with an actual PA design.
A detailed guideline of choosing the design parameters of the
transformers to combine four parallel PA cores is introduced.
The individual PA core was designed using a 0.18 m CMOS
technology, having a differential cascode structure with 3-mm
and 4-mm total channel widths for the common source (CS)
and the common gate (CG) devices, respectively. The optimal
load impedance was obtained from the load-pull simulation as
at which the individual PA cores can deliver
29-dBm output power with the maximum efficiency. The target
operating frequency is 2.4 GHz.
As presented in Fig. 4, two factors can affect to the overall
power efficiency from the output of the individual PA cores to
the load impedance. The first factor is the passive efficiency ( )
of the impedance-transforming power combiner, and the second
factor is the reflection at the input terminal of the power com-
biner. The performance of the PA cores is maximized only if the
load impedance at the drain ( ) matches . When is
deviated from , a finite fraction of the power out of the
PA cores is not transmitted to the combining network due to the
reflection, degrading the overall efficiency. Therefore, we can
define a power transmission ratio (PTR) of the impedance-trans-
forming power-combining network with -primary input ter-
minals to calculate the effective overall efficiency within the
parallel PA system as
(17)
where the reflection coefficient, , at each input terminal is
(18)
This PTR can be a useful parameter that indicates power trans-
mission capability of power-combining transformers integrated
with PA core amplifiers although it includes the effect of spec-
ified load impedance. Thus, more careful design of different
types of the transformers is possible using the PTR for the given
as well as .
The turn ratio, , of the transformers can be determined
using (6) and (12). Since and
, we can set for the SCT
and for the PCT to have for both
transformers which is close to . Variations
of and PTR with different values of for the SCT
and the PCT are presented in Fig. 5. For both transformers,
the highest PTR around the target frequency of 2.4 GHz is
achieved with of about 1 nH that is close to the value
obtained from (15) for the SCT. However, the PCT has a little
smaller maximizing the PTR than the value maximizing
the efficiency ( nH obtained from (16)). This is
because at 2.4 GHz with of 1 nH is closer to
than one with of 1.4 nH, which brings less reflection
and higher PTR. It is observed that the SCT outperforms the
604 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 3, MARCH 2012

Fig. 4. Efficiency degradation factors in a parallel-combined PA structure.

PCT from the PTR perspective for the combination of four

parallel PA cores. This can be explained by the fact that the
PCT requires a higher ( ) to generate the target input
impedance with . While the total series resistance at
the secondary side of the SCT is , that of
the PCT is . Therefore, the SCT seems to be
a reasonable choice as a power combiner in designing the
PA system combining four parallel PA cores. However, the
considerable design issue for the SCT is its large size which
puts limitation on the implementation of a fully-integrated
PA (e.g., four secondary inductors need to be placed side by
side). Furthermore, the efficiency (or PTR) of the SCT has
room for further improvement.

III. PARALLEL-SERIES COMBINING TRANSFORMER (PSCT)

We propose a hybrid-type power combining transformer that
takes merits of the SCT and the PCT. The proposed parallel-se-
ries combining transformer (PSCT) performs the parallel (or
current) and the series (or voltage) combining simultaneously
in a single structure, enabling the implementation of the power-
combining transformer in a smaller form-factor compared to the
SCT (i.e., almost a half size in the outer dimension). Moreover,
the mutual inductance at the primary side in the PSCT is in-
creased due to additional coupling between adjacent primary
inductors, leading to improved efficiency and PTR (Note that
this is a merit of the PCT for the limited number of the parallel
combining inputs).

A. Characteristics of the PSCT

The structure of the general PSCT and its equivalent circuit
Fig. 5. Calculated PTR of the SCT and the PCT. (a) with , model are presented in Fig. 6. There are -primary inductors
and varying . (b) with , and varying . that are coupled to one secondary inductor (i.e., -parallel-

Authorized licensed use limited to: ETH BIBLIOTHEK ZURICH. Downloaded on October 12,2020 at 10:34:53 UTC from IEEE Xplore. Restrictions apply.
KIM et al.: A FULLY-INTEGRATED HIGH-POWER LINEAR CMOS POWER AMPLIFIER WITH A PARALLEL-SERIES COMBINING TRANSFORMER 605

Fig. 6. Proposed PSCT. (a) Schematic diagram. (b) Equivalent circuit.

combining) and -sets of -parallel-combining parts con- -primary inductors share one secondary inductor, the phys-
nected in series (i.e., -series-combining). Thus, the number ical implementation of the PSCT can occupy smaller chip area
of the total combining inputs in the PSCT is . Since compared to the SCT for the same number of total combining

Authorized licensed use limited to: ETH BIBLIOTHEK ZURICH. Downloaded on October 12,2020 at 10:34:53 UTC from IEEE Xplore. Restrictions apply.
606 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 3, MARCH 2012

Fig. 7. Analyzed characteristics of the PSCT. (a) Efficiency with and varying . (b) Efficiency with and varying . (c) with ,
, and varying . (d) PTR with , , and varying .

inputs ( ). From the equivalent circuit shown in Fig. 6(b), the If the finite coupling effect and the frequency-dependent mutual
input impedance of the PSCT can be derived using the approach inductance are ignored, the input impedance of the PCT can be
taken in Section II as follows: simplified as

(25)

(19)
Interestingly, the input impedance (hence the impedance trans-
(20) formation ratio) of the PSCT is negligibly affected by the
number of combining inputs if the number of series and parallel
(21) combining parts are same (i.e., if
), which brings more flexibilities to implementation
of the transformer.
The efficiency and the optimal primary inductance value of
(22) the PSCT can be derived as shown in (26)–(28) at the bottom
(23) of the next page. The calculated efficiencies of the PSCT with
varying and (with and ) are presented in
Fig. 7(a) and (b). Only two cases of and are
considered when a fixed is used to ensure that .
The PSCT shows less sensitivity in the efficiency to increasing
(24) compared to the SCT or the PCT. The input impedance and
the PTR of the PSCT with varying are also presented in

Authorized licensed use limited to: ETH BIBLIOTHEK ZURICH. Downloaded on October 12,2020 at 10:34:53 UTC from IEEE Xplore. Restrictions apply.
KIM et al.: A FULLY-INTEGRATED HIGH-POWER LINEAR CMOS POWER AMPLIFIER WITH A PARALLEL-SERIES COMBINING TRANSFORMER 607

used for the comparison. The efficiency of the PSCT at 2.4 GHz
is 68% which is slightly lower than that of the SCT (71.5%),
but higher than that of the PCT (59.4%). However, the PTR of
the PSCT is 2.5, which is higher than that of the SCT (2.4) and
the PCT (2.15) at 2.4 GHz. The reason why the is
higher than the is because the real part of the input
impedance of the PSCT ( )
is larger than that of the SCT ( ),
which causes less reflection for the given . As men-
tioned in the previous section, however, the PTR indicates
how efficiently the transformer is incorporated with parallel
PA cores, but does not represent the pure efficiency of the
transformer itself. Designers have to determine proper de-
sign parameters of the transformer considering the efficiency
and the PTR for given which depends on the size
of the PA core cell and parasitic elements associated with it.
It must be noted that the previous analysis of efficiency for
the PCT and PSCT did not take into account the additional cou-
pling effect between adjacent primary inductors. As shown in
Fig. 9, in reality, the effective coupling factor in the parallel
combining sections is increased due to the additional coupling,
. The increased mutual inductance and the decreased leakage
inductance due to boosted coupling factor ( ) lead to im-
provement in overall efficiency at the lower frequency range
((27)). By the EM simulation, the mutual inductance at the pri-
mary side of the PSCT was found to be 10.7% larger than that
of the SCT. With modified mutual/leakage inductance values for
the PSCT, the efficiencies of the SCT and the PSCT are com-
pared in Fig. 9(c). Therefore, the proposed 4-primary PSCT can
achieve similar or better efficiency and PTR compared to the
Fig. 8. Comparison of the SCT, the PCT, and the PSCT. (a) Efficiency. (b) PTR 4-primary SCT with significantly reduced physical size.
for .
B. Implementation of the PSCT
Fig. 7(c) and (d). The turn ratio of was selected to trans- The implemented 4-primary 1:2 PSCT (i.e., and
form to the value close to . The PTR for the PSCT ) is illustrated in Fig. 10. The PSCT is composed of two
also depends on the value of , and reaches a maximum value PCTs that have two primary inductors interwoven to the sec-
with nH at the frequency of 2.4 GHz. ondary inductor with a turn ratio of . Then, these two PCTs
The comparison in the passive efficiency and the PTR of are connected in series by the secondary inductors. Thus, the
the SCT ( ), the PCT ( ), and the PSCT ( ) transformer exhibits a series-combining of two parallel-com-
with four input terminals ( ) are presented in Fig. 8. The bining parts (i.e., ) with the total combining
primary inductance of nH for all three transformers are inputs of . The size (outer dimension) of the primary

(26)

(27)

(28)

Authorized licensed use limited to: ETH BIBLIOTHEK ZURICH. Downloaded on October 12,2020 at 10:34:53 UTC from IEEE Xplore. Restrictions apply.
608 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 3, MARCH 2012

Fig. 9. (a) Coupling between adjacent primary inductors in the PCT. (b) Equivalent circuit of the 2-primary PCT accounting for the coupling between adjacent
primary inductors. (c) Calculated efficiencies of the SCT and PSCT with modified mutual inductance for the PSCT.

Fig. 10. Implementation of the proposed 4-primary 1:2 PSCT. (a) Conceptual diagram. (b) Actual layout.

Authorized licensed use limited to: ETH BIBLIOTHEK ZURICH. Downloaded on October 12,2020 at 10:34:53 UTC from IEEE Xplore. Restrictions apply.
KIM et al.: A FULLY-INTEGRATED HIGH-POWER LINEAR CMOS POWER AMPLIFIER WITH A PARALLEL-SERIES COMBINING TRANSFORMER 609

Fig. 11. Size comparison between the proposed PSCT and the conventional SCT. (a) PSCT ( , ). (b) SCT ( , ).

inductors was determined to realize the self inductance ( )

of 1 nH. of 1 nH was chosen for this design rather than
1.2 nH as in the analysis because the primary inductors can be
implemented in reduced size with only 0.05-reduction in the
PTR. Since the transformer was implemented using two thick
metals (4- m-thick aluminum and 3- m-thick copper) that are
connected through whole via trace as presented in Fig. 10(b),
high- winding inductors can be realized. The width of the in-
ductor metal traces (30 m) was chosen in order for DC cur-
rents, feeding the drain of the PA cores through the center tap,
to meet electromigration rules. The EM simulation shows that
each primary inductor and the secondary inductor have the self
inductance of 0.93 nH and 3.17 nH with the of 13.2 and 17.9
at 2.4 GHz, respectively. The simulated coupling factor and the
mutual inductance at 2.4 GHz are 0.71 and 1.1 nH, respectively,
and the size of the PSCT is 1.43 0.58 mm .
The conventional 4-primary 1:1 SCT was also implemented
and EM-simulated for a comparison. Layouts of the PSCT and
the SCT with 4-primary inputs are illustrated in Fig. 11. The
size of the SCT (2.72 0.55 mm ) is almost twice of that of
the PSCT while having the self inductance of the primary and
the secondary inductors of 0.95 and 4.4 nH, respectively. The
EM simulated insertion loss and the PTR of these transformers
are compared in Fig. 12. While the SCT has the insertion loss
of 0.85 dB and the PTR of 2.75, the PSCT achieves the
lower insertion loss of 0.73 dB and the higher PTR of 2.9 at
2.4 GHz.

IV. DESIGN OF A PSCT-BASED HIGH-POWER CMOS PA

A. A Structure of the PSCT-Based CMOS PA

Using the proposed PSCT, a fully-integrated PA is imple-
mented in a CMOS technology. The schematic diagram of the
proposed PA structure is presented in Fig. 13. Four PA branches Fig. 12. EM simulated characteristics of the 4-primary PSCT and the SCT.
are combined by the PSCT at the output. The top and bottom (a) Insertion loss. (b) PTR.

Authorized licensed use limited to: ETH BIBLIOTHEK ZURICH. Downloaded on October 12,2020 at 10:34:53 UTC from IEEE Xplore. Restrictions apply.
610
Fig. 13. Simplified schematic diagram of the designed PSCT-based CMOS PA.
adjacent PA branches are combined in parallel (i.e., output AC
currents are combined), and two sets of the parallel combining
parts are connected in series (i.e., output AC voltages are com-
bined). The PSCT performs not only the power combining, but
also the impedance down-transformation. Thus, no additional
output matching networks are required (except for shunt capac-
itors to tune out the reactive component at the drain node of
the sub-PAs). The entire PA system consists of a driver stage
and a combined power stage that are interconnected by an LC
matching network in between. An on-chip transformer as an
input balun is used along with matching capacitors to convert
a single-ended external signal to a differential internal signal.
B. Circuit Design
The driver and the power stage amplifiers are pseudo differ-
ential amplifiers with a cascode configuration. The thick gate-
oxide transistors ( m) are used for CG devices ( )
in the driver and the power stage amplifiers to avoid the de-
vice breakdown issues. The width of the CS devices ( ) in
the power stage amplifiers is 3072 m (384 fingers with the unit
finger width of 8 m). This device size was chosen through the
load-pull simulation in the Agilent ADS in such a way that each
power-cell can generate the maximum output power of 28 to
29 dBm with high efficiency. The size of the CG devices in the
power stage amplifiers is 3936 m (492 fingers with the unit
finger width of 8 m). Because four power-cells are combined
in parallel, the effective cell size of the entire power stage be-
comes 12.288 mm (3072 m 4). The cell size of the driver
stage is determined in a way that the output power of the driver
stage amplifier is not compressed before the output power of
the entire power stage starts to be compressed. Considering the
gain of the combined power stage, a minimum level of the
Authorized licensed use limited to: ETH BIBLIOTHEK ZURICH. Downloaded on October 12,2020 at 10:34:53 UTC from IEEE Xplore. Restrictions apply.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 3, MARCH 2012
driver stage amplifier can be obtained, and the size of one-fifth
of the entire power stage (2560 m, 321 fingers with the unit
finger width of 8 m) was chosen for the driver stage ampli-
fier in this design. Multiple bonding-wires are used to ground
the source of the driver and the power stage amplifiers to min-
imize the effect of wire inductance and resistance. To reduce
the second-order distortion, large bypass capacitors ( )
are used to connect the center-tap of the primary windings of
the PSCT to the source of each power stage amplifiers. Each
cascode differential amplifier has a resistive feedback network
from the drain of the CG devices to the gate of the CS de-
vices to improve the AM-AM characteristic and the stability.
DC supply currents for the driver and the power stages are fed
through the center-tap of the differential inductor or the trans-
former. Since no bonding-wires are included in the matching
network, accurate frequency matching can be realized. The CS
transistors are biased by external voltage source applied to the
gate through large resistors. The power stage amplifiers are bi-
ased at class-AB condition for the good efficiency and the lin-
earity. The driver stage is biased at more close to class-B to
maximize the efficiency. This also expands the gain compres-
sion point of the driver stage amplifier, which compensates for
the gain compression of the power stage amplifiers. Expanded
gain (or better AM-AM characteristic) is beneficial to have the
better EVM performance for the entire PA system.
V. MEASUREMENT RESULTS
The high-power linear CMOS PA has been fabricated in a
0.18- m CMOS (IBM 1P6M) technology. A microphotograph
of the fabricated PA is presented in Fig. 14. The size of the
PA is 2.1 1.64 mm . The PA chip was mounted on the FR-4
PCB for measurements. The PCB line loss (0.3 dB) was de-em-
bedded to obtain actual PA performances. However, the effects
KIM et al.: A FULLY-INTEGRATED HIGH-POWER LINEAR CMOS POWER AMPLIFIER WITH A PARALLEL-SERIES COMBINING TRANSFORMER 611

Fig. 17. Measured result of the designed PA: -parameters.

Fig. 14. Microphotograph of the fabricated PA (2.1 1.64 mm ).

Fig. 15. Measured result of the designed PA: gain, DE, and PAE at 2.4 GHz.

Fig. 18. Measured result of the designed PA: EVM at 2.4 GHz. (a) For WLAN
Fig. 16. Measured result of the designed PA: gain versus at different 54 Mbps 64-QAM signal. (b) For WiMAX 54 Mbps 64-QAM signal.
frequencies.

for the CG devices improves the AM-AM performance of the

of bonding-wires are included in the measurement results. A PA with a small penalty in the efficiency. The measured gain
gain, a ,a , and a PAE were measured with single-tone and the efficiency of the designed PA at the operating frequency
continuous-wave signal. The gate bias voltages for CS devices in of 2.4 GHz are presented in Fig. 15. The PA achieves a gain of
the driver and the power stage amplifiers are 0.43 V and 0.46 V, 22 dB, a of 31.5 dBm, a of 34 dBm, a PAE of 34.9%,
respectively, at which the overall PA has the highest with and a drain efficiency (DE) of 41%. The gain variation is less than
small gain variations. The gate bias voltages for the CG devices 0.45 dB. The measured gain/ at 2.3 GHz and 2.5 GHz are
in the driver and the power stage amplifiers are chosen to be 21.5 dB/32.5 dBm and 22 dB/29 dBm, respectively, as shown in
3.3 V and 3.2 V, respectively. The relatively higher bias voltage Fig. 16.

Authorized licensed use limited to: ETH BIBLIOTHEK ZURICH. Downloaded on October 12,2020 at 10:34:53 UTC from IEEE Xplore. Restrictions apply.
612 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 3, MARCH 2012

Fig. 19. Measured result of the designed PA: constellation and spectrum at 2.4 GHz. (a) For WLAN 54 Mbps 64-QAM signal ( 23 dBm). (b) For WiMAX
54 Mbps 64-QAM signal ( 19 dBm).

TABLE I
PERFORMANCE COMPARISON OF WATT-LEVEL LINEAR CMOS PAS

The measured -parameters are plotted in Fig. 17. The
achieved input and output return losses ( and ) are better
than 15 dB at 2.4 GHz. The small signal gain ( ) of the
PA is greater than 19 dB from 1.8 to 3.2 GHz (i.e., the 3-dB
bandwidth is 1.4 GHz). The EVM was also measured using the
IEEE 802.11g WLAN OFDM 64-QAM (channel bandwidth
of 20 MHz) and 802.16e WiMAX OFDM 64-QAM (channel
bandwidth of 24 MHz) modulated signals at 2.4 GHz. The PA
meets the WLAN EVM specification ( 25 dB or 5.6%) up to
23.5-dBm output power, and the WiMAX EVM specification
( 31 dB or 2.8%) up to 19.5-dBm output power (Fig. 18).
The measured spectrums and constellations for the WLAN and

Authorized licensed use limited to: ETH BIBLIOTHEK ZURICH. Downloaded on October 12,2020 at 10:34:53 UTC from IEEE Xplore. Restrictions apply.
KIM et al.: A FULLY-INTEGRATED HIGH-POWER LINEAR CMOS POWER AMPLIFIER WITH A PARALLEL-SERIES COMBINING TRANSFORMER
WiMAX signals are presented in Fig. 19. The PA consumes
the idle DC current of 270 mA (30 mA for the driver stage
amplifier and 60 mA for each of power stage amplifier) from
3.3 V supply. The performance of designed PA is compared to
other state-of-the-art linear CMOS PAs in Table I.
VI. CONCLUSION
A hybrid-type power-combining transformer, parallel-series
combining transformer (PSCT), was proposed to implement a
fully-integrated high-power linear CMOS PA for high data-rate
mobile applications. The analysis of the proposed power com-
biner along with comparisons to the conventional transformer-
based power combiners was introduced, showing that the PSCT
is the optimal choice for the combination of four individual
sub-PAs to generate greater than 33-dBm output power. The
fabricated PA achieved a (31.5 dBm), a (34 dBm),
and a peak PAE (34.9%) at the operating frequency of 2.4 GHz.
ACKNOWLEDGMENT
The authors would like to thank T. Y. Cho for support.
REFERENCES
[1] N. Wongkomet, L. Tee, and P. R. Gray, “A 31.5 dBm CMOS RF Do-
herty power amplifier for wireless communications,” IEEE J. Solid-
State Circuits, vol. 41, no. 12, pp. 2852–2859, Dec. 2006.
[2] R. Brama, L. Larcher, A. Mazzanti, and F. Svelto, “A 30.5 dBm 48%
PAE CMOS class-E PA with integrated balun for RF applications,”
IEEE J. Solid-State Circuits, vol. 43, no. 8, pp. 1755–1762, Aug. 2008.
[3] A. Shirvani, D. K. Su, and B. A. Wooley, “A CMOS RF power am-
plifier with parallel amplification for efficient power control,” IEEE J.
Solid-State Circuits, vol. 37, no. 6, pp. 684–693, Jun. 2002.
[4] P. Reynaert and M. Steyaert, “A 2.45-GHz 0.13- m CMOS PA with
parallel amplification,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp.
551–562, Mar. 2007.
[5] I. Aoki, S. Kee, R. Magoon, R. Aparicio, F. Bohn, J. Zachan,
G. Hatcher, D. McClymont, and A. Hajimiri, “A fully-integrated
quad-band GSM/GPRS CMOS power amplifier,” IEEE J. Solid-State
Circuits, vol. 43, no. 12, pp. 2747–2758, Dec. 2008.
[6] G. Liu, P. Haldi, T.-J. K. Liu, and A. M. Niknejad, “Fully integrated
CMOS power amplifier with efficiency enhancement at power backoff,”
IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 600–609, Mar. 2008.
[7] P. Haldi, D. Chowdhury, P. Reynaert, G. Liu, and A. M. Niknejad, “A
5.8 GHz 1 V linear power amplifier using a novel on-chip transformer
power combiner in standard 90 nm CMOS,” IEEE J. Solid-State Cir-
cuits, vol. 43, no. 5, pp. 1054–1063, Mar. 2008.
[8] D. Chowdhury, C. D. Hull, O. B. Degani, Y. Wang, and A. M. Niknejad,
“A fully integrated dual-mode highly linear 2.4 GHz CMOS power
amplifier for 4G WiMAX applications,” IEEE J. Solid-State Circuits,
vol. 44, no. 12, pp. 1054–1063, Dec. 2009.
[9] K. H. An, O. Lee, H. Kim, D. H. Lee, J. Han, K. S. Yang, Y. Kim, J. J.
Chang, W. Woo, C.-H. Lee, H. Kim, and J. Laskar, “Power-combining
transformer techniques for fully-integrated CMOS power amplifiers,”
IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1064–1075, May 2008.
[10] K. H. An, D. H. Lee, O. Lee, H. Kim, J. Han, W. Kim, C. –H. Lee,
H. Kim, and J. Laskar, “A 2.4 GHz fully integrated linear CMOS
power amplifier with discrete power control,” IEEE Microw. Wireless
Compon. Lett., vol. 19, no. 7, pp. 479–481, Jul. 2009.
[11] J. Kim, Y. Yoon, H. Kim, K. H. An, W. Kim, C. -H. Lee, and K. T.
Kornegay, “A linear multi-mode CMOS power amplifier with discrete
resizing and concurrent power combining structure,” IEEE J. Solid-
State Circuits., vol. 46, no. 5, pp. 1034–1048, May 2011.
[12] A. Afsahi, A. Behzad, and L. E. Larson, “A 65 nm CMOS 2.4 GHz 31.5
dBm power amplifier with a distributed LC power-combining network
and improved linearization for WLAN applications,” in IEEE Int. Solid-
State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2010, pp. 452–453.
[13] O. Degani, F. Cossoy, S. Shahaf, E. Cohen, V. Kravtsov, O. Sendik,
D. Chowdhury, C. D. Hull, and S. Ravid, “A 90-nm CMOS power
amplifier for 802.16e (WiMAX) applications,” IEEE Trans. Microw.
Theory Tech., vol. 58, no. 5, pp. 1431–1437, May 2010.
Authorized licensed use limited to: ETH BIBLIOTHEK ZURICH. Downloaded on October 12,2020 at 10:34:53 UTC from IEEE Xplore. Restrictions apply.
613
[14] A. Afsahi and L. E. Larson, “An integrated 33.5 dBm linear 2.4 GHz
power amplifier in 65 nm CMOS for WLAN applications,” in Proc.
IEEE Custom Integrated Circuits Conf. (CICC), 2010, pp. 19–22.
[15] I. Aoki, S. D. Kee, D. B. Rutledge, and A. Hajimiri, “Distributed ac-
tive transformer – A new power-combining and impedance-transfor-
mation technique,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 1,
pp. 316–331, Mar. 2002.
[16] J. Long, “Monolithic transformers for silicon RF IC design,” IEEE J.
Solid-State Circuits, vol. 35, no. 9, pp. 1368–1382, Sep. 2000.
Jihwan Kim (S’07–M’11) received the B.S. degree
in electrical and computer engineering from Hanyang
University, Seoul, Korea in 2005, and the M.S. and
Ph.D. degrees in electrical and computer engineering
from the Georgia Institute of Technology, Atlanta,
GA, in 2007 and 2011, respectively. His doctoral
research focused on design techniques for RF and
mm-wave front-end integrated circuits, including
power amplifiers (PAs), mixers, low-noise amplifiers
(LNAs), and voltage-controlled oscillators (VCOs)
using CMOS/SiGe technologies.
He has worked as an intern at Samsung Design Center, Atlanta, GA, in
2008 designing CMOS LNAs for mobile handset applications and at RF
Micro Devices (RFMD), Torrance, CA, in 2009 designing high-performance
GaAs pHEMT LNAs and PAs for mm-wave applications. Since 2011, he
has been with Intel’s Advanced Design Group, Hillsboro, OR. His current
research interests include analog and mixed-signal integrated circuits designs
for high-speed wireless/wireline data communications.
Woonyun Kim (S’94–M’01) received the B.S.,
M.S., and Ph.D. degrees in electrical and electronics
engineering from Pohang University of Science
and Technology (POSTECH), Pohang, Korea, in
1994, 1996, and 2001, respectively. His doctoral
dissertation focused on the design, modeling, and
fabrication of GaAs- and InP-based HBTs, especially
the linearity of HBTs.
In 2001, he joined Samsung Electronics, Giheung,
Gyeonggi-Do, Korea, where he was involved in the
design and development of RF ICs and RF tuners.
From 2007 and 2009, he was a member of the research staff at the Georgia
Institute of Technology, Atlanta, GA. In 2011, he joined Qualcomm, San Diego,
CA. His research interests include RF/analog circuits for wireless applications.
Hamhee Jeon (S’09) received the B.S. degree in
electrical engineering from Kwangwoon University,
Seoul, Korea, in 2006, and the M.S. degree in elec-
trical and computer engineering from the Georgia
Institute of Technology, Atlanta, in 2009, where he
is currently working toward the Ph.D. degree.
His major research interests include CMOS RF
power amplifiers, RF front-end circuits, analog in-
tegrated circuits, and the implementation of passive
circuits on silicon substrate and integrated passive
devices (IPDs).
Yan-Yu Huang (S’09–M’11) received the B.S.
degree in electrical engineering from National
Tsing Hua University, Hsinchu, Taiwan, in 2006,
and the M.S. and Ph.D. degrees in electrical and
computer engineering from the Georgia Institute of
Technology, Atlanta, in 2009 and 2011, respectively.
He is currently with Intel’s Advanced Design
Group, Hillsboro, OR. His major research interests
are analog/RF tunable circuits design, such as vari-
able attenuators, variable gain amplifiers and phase
shifters using bulk CMOS process.
614
Youngchang Yoon (S’07) received the B.S. and M.S.
degrees in electrical engineering from Seoul National
University, Seoul, Korea, in 2005 and 2007, respec-
tively, and the Ph.D. degree in electrical and com-
puter engineering from the Georgia Institute of Tech-
nology, Atlanta, GA, in 2011. His doctoral research
focused on RF front-end circuits for multi-standard
and multi-band operations, especially highly efficient
linear CMOS RF power amplifiers.
In 2008 and 2010, he was an intern at Samsung
Design Center, Atlanta, where he worked as an RFIC
designer to develop a CMOS RF power amplifier for mobile handset applica-
tions. Since 2011, he has been with Qualcomm Inc., San Diego, CA. His re-
search interests include CMOS RF transceivers and power amplifier design for
wireless communication
Hyungwook Kim (S’06) received the B.S. degree
in physics education and M.S. degree in electronics
engineering from Seoul National University, Seoul,
Korea, in 1994 and 1996, respectively, and the Ph.D.
degree in electrical and computer engineering from
the Georgia Institute of Technology, Atlanta, in 2011.
From 1996 to 2003, he was a senior research
engineer with LG Electronics, Seoul, Korea, where
he was involved in the design and fabrication of
GaAs-based electronic devices and the development
of power amplifier for CDMA application. In 2010,
he held an internship position at Qualcomm, San Diego, CA, and since 2011,
he has been with Qualcomm Incorporated, Santa Clara, CA. His major research
interests include RF CMOS device modeling, CMOS RF transceivers and
power amplifier design for wireless communication.
Chang-Ho Lee (S’97–M’01–SM’06) received the
B.S. and M.S. degrees in electrical engineering
from Korea University, Seoul, Korea, in 1989 and
1991, respectively, and the M.S. and Ph.D. degrees
in electrical and computer engineering from the
Georgia Institute of Technology, Atlanta, GA, in
1999 and 2001, respectively.
In 2000, he joined RF Solutions, Inc., Norcross,
GA, where he was a staff engineer. In 2003, he joined
the Georgia Institute of Technology, Atlanta, GA, as
a research faculty. In 2005, he joined Samsung De-
sign Center, Atlanta, GA, where he was a technical director, as well as an ad-
junct professor at the Georgia Institute of Technology. Since 2011, he has been
a principal engineer with Qualcomm, San Diego, CA, working on RFIC design.
He has more than 150 technical conference presentations and journal publica-
tions, a book publication, and over 80 patents filing in the area of RFIC and
module development.
Dr. Lee has served as a TPC member of IEEE IMS, RFIC, RWS, and ISCAS.
He was a recipient of the third place of the Best Paper Award at 2001 IEEE
IMS, a co-recipient of the finalist of the Best Paper Award at 2003 IEEE IMS,
a co-recipient of the finalist of 2004 ECWT Young Engineer Prize Award, and
a co-recipient of the 2008 APMC Best Paper Competition Award.
Authorized licensed use limited to: ETH BIBLIOTHEK ZURICH. Downloaded on October 12,2020 at 10:34:53 UTC from IEEE Xplore. Restrictions apply.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 3, MARCH 2012
Kevin T. Kornegay (M’91–SM’96) received the
B.S. degree in electrical engineering from Pratt
Institute, Brooklyn, NY, in 1985, and the M.S. and
Ph.D. degrees in electrical engineering from the
University of California at Berkeley in 1990 and
1992, respectively.
From 1998 to 2006, he was an Associate Pro-
fessor in the School of Electrical and Computer
Engineering, Cornell University, Ithaca, NY. He
is presently the Motorola Foundation Associate
Professor in the School of Electrical and Computer
Engineering at the Georgia Institute of Technology, Atlanta, GA. His research
interests include radio frequency and millimeter wave integrated circuit design,
high-speed circuits, and broadband wired and wireless systems design.
Dr. Kornegay serves or has served on the technical program committees of
several international conferences including the IEEE International Solid-State
Circuits Conference, the IEEE Custom Integrated Circuits Conference, and the
Radio Frequency Integrated Circuits Symposium. He is also presently serving
a two-year term on the IEEE Solid-State Circuits AdCom committee. He cur-
rently serves on the editorial board of the IEEE TRANSACTIONS ON CIRCUITS
AND SYSTEMS II and previously served an Editor of IEEE Electron Device Let-
ters and Guest Editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS Special
Issue on the 2004 Compound Semiconductor IC Symposium. He is the recip-
ient of numerous awards, including the National Society of Black Engineers’ Dr.
Janice A. Lumpkin Educator of the Year in 2005, the 2002 Black Engineer of
the Year Award in Higher Education from U.S. Black Engineer and Information
Technology magazine, the NSF CAREER Award, an IBM Faculty Partnership
Award, the National Semiconductor Faculty Development Award, and the Gen-
eral Motors Faculty Fellowship Award. He was also selected as a participant
in the National Academy of Engineering Frontiers of Engineering Symposium,
and the German–American Frontiers of Engineering, where he later served on
the organizing committee. He is a Distinguished Lecturer of the IEEE Electron
Devices Society and a senior member of the IEEE, as well as a member of Eta
Kappa Nu and Tau Beta Pi.