Enabling the Semiconductor
Roadmap from a Multi-Angled
Approach
June 13th, 2019
Steven Welch
Senior Director of Strategy, Advanced Product and Technology
Development, Applied Materials
External Use
Introduction
Steven Welch is currently Senior Director of Strategy for Applied
Materials’ Advanced Product and Technology Development
group. In this role, he is responsible for identifying and synthesizing
key inflections in the longer-term Semiconductor technology
roadmap, as well as enabling disruptive technology development
and business growth strategies to intercept these emerging
opportunities. With over 20 years in the industry, Steven started his
career in 1998 as a photolithography engineer at IBM’s Storage
Systems Division in San Jose, California. Since then, he has held
marketing and strategy leadership positions in KLA-Tencor’s wafer
inspection, Applied Materials’ etch, and ASML’s holistic lithography
businesses. Steven holds a B.S. in Chemistry from Harvey Mudd
College and MA & MBA degrees from the University of
Pennsylvania’s Wharton School of Business.
2 External Use
AGENDA Semiconductor Scaling and Enablers
Logic Scaling Advancements
Memory Advancements to Scale A.I. Big Data
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AGENDA Semiconductor Scaling and Enablers
Logic Scaling Advancements
Memory Advancements to Scale A.I. Big Data
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Market Growth
and Evolution Trillions
of units
A.I.
Big Data
Mobile +
Social Media Billions of units
PC +
Internet 100 Millions of units
Mainframe
Computing 100,000s of units
1988 1998 2008 2018
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Industry’s Old Playbook…
MOORE’S LAW PPAC
105
ENABLED BY
1962
RELATIVE COST/COMPONENT
104 “Classic” 2D
103
1965 PERFORMANCE feature shrinking
102 1970
10
PPAC materials
engineering to
1
1 10 102 103 104 105
POWER AREA-COST drive power and
COMPONENT PER IC performance
Now: Apple A12X Bionic
>10 billion transistors
https://wccftech.com/apple-a12x-10-billion-transistors-performance/
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In the Future…
ENABLED BY
PERFORMANCE
New architectures
New structures / 3D
New materials
PPAC
New ways to shrink
POWER AREA-COST
Advanced packaging
… New industry playbook needed to drive PPAC
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Moore’s Law beyond 5nm Node?
AI compute
Negative capacitance (NC)-FET
3D Memories BEOL new materials & transistors
Adapted from Nature Electronics, V1, August’ 2018, 442–450
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AGENDA Semiconductor Scaling and Enablers
Logic Scaling Advancements
Memory Advancements to Scale A.I. Big Data
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CMOS Scaling and Enablers
65nm 45nm 22/14nm 10/7nm 5/3nm 3nm
Strain High-k Metal Gate New Metal Fill SiGe-Ch.
FinFET taller/ narrower & fewer fins GAA-FET
Source: AMAT, SMC Korea 2019 conference
Intel, 65nm Intel, 45nm Intel, VLSI 2012 Intel, IEDM 2014 Intel, IEDM 2017 IBM, VLSI 2017
Research@Intel press event 2011
New Materials: New metal gate and new contact fill
New Architecture: FinFET to hGAA
Samsung announced GAA 3nm node processor will ship in 2021
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Why Horizontal-GAA Evolutional Change
FinFET hGAA
G
Thinner & Taller Fins SiGe p-Channel G G
better gate control & higher drive current mobility boosting G
xFin xNW
Intel, IEDM 2017 GLOBALFOUNDRIES/IBM, IEDM 2016 IBM, VLSI 2017
Vertically stackable channel (NW/NS) for increased current per area
Similar structures & flows: hGAA vs. FinFET
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hGAA CMOS Initial Demonstrations
Transfer Characteristics Ring Oscillator
H. Mertens, IEDM 2017
Source: IMEC/ Applied Materials, IEDM 2018
Functional CMOS demonstrated – getting ready for ≤3nm-node
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hGAA CMOS – Key Challenges
Parasitic capacitance reduction between sheets
xNW/NS
S/D
epi Epi defects
Inner spacer(low-k)
xGate IBM VLSI-T 2017
Si NW/NS
VT tuning metals
Metal-gate Vt tuning in narrow gaps
Source: AMAT, SMC Korea 2019 conference IBM, IEDM 2017
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Beyond Conventional CMOS (≤2nm)
Ge channel
SiGe PFET NCFET/Ferro (HZO) SpinFET
IEDM 2011
Buried Power Rail APL. 56 665 (1990)
Tunnel FET
(Ru)
2D TMD (MoS2)
2016 ICEEOT Co-integration
(VFET, TFT)
Complementary FET Nature
Nanotechnology 2011
3D integration (M3D)
IMEC, IEDM, 2018
IMEC, IEDM, 2018 VLSI-T 2018
14 External Use Source: AMAT, SMC Korea 2019 conference
Selective Processes – Enabling New Ways to Build Chips
Inherent Selective Selective by Deactivation Selective by Activation
Selective Deposition
ANALOGY: 3D Printing – putting material only
where you want it (materials-enabled not litho)
Selective Removal
ANALOGY: Removing a single weed without
damaging adjacent grass or leaving residue
T. Faraz et al, ECS J. Solid State Sci. Technol. 4(6), N5023-N5032 (2015)
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Scaling Opportunities in the Back-end-of-line Interconnect
BEOL Cu wire resistance (R) Materials-Engineering Solutions:
increasing at smaller geometries due
to: New materials (lowest R at CD)
Inherent bulk conductor resistivity Full-volume metal fills
characteristics Interface management
Trade-off fill volume of high-
conducting vs. cladding materials Length of line
Scattering at surfaces and grain
boundaries Core Metal
…resulting in slower performance and CD at mid height
higher power consumption Cladding
(barrier / liner)
Source: AMAT, IEDM 2018 conference
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Copper Extension Scenarios
Co-optimization of ALD barriers with thinner liners and new fill technology is key to
maximize conductor volume (low line R) and minimize interface resistance (low via R)
17 External Use Source: AMAT, IEDM 2018 conference
New Metals for Resistance Scaling
Co, Ru, Mo better than Cu at CD’s between 10-15nm
Ir better than Cu at CD’s between 15-20nm
Is a barrier or liner required?
How to fill?
Can it be integrated?
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AGENDA Semiconductor Scaling and Enablers
Logic Scaling Advancements
Memory Advancements to Scale A.I. Big Data
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Emerging Memories for Pervasive Data and Compute
3D SRAM
SOT-MRAM
STT-MRAM Ferro DRAM
Capacity
Cost/bit
MIMCAP STT-MRAM
Speed
3D SCM 3D DRAM
3D FeFET
More 3D NAND
Molecular Memory
Source: http://www.imec.be from techspot.com (February 21, 2019)
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Architectural Advancements Leveraging Memory & Design
3D Material DRAM & Distributed Analog
Architecture Innovation Packaging Cache Computing
NVIDIA
L2 cache
L1 Cache
Micron.com ElectronicDesign.com (Samsung) NVIDIA Tesla P100 white paper HPE, ACM 2016
Significant investments in memory to
enable better bit scaling and performance
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3D Architectures
3D Material DRAM & Distributed Analog
Architecture Innovation Packaging Cache Computing
NVIDIA
L2 cache
L1 Cache
3D architectures extend memory densities
3DNAND
Source: Intel 2015 S. Kang, IMW2018 tutorial
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3D Architectures
3D Material DRAM & Distributed Analog
Architecture Innovation Packaging Cache Computing
NVIDIA
L2 cache
L1 Cache
Materials and Interfaces
▪ Complex stacks with multiple exotic materials are required to enable new
memories
▪ Deposition, etch and CMP are critical process development areas
Deposition Etch Planarization
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Example of Elements to Enable New Memories
PCM Selector
▪ M-K. Lee, IEDM 2012
▪ G.H. Kim, APL 2012
▪ L. Zhang, IEDM 2014
STT-MRAM
▪ K. Ando, JAP 2014
FE-FET
▪ X. Tian, APL 2018
▪ A. Pal, APL 2017
CBRAM
▪ Adesto Technologies,
IEEE 2013 talk
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DRAM and Packaging
3D Material DRAM & Distributed Analog
Architecture Innovation Packaging Cache Computing
NVIDIA
L2 cache
L1 Cache
Packaging enables higher performance to support more complex workloads
YMTC.com (2018) Nvdia V100 source: techreport.com 2017
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Beyond Chip Scaling: Advanced Packaging
DRAM ON PCB to STACKED DRAM IN PACKAGE HETEROGENEOUS INTEGRATION
3x I/O 14nm
System on Chip
STACKED
STACKED
DRAM
DRAM
to System on
GRAPHICS / IMAGING
CPU CORES
GPU Logic DRAM 10nm
Package
OTHER IP
STACKED
STACKED
DRAM
DRAM
bandwidth
10nm
22nm
performance COMMS
Integration of
14nm
chiplets provides
time, cost and
50%
DRAM (stacked) GPU
SOURCES: Intel,
GLOBALFOUNDRIES yield benefits
Substrate (PCB) Power savings
per bit
Si Interposer SOURCES: AMD, NVIDIA
Connecting chips together in new ways using advanced packaging
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Distributed Cache
3D Material DRAM & Distributed Analog
Architecture Innovation Packaging Cache Computing
NVIDIA
L2 cache
L1 Cache
▪ Distributed computing further reduces memory bottlenecks
SRAM
▪ MRAM alternative to improve area + energy efficiency
6T SRAM 1T, 1 STT-MRAM
Source: techspot.com Source: Intel, IEDM, 2012 Source: AMAT
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Multiple MRAM Milestone Announcements
8/2017 9/2017 7/2018 11/2018 12/2018 12/2018 IEDM conference 3/2019
Everspin Global TSMC Spin Memory Gyrfalcon Intel Samsung Global Samsung
announced Foundries “Over 50 & Applied Technology described the showed Foundries shipped the
sampling of announced customers and Materials announced first FinFET- MRAM showed first 28nm
the world’s availability of 140 tapeout in commercial the based design 22nm eMRAM
first 1Gb embedded N22ULP, agreement to commercial MRAM technology embedded
MRAM MRAM on spanning create a availability of technology co- 40 Mb
product leading many comprehensive its AI ASIC (22nm) is optimization MRAM for
22FDX FD- application embedded that include production for hardware low-power
SOI platform areas… MRAM solution TSMC’s ready neural automotive
connectivity, 22nm networks MCU
digital TV/STB, eMRAM application
application
processors.”
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MRAM Benefits
Low Power & Non-Volatile High Density More Functionality Robust
FinFET SRAM
MRAM Planar SRAM
Source: Everspin.com
CMOS Technology Node (nm)
▪ IMEC DTCO studied: ▪ MRAM is with > 3x cell ▪ MRAM implementation in ▪ MRAM for high temperature,
MRAM write energy < density than SRAM MCU / SoC: low-power operations:
SRAM @ 5MB 45% chip size saving (~ one 22nm embedded 40 Mb
▪ Greater benefit in
MRAM read energy < advanced technology node MRAM could be used
advanced node
SRAM @ 0.4MB advantage) OR between -40 to 150 degrees
1.5-2x more processors at C with good read and write
same chip size characteristics and
immunity to 500 Oersted
magnetic fields.
Source: IMEC, IEDM 2018 Source: SpinMemory.com 2019 Source: Spintec ORaP Forum 2015 Source: GF, IEDM 2018
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MRAM Capability Demonstrated by Optimization of Complex Stack
IEDM, 2015
IEDM, 2016
VLSI, 2018
VLSI, 2018
Sources: Applied Materials
Roadmap for additional density and performance scaling in development
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Digital to Analog Computing
3D Material DRAM & Distributed Analog
Architecture Innovation Packaging Cache Computing
NVIDIA
L2 cache
L1 Cache
Analog vector-matrix multiplier: reduced complexity and
power; will require further advances in process variability
12x12 array, Bell Labs 1986
cited by LeCuin, ISSCC 2019 CAS, IEDM 2017 Tsinghua, IEDM 2017
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Emerging Memory for Machine Learning Accelerators
1. Digital Accelerator 2. Analog Accelerator
SRAM → MRAM available in Foundry eFlash → RERAM, FEFET, PCRAM in Development
In-memory Compute Vector-Matrix Multiplier
NVM
“The 2802M ASIC has 40MB of
eMRAM memory, which can Weights: Conductance of NVM
support large AI models or
multiple AI models within a Matrix multiplication in hardware
(Ohms, Kirchhoff law)
single chip.” – gyrfalcontech.ai
2019
“1,000 to 10,000 better speed-energy efficiency product
than digital ASICs” - HPE, ACM 2016
▪ New analog memories, once performance at scale is
▪ MRAM can enable area benefit at lower power versus robust, can enable additional performance boosts @
traditional distributed SRAM techniques density and new ways of compute
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PPAC Optimization Beyond the Chip
33 External Use Image sources: Applied Materials Blog
