TSV in IC Packaging: Now and Future

Mike Ma, Ph.D.

Vice President, SPIL
 2011

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 2011

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 SEMICON Taiwan : 3DIC Technology Forum 2011-2015
Years 2011 2012 2013 2014 2015
Market Search • Gartner • Yole
• Cisco
• Xilinx • Xilinx
System/ Fabless/ • IBM Research • AMD
• Sony • LSI • Micron
IDM • Innotera • Altera
• Elpida • Aptina
• SK Hynix
•Meisei University
•IMEC
•Tohoku- • IMEC
R&D •Tsukuba Research • LETI
MicroTec
•Fraunhofer IZM
• LETI

•TSMC •UMC •TSMC •ASE •ASE

Foundry/ OSAT
•Powertech •Amkor •Amkor •SPIL •Amkor

•Cadence •Mentor graphic

•Cadence
•Teradyne Optimal Plus
•Cadence •Teradyne
Design/Test/Proc •Verigy •SUSS EVG
•Teradyne • AMAT
ess Tools/ Mat. •Corning SUSS
•Namics •Senju Metal

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So what’s Through Si Via (TSV) 3DIC/ 2.5DIC Adoption Status
1. TSV in CIS : Sony..
2. Low cost TSV in MEMS/Sensor
3. 3D IC with TSV: only in High Band Width (HBM) DRAM
 Hynix, Samsung start HBM-1 LVM in 2015
 HBM-2 in 2016
 Advantage proven, cost still high
4. 2.5D IC with TSV Si Interposer
 Nov. 2010 Xilinx debuted 1st product group (FPGA)
 May. 2015: AMD rolled out 2nd product group (GPU+HBM)
 June. 2016 nVidia GP100 with HBM-2
 Renew interests for high end networking, VR/AR

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 SPIL 2.5DIC Readiness – 20nm FPGAs

40um pitch
ubumps

FPGA FPGA

u-bump

C4-bump

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 SPIL 2.5D IC Readiness – 28nm GPU+ HBM-1x4
DRAM ASIC DRAM

• PKG size 45 x 45 mm2

• ASIC 19 x25 mm2
• Memory 5.5 x 7.3 mm2
• Si Interposer size 33 x27 mm2
C4 joint Micro joint • ASIC Bump Pitch : 45 um
RT TCG1200x Passed HAST 96h Passed HTSL 1008h Passed

uBump
/uPad

C4

UF
height

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 SPIL 2.5D IC Readiness – 16 nm GPU+HBM-2 x4

• Si Interposer size:
25.6 x40.8 mm2
• PKG size 55 x 55 mm2

HBM GPU HBM

u-bump

Cu pillar bump
C4-bump

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 Application: high end logic splits for wafer yield

Source: Dr. Charles Chen, MTK, cited with permission

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 Example for split die to gain yield (cost down)

Source: Dr. Charles Chen, MTK, cited with permission

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 2.5DIC Technology Trend
 TSV Si Interposer size is trending bigger (> field size)

X (mm) 27.3 40.8 31.6 42

Y (mm) 33 25.6 35.58 30
TSI size (mm2) 900.9 1044.48 1124.33 1260
Area ratio 1 1.16 1.25 1.4

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2011

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 2.5DIC Industry Business Models:
I. TSMC Turnkey Model:
I.1 CoWoS (Chip on Wafer (TSI) on Substrate)
I.2 CoW 1st (TSMC) + oS (OSAT)

II. Customer Consign Model

PO •TSI Front Side
Customers IC Fabs +
& Ship to TSV Fine pitch RDL
PO
•TSI Wf baclside
OSATs • bumping
•Assembly Carrier
•CP/ FT
III. OSAT Turnkey Model (ASE+ Innotera, 2014)
PO
PO
Customers OSAT TSI wf by IC fab
Ship to

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 SPIL’s Effort to Reduce 2.5DIC CoO_I: Do Fab’s Job ?!
1.01um M3

0.86um V2

1.04um M2
10.61um
0.88um V1

1.02um M1

1.0um
101.3um TSV
0.9um
1.0um

M3
V2
10.34um

M2
V1

 SPIL R&D demonstrated M1

capability to manufacture entire
TSV
TSV Si interposer (Confab. 2013)

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Confidential
 II. Skip the TSV – NTI (Non TSV Interconnect) or SLIT
• PKG size 45 x45mm2
• NTI size 30.8 x24.8 mm2
• ASIC Bump Pitch = 45 um

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 NTI-2 (Hybrid RDLs; substrate-less) Demo
 PKG size: 15 x 14 mm2
Top Die#1 Top Die#2
MUF  IC ubump-NTI- BGA (substrate-less)
u-bump
2/2 SD  NTI scheme (Line width): 2um (fab tech)/
Via
Via2
5/5 RDL1 5um/ 10um (by bumping RDL)
10/10 RDL2 1
 BGA pitch: 0.4mm
BGA

Top Die

u-bump 2/2 SD
MUF

• Equivalent to Amkor’s SLIM

MUF
(Silicon less integrated module)
2/2 SD
• Fine pitch interconnect still rely
Via
5/5 RDL1 on IC fab to provide
10/10 RDL2

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 2 Carrier

Chip Chip

III. Consolidate the stacking options_CoW Last-M Chip bonding on

interposer &1 stunderfilling
2nd Carrier
1st Underfill

Interposer wafer bumping Compound

Si interposer Chip Chip
process for u-pad
Compound molding &
lapping
2nd Carrier
Interposer wafer bonding
to 1st carrier 1st Carrier *Blade saw for
Chip Chip
molding
2nd carrier de-bonding &
sigulation
BVR process & bumping
for C4 bump 1st Carrier

Chip Chip
1st Carrier Chip module bonding on Si Interposer
substrate & 2 nd underfilling 2nd Underfill
2nd carrier bonding & 1st
Substrate
carrier de-bonding
2nd Carrier

Chip Chip
Chip Chip Heat sink assembly and Si Interposer
Chip bonding on 1st Underfill
ball placement
interposer &1 stunderfilling
Substrate
2nd Carrier

Compound
• KGD stacked on KGI wafer with bonded carrier
Chip Chip
Compound molding &
lapping
• Allow CP to sort out KGD, KGI and chip module b/f assembly
Advantages • Lower
nd
2 Carrier
thermal budget for KGD with three mass reflow due to interposer
Chip
processChip
implementation separated
2nd carrier de-bonding &
sigulation
• Need second carrier-bond request for extra cost
•ChipLaserChipStealth Dicing (SD) yield control for non-molding package risk in
Challenges
Chip module bonding on Sichipping
Interposer and2 crack nd
due to passivation topography and stress of wafer
substrate & 2 nd underfilling Underfill

Substrate

Chip Chip
Heat sink assembly and
ball placement
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Si Interposer
Various Stacking Platform Comparisons (ECTC 2016)

CioS CoCi CoWi_first CoWi_last

Testing for KGI
Possible
IC-TSI Joint Risks
-Warpage for DB
-Thermal cycles
after IC DB TCB
Process risks
after IC DB
Partial dies test
possible
Added Cost
(+process steps) TCB
Enabled or the best
Medium & manageable
Unable, or higher risk/ cost

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 Status of Contenders of TSV Si Interposer (2.5DIC)

 Si Interposer has unparalleled ‘Fine Pitch (<1 um) line

and via ‘ capability and suitable for high density
multiple die packaging
• Other close contender status are:
• Glass Interposer : came and gone, lack of ecosystem
• Organic Interposer (fine line laminated substrate):
delivery of 5um line keep delaying, cost still unknown;
PCB industry need to invest below 5um
• Fan Out Packaging: capability of 2um line x 2 layers
demonstrated, but larger package size (> 15 x 15 mm2)
will be challenging

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 Extending TSV/ Interposer to Optical Interconnects
• Motivation: the cloud computing, IoT, big data, all driving
high speed data transmitting while maintain power budget
(less heat)
• Optical interconnection is candidate to replace Cu
interconnections
• To reduce the light transmittion loss (ideally <1db across
wavelength) ; IC packaging technology is considered would
enhance the passive alignment accuracy (request +/- 1-2 um,
in x, y, z directions) on multiple opto-electronic devices like
- Photodiode (PD), VCSEL
- Controller (IC), Si Photonics

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Optoelectronic Packaging- Key Components
*There are four key die in light engine packaging: VCSEL(LD),PD ,Drive IC ,TIA
Fiber Array Fiber Array
Microlens Microlens Passive
Align
Wire Bond
TSV Si Interposer Underfill
C4 Bump PD Hermetic Drive VCSEL PD TIA
Drive IC VCSEL TIA

Substrate Substrate
Heat sink

Flip Chip Assembly Wire Bond Assembly

(Couple light to glass fiber by microlens) (Couple light to glass fiber by microlens)

*VCSEL(Laser Diode)(面射型or邊射型雷射) *PD(Photodiode)(光電二極體)

-Optical transmitting(光發射端,電轉成光訊號) -Optical receiving(光接收端,光轉成電訊號)
-III-V compounds(GaAs) -III-V compounds(InGaAs)
-Au pad for wire bond or flip chip bond -Au pad for wire bond or flip chip bond
-Die size: single channel 0.25x0.25x0.15mm -Die size: single channel 0.25x0.25x0.15mm
4 channel 1.0x0.25x0.15mm 4 channel 1.0x0.25x0.15mm
-Alignment accuracy x, y, z +/-10um (w/ lens) -Alignment accuracy x, y, z +/-10um(w/ lens)
x, y, z +/-2um (w/o lens) x, y ,z +/- 2um (w/o lens)

*Drive IC (雷射驅動晶片) *TIA(Transimpedance Amplifier (轉阻放大器)

- To drive laser diode(驅動控制雷射光發射) -To amplify PD single(放大光電二極體電訊號)
-Si CMOS chip -Si CMOS chip
-Al pad for wire bond -Al pad for wire bond
-SnAg bump for flip chip bond -SnAg bump for flip chip bond
-Die size: single channel 0.5x0.5x0.35mm -Die size: single channel 0.5x0.5x0.35mm
4 channel 1.5x1.5x0.35mm 4 channel 1.5x1.5x0.35mm

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Optoelectronic Packaging – Light Engine
Example:

SPIL 25Gpbs
Light Engine
TV Structure
Micro-lens
Proposal
Top View
Substrate
Block
VCSEL/PD
TSV Interposer

Drive IC/TIA
Heat Sink

Bottom View

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SPIL Light Engine demo.: TSV Interposer
Interposer
Lens
thickness:152~200um,
TSV Interposer Via diameter: 160um,
Via pitch: 250um,

Small bump

Grinding

 SPIL offer TSV Interposer with high accuracy control in TSV via dimension
(offset accuracy +/-0.5um, diameter accuracy +/-5%) and Interposer thickness.

 100% aligned with 3DIC platform technology.

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SPIL Light Engine demo.: Lens Bonding
Micro-Lens
Micro-lens

Micro-Lens
Interposer

2 sight camera

Lens ±5um
lens

Interposer
VCSEL
VCSEL/PD

Micro-lens passive alignment scheme

Lens Alignment

 SPIL proposes passive alignment scheme which can reach high AOI
alignment with optical component
 Micro-lens bonding passively with high accuracy control (+/-5um)

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24 Confidential
 Summary:
• TSV 3DIC is realized in high bandwidth memory (HBM),
TSV Si interposer (2.5DIC) have been adopted that
realized the homogeneous and heterogeneous
integration
• High cost due to fragmented supply chain still limited
2.5DIC in very high end products that can afford it
• The ramping of 2.5DIC will largely depending on the
speed of cost down and how fast the other contending
alternatives can close in with better C/P value
• TSV interposer can also be applied in optoelectronic
packaging, but depending on the structure and it is not
a must be solution

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