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Integrated circuits are put into protective packages to allow easy handling and assembly onto printed
circuit boards and to protect the devices from damage. A very large number of different types of
package exist. Some package types have standardized dimensions and tolerances, and are registered
with trade industry associations such as JEDEC and Pro Electron. Other types are proprietary
designations that may be made by only one or two manufacturers. Integrated circuit packaging is the
last assembly process before testing and shipping devices to customers.
Occasionally specially-processed integrated circuit dies are prepared for direct connections to a
substrate without an intermediate header or carrier. In flip chip systems the IC is connected by solder
bumps to a substrate. In beam-lead technology, the metallized pads that would be used for wire A standard-sized 8-pin dual in-line
bonding connections in a conventional chip are thickened and extended to allow external connections package (DIP) containing a 555 IC.
to the circuit. Assemblies using "bare" chips have additional packaging or filling with epoxy to protect
the devices from moisture.
Contents
Through-hole packages
Surface mount
Chip carrier
Pin grid arrays
Flat packages
Small outline packages
Chip-scale packages
Ball grid array
Transistor, diode, small-pin-count IC packages
Dimension reference
Surface-mount
Through-hole
Package dimensions
Dual row
Quad rows
LGA
Multi-chip packages
See also
References
External links
Through-hole packages
Through-hole technology uses holes drilled through the PCB for mounting the components. The component has leads that are soldered to pads on the
PCB to electrically and mechanically connect them to the PCB.
Acronym Full name Remark
Single in-line
SIP
package
Dual in-line 0.1 in (2.54 mm) pin spacing, rows 0.3 in (7.62 mm) or
DIP
package 0.6 in (15.24 mm) apart.
Surface mount
Acronym Full name Remark
CQGP[5]
LLP Lead-less lead-frame package A package with metric pin distribution (0.5–0.8 mm pitch)[6]
Chip carrier
A chip carrier is a rectangular package with contacts on all four edges. Leaded chip carriers have metal leads wrapped around the edge of the package,
in the shape of a letter J. Leadless chip carriers have metal pads on the edges. Chip carrier packages may be made of ceramic or plastic and are usually
secured to a printed circuit board by soldering, though sockets can be used for testing.
Flat packages
Acronym Full name Remark
- Flat-pack Earliest version metal/ceramic packaging with flat leads
PQFN Power quad flat-pack No-leads, with exposed die-pad[s] for heatsinking[12]
QFN Quad flat no-leads package Also called as micro lead frame (MLF).[3][13]
SIDEBRAZE[14][15]
Chip-scale packages
FBGA Fine-pitch ball-grid array A square or rectangular array of solder balls on one surface[3]
Dimension reference
Surface-mount
C
Clearance between IC body and PCB
H
Total Height
T
Lead Thickness
L
Total carrier length
LW
Lead width
LL
Lead length
P
Pitch
Through-hole
C
Clearance between IC body and board
H
Total height
T
Lead thickness
L
Total carrier length
LW
Lead width
LL
Lead length
P
Pitch
WB
IC body width
WL
Lead-to-lead width
Package dimensions
All measurements below are given in mm. To convert mm to mils, divide mm by 0.0254 (i.e., 2.54 mm / 0.0254 = 100 mil).
C
Clearance between package body and PCB.
H
Height of package from pin tip to top of package.
T
Thickness of pin.
L
Length of package body only.
LW
Pin width.
LL
Pin length from package to pin tip.
P
Pin pitch (distance between conductors to the PCB).
WB
Width of the package body only.
WL
Length from pin tip to pin tip on the opposite side.
Dual row
Image Family Pin Name Package WB WL H C L P LL T LW
Small-
SOT-23- 0.22–
SOT Y outline 1.6 2.8 1.45 2.9 0.95 0.6
6 0.38
transistor
Shrink
small-
SSOP Y 0.65
outline
package
Thin dual 0.7– 0.19–
TDFN N 8-TDFN 3 3 3 0.65 N/A
flat no-lead 0.8 0.3
Thin small-
TSOP Y outline 0.5
package
Thin shrink
small- 8- 0.09– 0.19–
TSSOP Y 4.4 6.4 1.2 0.15 3 0.65
outline TSSOP 0.2 0.3
package
Micro
small-
µSOP Y µSOP-8 4.9 1.1 3 0.65
outline
package[22]
US8
US8[23] Y 2.3 3.1 .7 2 0.5
package
Quad rows
Image Family Pin Name Package WB WL H C L P LL T LW
Plastic
PLCC N leaded chip- 1.27
carrier
Ceramic
48-
CLCC N leadless 14.22 14.22 2.21 14.22 1.016 N/A 0.508
CLCC
chip-carrier
Low-profile
LQFP Y Quad Flat 0.50
Package
Thin quad
TQFN N
flat no-lead
LGA
Package x y z
52-ULGA 12 mm 17 mm 0.65 mm
52-ULGA 14 mm 18 mm 0.10 mm
52-VELGA ? ? ?
Multi-chip packages
A variety of techniques for interconnecting several chips within a single package have been proposed and researched:
See also
Surface-mount technology
Three-dimensional integrated circuit
Interposer
IPC (electronics)
List of chip carriers
List of electronics package dimensions
Redistribution layer
Surface-mounted package sizes
Wafer-level packaging
References
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2011-12-15.
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3. "Integrated Circuit, IC Package Types; SOIC. Surface Mount Device Package" (http://www.interfacebus.com/Design_Pack_Type_SO
IC.html). Interfacebus.com. Retrieved 2011-12-15.
4. "National Semiconductor CERPACK Package Products" (https://web.archive.org/web/20120218205030/http://www.national.com/pac
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2012-02-18. Retrieved 2011-12-15.
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ng/parts/CQGP.html). National.com. Archived from the original (http://www.national.com/packaging/parts/CQGP.html) on 2007-10-21.
Retrieved 2011-12-15.
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National.com. Archived from the original (http://www.national.com/analog/packaging/llp) on 2011-02-13. Retrieved 2011-12-15.
7. "LTCC Low Temperature Co-fired Ceramic" (http://www.minicaps.com/ltcc.html). Minicaps.com. Retrieved 2011-12-15.
8. Frye, R.C.; Gabara, T.J.; Tai, K.L.; Fischer, W.C.; Knauer, S.C. (1993). "Performance evaluation of MCM chip-to-chip
interconnections using custom I/O buffer designs" (http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=410760). IEEE Xplore -
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9. "National Semiconductor Launches New Generation of Ultra-Miniature, High Pin-Count Integrated Circuit Packages" (https://web.arc
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10. Meyers, Michael; Jernigan, Scott (2004). Mike Meyers' A+ Guide to PC Hardware (https://books.google.com/?id=mvo5rpAX3RsC&p
g=PT94&lpg=PT94&dq=PAC+%22Pin+Array+Cartridge%22#v=onepage&q=PAC%20%22Pin%20Array%20Cartridge%22&f=false).
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11. [1] (http://ir.conexant.com/releasedetail.cfm?ReleaseID=431800) Archived (https://web.archive.org/web/20110818161952/http://ir.co
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External links
JEDEC JEP95 (http://www.jedec.org/category/technology-focus-area/jc-10/registered-outlines-jep95) official list of all (over 500)
standard electronic packages
Fairchild Index of Package Information (https://www.fairchildsemi.com/get-help/package-information/)
An illustrated listing of different package types, with links to typical dimensions/features of each (https://web.archive.org/web/201312
15133813/http://www.siliconfareast.com/ic-package-types.htm)
JEDEC JEP95 (https://www.jedec.org/category/technology-focus-area/jc-10/registered-outlines-jep95) official list of all (over 500)
standard electronic packages
Intersil packaging information (http://www.intersil.com/design/packages/)
ICpackage.org (http://www.icpackage.org)
Solder Pad Layout Dimensions (http://catalog.tycoelectronics.com/catalog/common/images/PartImages/chip_res_padsz.jpg)
International Microelectronics And Packaging Society (http://www.imaps.org)
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