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EXPERIMENT NO. 7
X A B Y
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
Figure 7.2: 2:1 MUX circuit has been successfully designed using SymicaDE tool.
Figure 7.3: 2:1 MUX Test circuit has been successfully designed using SymicaDE tool.
OBSERVATIONS:
Delay calculated: 2.21484e-10
Parameters Values
CMOS PTM 130nm
Technology
NMOS: W/L 360nm/180nm
PMOS: W/L 720nm/180nm
VDD 1.8V
Input signal V1=1.8V, V2=0V, Time
(Pulse) Period=100ns, Pulse Width=50ns
S
Input signal X0=1.8V, X1=0V
RESULT:
• 2:1 MUX circuit has been successfully designed using SymicaDE tool.
• Transient analysis also performed.