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Features
• High speed switching
• Capable of 4.5 V gate drive
• Low drive current
• High density mounting
• Low on-resistance
RDS(on) = 7.2 mΩ typ. (at VGS = 10 V)
Outline
SOP-8
5 6 7 8
D D D D
65
7
4 8 1, 2, 3 Source
G 4 Gate
3
4 5, 6, 7, 8 Drain
1 2
S S S
1 2 3
Electrical Characteristics
(Ta = 25°C)
Item Symbol Min Typ Max Unit Test Conditions
Drain to source breakdown voltage V(BR)DSS 30 — — V ID = 10 mA, VGS = 0
Gate to source leak current IGSS — — ± 0.1 µA VGS = ±20 V, VDS = 0
Zero gate voltage drain current IDSS — — 1 µA VDS = 30 V, VGS = 0
Gate to source cutoff voltage VGS(off) 1.0 — 2.5 V VDS = 10 V, I D = 1 mA
Static drain to source on state RDS(on) — 7.2 9.0 mΩ ID = 7 A, VGS = 10 V Note4
resistance RDS(on) — 9.6 14.0 mΩ ID = 7 A, VGS = 4.5 V Note4
Forward transfer admittance |yfs| 18 30 — S ID = 7 A, VDS = 10 V Note4
Input capacitance Ciss — 1650 — pF VDS = 10 V
Output capacitance Coss — 390 — pF VGS = 0
Reverse transfer capacitance Crss — 135 — pF f = 1 MHz
Gate Resistance Rg — 0.55 — Ω
Total gate charge Qg — 11 — nC VDD = 10 V
Gate to source charge Qgs — 4.7 — nC VGS = 4.5 V
Gate to drain charge Qgd — 2.5 — nC ID = 14 A
Turn-on delay time td(on) — 8.5 — ns VGS = 10 V, ID = 7 A
Rise time tr — 5 — ns VDD ≅ 10 V
Turn-off delay time td(off) — 38 — ns RL = 1.42 Ω
Rg = 4.7 Ω
Fall time tf — 3.8 — ns
Body–drain diode forward voltage VDF — 0.80 1.04 V IF = 14 A, VGS = 0 Note4
Body–drain diode reverse recovery trr — 28 — ns IF = 14 A, VGS = 0
time diF/ dt = 100 A/ µs
Notes: 4. Pulse test
Main Characteristics
ID (A)
(FR4 40 x 40 x 1.6 mm), PW < 10 s 10
3.0 0µ
1m s
DC PW s
10 Op =1
era 0m
Drain Current
Channel Dissipation
tio s
n(
2.0 PW
1 < 1Note
Operation in 0s 5
)
this area is
1.0 limited by RDS(on)
0.1
Ta = 25°C
1 shot Pulse
0.01
0 50 100 150 200 0.1 0.3 1 3 10 30 100
Ambient Temperature Ta (°C) Drain to Source Voltage VDS (V)
Note 5 :
When using the glass epoxy board
(FR4 40x40x1.6 mm)
ID (A)
12 12
Drain Current
2.6 V
Drain Current
Tc = 75°C
8 8
0 2 4 6 8 10 0 1 2 3 4 5
Drain to Source Voltage VDS (V) Gate to Source Voltage VGS (V)
Drain to Source Saturation Voltage vs. Static Drain to Source on State Resistance
Gate to Source Voltage vs. Drain Current
VDS(on) (mV)
300 100
Drain to Source On State Resistance
50
240
V GS = 4.5 V
20
180
Drain to Source Voltage
ID = 20 A
10
10 V
120
5
10 A
60
5A 2
1
0 4 8 12 16 20 1 10 100 1000
Gate to Source Voltage VGS (V) Drain Current ID (A)
12 V
GS = 4.5 V
10
8 25°C
5 A, 10 A, 20 A
1 75°C
10 V
4
VDS = 10 V
Pulse Test
0
-25 0 25 50 75 100 125 150 0.1 0.3 1 3 10 30 100
Case Temperature Tc (°C) Drain Current ID (A)
3000
Ciss
Capacitance C (pF)
50
1000
Coss
300
Crss
20 100
ID = 14 A VGS = 10 V, VDS = 10 V
V GS (V)
VDD = 25 V
100
Drain to Source Voltage
10 V
Gate to Source Voltage
30 5V 12 t d(off)
VDS
tr
20 8 t d(on)
10
VDD = 25 V
10 10 V 4
5V tf
0 1
0 8 16 24 32 40 0.1 1 10 100
Gate Charge Qg (nc) Drain Current ID (A)
8 8
4 4
Pulse Test
0
0 0.4 0.8 1.2 1.6 2.0 25 50 75 100 125 150
Source to Drain Voltage VSD (V) Channel Temperature Tch (°C)
D=1
1
0.5
0.2
0.1
0.1
0.05
θch - f(t) = γs (t) x θch - f
0.02 θch - f = 83.3°C/W, Ta = 25°C
0.01
0.01 When using the glass epoxy board
lse (FR4 40 x 40 x 1.6 mm)
t pu
ho PW
0.001 1s PDM D=
T
PW
T
0.0001
10 µ 100 µ 1m 10 m 100 m 1 10 100 1000 10000
Pulse Width PW (s)
1 VDSS
EAR = L • IAP2 •
L 2 VDSS - V DD
V DS
Monitor
I AP V (BR)DSS
Monitor
I AP
Rg D. U. T VDD V DS
ID
Vin 50Ω
15 V
VDD
0
td(on) tr td(off) tf
Package Dimensions
As of January, 2003
Unit: mm
4.90
5.3 Max
8 5
3.95
1 4
*0.22 ± 0.03
0.20 ± 0.03
1.75 Max
+ 0.10
6.10 – 0.30
0.75 Max
1.08
0˚ – 8˚
+ 0.11
0.14 – 0.04
+ 0.67
1.27 0.60 – 0.20
*0.42 ± 0.08
0.40 ± 0.06
0.15
0.25 M
Package Code FP-8DA
JEDEC Conforms
*Dimension including the plating thickness JEITA —
Base material dimension Mass (reference value) 0.085 g
Ordering Information
Part Name Quantity Shipping Container
HAT2198R-EL-E 2500 pcs Taping
Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of
production before ordering the product.