2017 IEEE PES Asia-Pacific Power and Energy Engineering Conference (APPEEC)
A Simplified Charge Balancing Algorithm for
Modular Multilevel Converter
Rajdip Dey and Shabari Nath
Department of Electronics and Electrical Engineering
Indian Institute of Technology Guwahati, Assam, India
Email: rajdip.dey@iitg.ernet.in, snath@iitg.ernet.in
Abstract—Modular multilevel converter (MMC) is used in
several applications of medium and high voltage transmission
system as it has several advantages over other power electronic
converters. For conventional converters, capacitor charge balanc-
ing is not a huge problem. Only the load ripple current flows
through the DC link capacitor. Main load current doesn’t affect
the capacitor and it flows through the DC bus. For a MMC,
charge balancing of all the module capacitors is a complicated
task as the full load current flows through all the modules when
MMC is operational. The module capacitors get charged and
discharged very rapidly. Few charge balancing algorithms are
already proposed in the literature. They have some disadvantages
due to high execution time and complexity, as number of modules
need to be inserted or bypassed is calculated in every step of
operation.
In this paper a simplified charge balancing algorithm is
proposed depending upon the phase disposition modulation
technique. In the proposed algorithm there is no need to
calculate the number of modules that need to be inserted or
bypassed during every step of operation. In addition, gate signals
are given to the module switches directly. The new technique is
fast and less complex. A nine level modular multilevel converter
is simulated using the proposed algorithm in Matlab Simulink
environment. All simulation results are presented in the paper.
Keywords: Capacitor charge balancing, modular multilevel
converter, modulation technique, phase disposition
N OMENCLATURE
( p,n ) = y Variable for upper and lower switch
in a half bridge module
( u,l ) = x Variable for upper and lower arm
( a,b,c ) = j Variable for phase
( 1,2..N ) = i Variable for module number
SMx,i,j ith module in arm x and j th phase
Vgate,x,i,j,y Gate pulse for y th switch for ith
module in arm x and j th phase
Vcap,x,i,j Capacitor voltage for ith module in
arm x and j th phase
Vcarrier,i ith carrier waveform
Vmod,j Modulating signal for j th phase
Vinter−pulse,i,j Pulse obtained by Vcarrier,i and Vmod,j
V̄inter−pulse,i,j Complementary pulse of Vinter−pulse,i,j
Tinter−pulse,i,j Time period for Vinter−pulse,i,j
978-1-5386-1379-5/17/$31.00 2017
c IEEE
I. I NTRODUCTION
In today’s transmission system, transmission voltage and
distance of transmission line are increasing rapidly. With
this modular multilevel converter (MMC) is becoming very
popular. MMC is used in several applications in high and
medium voltage power conversion. It has many advantages like
scalability, modularity, absence of bigger DC link capacitor,
good harmonic performances and high efficiency [1,2].
Output load voltage control and capacitor charge balancing
are two main control functions in MMC [4,5]. For voltage
source or multilevel converters capacitor charge balancing is
not as difficult as MMC. Only the load ripple current flows
through the DC link capacitor. Full load current flows through
the DC bus and doesn’t affect the capacitor charge.
In a MMC a single DC link capacitor is not used. Instead
of this, the DC bus capacitor is divided in all the modules
[3]. In a half bridge module MMC, module capacitors can be
bypassed or inserted depending upon the switching of half
bridge module [1,9]. The full load current of MMC flows
through the capacitors of all inserted modules. Depending
upon the load current direction the capacitors get charged
or discharged very rapidly. So charge balancing of module
capacitors is a severe problem for MMC [6].
A charge balancing algorithm is already proposed in the
literature which has several disadvantages [1,6,7,8,10]. In
this technique first the number of modules that need to be
inserted or bypassed is calculated in every step of operation.
This calculation depends upon load voltage requirement and
capacitor voltage of the module. If the number of modules
increase in MMC then this calculation becomes very complex
and tedious which is explained in detail in section III. In
HVDC transmission system voltage level is in KV range and a
few hundred modules are used in the MMC, so this algorithm
is not very suitable.
Based on phase disposition (PD) modulation technique,
a simplified charge balancing algorithm is proposed. Here
PD modulation technique is used and number of modules
need to be inserted or bypassed is directly calculated from
modulation technique. In this new algorithm gate signals can
be given to respective module switches directly which is
properly explained in section IV. The proposed new algorithm
is less complex, faster and can be used in MMC for HVDC load voltage increases more number of modules are inserted
applications. in the operation of MMC to create higher output voltage.
The simplified charge balancing algorithm is verified in
Matlab Simulink environment. A nine level MMC is simulated  

and simulation results are analysed. The load voltage control

 
 
and capacitor balancing is achieved using proposed charge 

balancing algorithm. All simulation results are presented and
    
discussed in this paper. 

In this paper, MMC and some modulation techniques are

presented in Section II. In Section III the existing algorithm
 
is presented. In Section IV the new simplified algorithm is
proposed and analysed. Finally, in Section V the simulation 
 
 
results are presented and discussed.  

  
II. MMC AND ITS MODULATION TECHNIQUE   


  





  
  
   Fig. 2. Different module’s capacitor voltage when MMC is operational

 




For modulation of MMC, various PWM techniques based
on a single modulating are already proposed. In this simpli-
   fied new algorithm, phase disposition (PD) PWM technique
is used. As can be seen, around the x axis symmetrically



triangular carrier waves are displaced depending upon the no
  


of modules in MMC [7]. Comparison of modulating wave
  with all these carrier waves produces switching signals [8].
 
  For ‘N’ number of modules in each arm ‘N’ number of carrier
  
waveforms are required. Fig.3 shows the PD-PWM method for




a nine level MMC.
 



 


  



 


 

 

 


Fig. 1. MMC structure 





Fig.1 shows the structure of a modular multilevel converter.
Each module consists of a half bridge module with a capacitor. 


Each phase is called one leg of the converter and each leg 

consists of two arms, upper and lower. There is an inductor
in each arm to suppress higher order harmonic and circulating
 

currents [1]. A single capacitor for DC bus is not used. Instead
 
the DC bus capacitance is divided among individual modules.
Each leg is controlled and finally produce the required output
voltage [7]. Each arm has its own impedance.
A half bridge module is generally used in MMC, which has
two complementary switches Sx and S. When one switch is
kept ON then other is turned off and vice versa. Depending
upon the switching of these two switches of the half bridge
module, a module can be inserted or bypassed when MMC is
operational. It can be seen from the fig.2 that when Sx = 1 and
S = 0 then the module is inserted and it produces Vcell voltage
as output. If Sx = 0 and S = 1 then the module is bypassed
and output voltage of the module is zero. As requirement of
 
 
Fig. 3. Phase disposition modulation technique
As the DC bus capacitor is divided in all the modules as
small scale capacitors, the full load current flows through
all the inserted modules capacitors when MMC operates.
Depending upon the load current direction the inserted module
capacitors get highly charged or discharged as shown in fig.2.
If the capacitor voltage of all the modules are not balanced
then output voltage waveform can not be controlled. So a
proper charge balancing algorithm is needed for a MMC for
its proper functioning.
III. D ISADVANTAGE OF EXISTING ALGORITHM FOR
CHARGE BALANCING
In existing algorithm [1,6,7,8,10], shown in fig.4, first the
number of modules that need to be inserted or bypassed
to produce required output load voltage is calculated. This
number is compared to previous state to find if any new
module needs to be inserted or bypassed. This is a complex
procedure and not needed in the new algorithm.
Secondly the load current is measured to find if it is going to
charge or discharge the inserted module capacitors. After that
all modules are sorted depending upon their capacitor voltages.
If load current is positive and new modules need to be inserted
then the inserted module’s capacitors are going to be charged.
The lowest capacitor voltage module needs to be inserted for
highest possible time and highest capacitor voltage module
needs to be inserted for lowest possible time. If load current is
negative and new modules need to be inserted then the inserted
module’s capacitors are going to be discharged. So the highest


are needed. All carrier waveforms are named as 1,2,3....N and
are shifted from x axis in increasing order. Depending upon
the required load voltage, the modulating signal crosses the
carrier waveforms. If the required load voltage is low then
modulating signal may not cross all the carrier signals.
In this algorithm there is no need to calculate the number
of new modules need to be inserted or bypassed every step of
operation. From the number of carrier signals those are crossed
by the modulating signal, the number of modules needs to be
inserted or bypassed can be directly calculated. From fig.5 it
can be seen that when modulating signal crosses first carrier
waveform then one module from upper and one module from
lower arm are inserted and all other modules are bypassed.
When the modulating signal crosses two carrier waveforms
then two modules in upper arm and another two modules
from lower arm need to be inserted all other modules are
bypassed. Similarly when the modulating signal crosses all
carrier waveforms then all modules needs to be inserted to
produce the required load voltage.




capacitor voltage module needs to be inserted for highest 


possible time and lowest capacitor voltage module needs to be

inserted for lowest possible time to obtain charge balance. If 

more modules need to be bypassed then the opposite happens.


  
The calculation of which module needs to be inserted or  










bypassed becomes very tedious if MMC has very high number 

 


of modules. The calculation of which gate signal should 

 
 

 
be provided to which switch becomes very complex with







 

increasing number of modules in MMC. In the new algorithm
the gate signals can be given to the switches directly without Fig. 5. Calculation of number of modules need to be switched on or off
any calculation. directly from PD technique

   
From fig.5 and fig.6 it can be easily seen that when


 
modulating signal is compared to the carrier wave form,
  
  Vinter−pulse,1,j has higher time period (Tinter−pulse,1,j )
than Vinter−pulse,2,j and Vinter−pulse,2,j has longer dura-
tion (Tinter−pulse,2,j ) than Vinter−pulse,3,j and so on. The






Vinter−pulse,N,j has the shortest time period.
In this algorithm firstly all modules of one arm of one phase






 are sorted depending upon there capacitor voltages. A sorting







 algorithm is applied on all Vcap,u,i,a and on all Vcap,l,i,a of
a phase. The sorting algorithm is explained with the help of
following example. Suppose after sorting it is found that,
   

    Vcap,u,3,a < Vcap,u,5,a < Vcap,u,N,a .... < Vcap,u,2,a (1)

 

 

  
   Vcap,l,N −1,a < Vcap,l,N −4,a < Vcap,l,1,a .... < Vcap,l,3,a
               
       
Then in next step the direction of load current is measured.
Fig. 4. Existing algorithm Suppose in first case it is found that,
Il > 0
IV. P ROPOSED ALGORITHM As the load current is positive, it is going to charge the
The simplified proposed algorithm is based on phase dis- module capacitors. So highest time period switching signal
position modulation technique. For ‘N’ number of modules must be given to lowest capacitor voltage module and lowest
in each arm of each phase, ‘N’ number of carrier waveforms time period switching signal is given to highest capacitor
 

 
 
 
Vgate,l,N −1,a,p = V̄inter−pulse,N,a
 


 
Vgate,l,N −1,a,n = Vinter−pulse,N,a
 
Similarly switching signals are given to all other modules of


 phase ‘a’. For module SMu,2,a and SMl,3,a which has highest
capacitor voltage, the switching signal will be,
 



Vgate,u,2,a,p = Vinter−pulse,1,a (5)

 Vgate,u,2,a,n = V̄inter−pulse,1,a
 
Vgate,l,3,a,p = V̄inter−pulse,1,a


 
 
Vgate,l,3,a,n = Vinter−pulse,1,a


 
By this strategy, charge balancing is done in the MMC
  modules. Fig.7 shows the flowchart of simplified proposed



algorithm. Comparing fig.4 and fig.7 it is clear that two steps
are removed in proposed algorithm.

Fig. 6. Sending gate signals directly to the module switches for charge
balancing for the upper arm for Il > 0 and Il < 0


  

 


voltage module. So directly switching signals are sent to the

modules. For module SMu,3,a and SMl,N −1,a which have
 
lowest capacitor voltage, the switching signal will be, 

Vgate,u,3,a,p = Vinter−pulse,1,a (2)

Vgate,u,3,a,n = V̄inter−pulse,1,a 

 

 
  

 

 









       
Vgate,l,N −1,a,p = V̄inter−pulse,1,a            
     

 
 
 
 
 

Vgate,l,N −1,a,n = Vinter−pulse,1,a
Similarly switching signals are given to all other modules Fig. 7. Simplified proposed algorithm
of phase ‘a’. For module SMu,2,a and SMl,3,a which have
highest capacitor voltage, the switching signal will be,
V. S IMULATION RESULTS AND DISCUSSION
Vgate,u,2,a,p = Vinter−pulse,N,a (3) A three phase nine level modular multilevel converter is
Vgate,u,2,a,n = V̄inter−pulse,N,a simulated in Matlab Simulink environment and results are
discussed here. The simulated MMC is connected to a DC
Vgate,l,3,a,p = V̄inter−pulse,N,a bus and operated in inverter mode. The DC bus voltage, VP N
is taken as 1600V. In each arm, total eight number of half
Vgate,l,3,a,n = Vinter−pulse,N,a
bridge modules are placed to get nine level voltage. Arm
Similarly gate pulse for other modules can be obtained. Now inductance (L0 ) and module capacitance (C0 ) are two very
if, important parameters in which system cost and performance
Il < 0 depends. Arm inductor value depends upon the application and
power rating of MMC. It suppresses all higher order harmonic
As the load current is negative, it is going to discharge the currents. Depending upon the power rating the arm inductor
module capacitors. So highest time period switching signal is calculated and taken as 10mH. The half bridge module
must be given to highest capacitor voltage module and lowest capacitor value depends upon the voltage ripple and hence
time period switching signal is given to lowest capacitor on the stored energy in the capacitor. It is also calculated and
voltage module to keep the charge balance. For module taken as 500 μF. The load is inductive and star connected. In
SMu,3,a and SMl,N −1,a which has lowest capacitor voltage, each phase of load, 10 Ω resistance and 100 mH inductance are
the switching signal will be, present. In fig.8 phase voltage (Vao ) of the modular multilevel
Vgate,u,3,a,p = Vinter−pulse,N,a (4) converter is presented. It can be visualised that total nine levels
are present in the phase voltage waveform. As the VP N is
Vgate,u,3,a,n = V̄inter−pulse,N,a 1600V and in each arm eight modules are present so each
 1000
Vao 1000

Voltage (V)
Reference voltage
500
0
Voltage (V)

0 −1000
0.1 0.15 0.2 0.25 0.3 0.35 0.4
Time (Sec)
1000
−500

Voltage (V)
V
ao
0
−1000
0 0.05 0.1 0.15
Time (Sec) −1000
0.1 0.15 0.2 0.25 0.3 0.35 0.4
Time (Sec)
Fig. 8. Phase voltage waveform of nine level MMC 1000

Voltage (V)
Fundamental component of V
ao
0

Vab −1000
1000 0.1 0.15 0.2 0.25 0.3 0.35 0.4
Voltage (V)

Time (Sec)
0

−1000 Fig. 10. Reference voltage, phase voltage and fundamental component of
phase voltage of nine level MMC
0 0.05 0.1 0.15
Time (Sec)

40
300
Voltage (V)
I
a Capacitor voltage of SM
20 200 u,1,a
Current (A)

0 100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (Sec)
−20 300
Voltage (V)

Capacitor voltage of SM
200 u,2,a
−40
0 0.05 0.1 0.15
Time (Sec) 100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (Sec)
300
Voltage (V)

Fig. 9. Line voltage and line current waveform of nine level MMC Capacitor voltage of SMl,2,a
200

100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (Sec)
voltage level is 200V. The output phase voltage is 800V 50 300
Voltage (V)

Capacitor voltage of SM
Hz AC. 200 l,1,a

Here in fig.9 the output line to line voltage (Vab ) and line 100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
current (Ia ) are presented. The output line voltage has fifteen
√ Time (Sec)
steps. It can be seen from the figure that line voltage is 3
times of phase voltage as load is star connected. Depending
upon the load, the load current is 38A. Fig. 11. Different module’s capacitor voltage when MMC is operational
In fig.10 the tracking of output voltage in closed loop
control of modular multilevel converter is conferred. To get 201
Module Capacitor voltage
the fundamental waveform of the output phase voltage, the
output staircase waveform is passed through a low pass filter 200.5

and compared to the reference voltage waveform. A 720V

Voltage (V)

reference voltage is given to the control block of MMC. It 200

is observed from fig.10 fundamental component of output

199.5
voltage is tracking the reference voltage. Here total eight
modules from each arm need to be switched on. So close
199
loop control of output load voltage in a MMC is performed 0.1 0.105 0.11 0.115 0.12 0.125 0.13 0.135 0.14 0.145 0.15
Time (Sec)
using the proposed algorithm.
In fig.11 two upper arm module capacitor voltages Fig. 12. Capacitor voltage of half bridge module when MMC is operational
(Vcap,u,1,j , Vcap,u,2,j ) and two lower arm module capacitor
voltages (Vcap,l,1,j , Vcap,l,2,j ) are presented. It can be seen
from the fig.11 that all capacitor voltages are properly balanced be seen that capacitor voltage has very little ripple and has
and has a DC value of 200V. a DC value of 200V as it can be calculated as(VP N /N ).
Finally in fig.12 the enlarged version of the capacitor voltage So charge of all the module capacitors are balanced using
of one module is observed when MMC is operational. It can the proposed algorithm, So, the proposed simplified algorithm
works perfectly as the output voltage is tracking the load
voltage and the charge of all module capacitors are balanced.
VI. C ONCLUSION
MMC has several applications in high and medium volt-
age power conversion. Charge balancing of all the module
capacitors is a complex procedure as load current flows
directly through the module capacitors. Previous algorithms
are complex and tedious. In this paper a simplified charge
balancing algorithm of modular multilevel converter is pro-
posed based on phase disposition modulation technique. The
proposed algorithm is applied to the closed loop control of
single and three phase MMC. Using the new algorithm the
load voltage control can be achieved and it is simpler and
faster than previous algorithms. The simplified new algorithm
is verified by simulation results and can be used in modern
power transmission system where a very high no of modules
are present in MMC due to very high voltage requirement.
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