Scribd Logo
Upload

Welcome to Scribd!

  • Advanced Verification Techniques Training

    Uploaded by

    Maarij Raheem
    26 views2 pages
    The 4-week Advanced Verification Techniques Training program covers SystemVerilog training, UVM methodology, verification environments, and documentation. Each week focuses on a different verification topic, including SystemVerilog, UVM practical application, using VIP, and documentation evaluation. The training is designed to help hardware designers develop skills to leverage SystemVerilog features for design and validation.

    Original Description:

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    The 4-week Advanced Verification Techniques Training program covers SystemVerilog training, UVM methodology, verification environments, and documentation. Each week focuses on a different verification topic, including SystemVerilog, UVM practical application, using VIP, and documentation evaluation. The training is designed to help hardware designers develop skills to leverage SystemVerilog features for design and validation.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    26 views2 pages

    Advanced Verification Techniques Training

    Uploaded by

    Maarij Raheem
    The 4-week Advanced Verification Techniques Training program covers SystemVerilog training, UVM methodology, verification environments, and documentation. Each week focuses on a different verification topic, including SystemVerilog, UVM practical application, using VIP, and documentation evaluation. The training is designed to help hardware designers develop skills to leverage SystemVerilog features for design and validation.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 2

    Advanced Verification

    Techniques Training

    4 Weeks

    electraic www.electraic.com trainings@electraic.com +90 216 912 0167


    Training Course
    Week Program
    1 SystemVeriIog Training
    2 UVM Training and Practical Application
    3 Setting Up A Verification Environment Using VIP
    4 Use of Documentation in Verification Evaluation

    Advanced Verification Techniques Training offers a compact training


    program to meet the requirements of hardware design engineers. Our
    training is designed to enable designers to develop their capabilities by
    leveraging SystemVeriIog features for their overall design and validation
    requirements, including RTL Coding, Assertions and Testcases.
    In addition, designers will have the opportunity to install the UVM (UniversaI
    Verification Methodology) environment, a standard functional verification
    methodology developed for SystemVeriIog, from scratch.
    They will verify the design they have achieved in Digital Design and VHDL
    Training using VIP.

    Learning Outcomes
    Bus-Functional Modeling TLM and Channels
    Basic Data Types Component Hierarchy
    Interfaces Monitors and Checkers
    The SVA Language Functional Coverage
    Properties and Assertions Factory and Configuration
    Clocking Blocks Agent Architecture
    Randomization Objections
    Coverage Sequences
    Arrays and Queues Layered Sequences
    Classes for Transactions Events and Barriers
    Class Members and Copying UVM Register Layer
    Virtual Interfaces
    Extending Classes for Stimulus

    electraic www.electraic.com trainings@electraic.com +90 216 912 0167

    You might also like