Electrical and Computer Engineering

Computer Organization and Architecture

CSE 332
Credits – 3

Prerequisites : CSE 231 Digital Logic

Design

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 LESSON 7
Datapath & Control.

Source:
https://sites.google.com/site/neuro11school/lect
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 MIPS Program 1000
Add $t0,…
Inst. Addr. instruction
1000 Add $t0,…
1004 Lw $t1, …
…. ….

Instruction Memory is a part of Main Memory.

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 1004 1000
PC is a 32 bit Register

1004 1000

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1000

1004

0004

1004 1000

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 Inst. Addr. instruction
1000 Add $t0,…
1004 Lw $t1, …
…. ….

Draw
Draw & Explain
Develop or complete

Into CPU
for
execution

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10
-add, and

lw, sw

Bne, J

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 [$t3]

[$t2]

[$t1]

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 [$t3]
[$t3]

[$t1]
[$t2]
[$t2]

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 010

[$t3]

Add result
[$t2]

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[$t1] Add result

[result]

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 [$t1]
[result]
Add result

=1

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 16 bits Offset
Base
Lw $t1, 0($t2)

16 bits Offset
Base
Sw $t1, 0($t2)

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 16 bits Offset
Base
Lw $t1, 0($t2)

16 bits Offset
Base
Sw $t1, 0($t2)

If [$t2] = 0000 0008H then;

Base [$t2] + 32 bits Offset
=00000008 + 00000000 H
=00000008H

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 16 bits Offset
Base Write to register $t1
Lw $t1, 0($t2)
=0
Base [$t2] + 32 bits Offset
00000008H data
32 bits Offset

=1

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 16 bits Offset
Base
Sw $t1, 0($t2) =1

Base [$t2] + 32 bits Offset

00000008H
32 bits Offset

Update mem with [$t1]

=0

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 Base
Lw $t1, 0($t2)

Base
Sw $t1, 0($t2)

Complete the
datapath for
Load & Store
instructions.

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 The datapath for Load & Store instructions with fetch:
Lw $t1, 0($t2)
Sw $t1, 0($t2)

Base 010
=1 for sw
[$t2]
[$t2]

[$t1]

=1
Sw $t1, 0($t2)

16 bits Offset (0) 32 bits Offset (0) =1 for lw

Lw $t1, 0($t2) 22
 LESSON 7 (S2)
Datapath & Control.

Source:
https://sites.google.com/site/neuro11school/lect
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Lw $t1, 0($t2) Sw $t1, 0($t2)

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From Reg mem
0

Sign ext
1
Control o or 1

At the lower input of ALU

0
m
u
x
1

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 Lw/Sw & Add

From Data mem

0

ALU
1
Control o or 1

At the input of write data of reg mem

0
m
u
x
1

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 MIPS Program
Inst. Addr. instruction
1000 Add $t0,…
1004 Lw $t1, …
1008 Sw $t1, …

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 We have developed
MIPS Program datapath and controls
Inst. Addr. instruction for R type/ Memory
1000 Add $t0,… Data transfer
1004 Lw $t1, … instructions in last class.
1008 Sw $t1, …

Today we will
look into Branch
Inst. Addr. instruction
instructions
1000 Add $t0,…
1004 Lw $t1, …
1008 Sw $t1, …
….
1012 Beq $t1, $t2, 0

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# If [$t1] = [$t2] then branch out

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beq $t1, $t2, 16 bits offset # If [$t1] = [$t2] the branch to a Target location in memory based on
given offset.

$t1, $t2

If [$t1] = [$t2] then sub result =0

Hence ALU zero output =1

beq $t1, $t2, 1

Say, 16 bits Offset = 0001H
32 bits Offset = 0000 0001H

32 bits Offset = 0000 0100H

Target address = 0000 0000 0000 1000H

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beq $t1, $t2, 1
bne $t1, $t2, 1
J1
Word 0000 1000H
displacement

0000 0100H

110 (sub) 12
√8
[$t1] [$t1] 4
0 PC
[$t2]
=1 when equal (beq)
[$t2] =0 when not equal (bne)
0001H
If [$t1] = [$t2] then sub result =0
Hence ALU zero output =1
0000 0001H

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beq $t1, $t2, 1 ; Branch
PC+4
add $t1, $t2, $t3 ; R type

Plus branch

0
x
x x
x

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beq $t1, $t2, 1 ; 1 cycle
add $t1, $t2, $t3 ; 1 cycle
addi $t1, $t2, 1 ; 1 cycle
lw $t1, 16($t3) ; 1 cycle

CPI=1
1 cycle for 1 inst.

Executing one instruction at a time within one 35

cycle. CPI=1
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END OF LESSON 7

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