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1
Outline
Inductors
Transmission lines
Varactors
MIM Capacitors
Resistors
2
Types of integrated inductors (Yoon, RFIC-2003)
In silicon ICs:
● Spiral
● Multi-layer shunted
● Symmetrical spiral Stacked Helical Stacked MEMS
● Stacked helical
3
Types of inductors: by number of terminals
2-terminal
3-terminal (t-coil)
transformers
symmetrical transformers
(baluns)
4
Inductor integration issues
Low quality factor (Q)
5
2-terminal inductor layout & cross-section
Main FOMs
● Inductance L
● Quality factor Q
● SRF
● PQF
6
Inductance L
Inductance: induces and stores magnetic field
total flux
Greenhouse Equation L=
current
n n n
L=Self Inductance ∑ Li + Mutual Inductance ∑ ∑ M ij
i=1 i=1 j=2 j≠i
Lj3
Mij
Lj2 Li3
Lj4
Li1
Lj1
7
Inductor Q
recommended range
Q describes energy
efficiency:
stored energy
Q=
dissipated energy
Conventional definition:
PQF SRF
ℑ−Y11
Qeff =
ℜY11
8
0.13 µm CMOS two-terminal inductor meas.
−1
ℑ[ Y11 ] ℑ[−Y11 ]
Leff = Qeff =
ℜ[ Y11 ]
9
Loss mechanisms in inductors (Dubuc et al, IMS2002)
loss in
metal
loss in
substrate
10
Metal loss: series resistance Rs
DC-loss due to thin metal
and planar geometry
Frequency-dependent
cross-section due to skin
effect (B induced by
conductor itself) J=JpJe where
11
Metal loss: techniques to reduce it
12
Substrate loss
Ip = potential current in
substrate, induced by
electric field
sub
Jp = sub E=− sub ∇
2
where ∇ =0
13
Propagation modes (Dubuc et al, IMS2002)
14
Substrate loss: techniques to reduce it
Minimize electric coupling to substrate (Id) (also increases
SRF and PQF):
small inductor area
increase dielectric thickness (process change ?)
low-k dielectric (process change)
Reduce eddy currents in substrate
pattern shield (reduces PQF, SRF)
Reduce both eddy and potential currents in sub.
increase substrate ( =>0) (process change)
Place sub contacts 30 m .. 50 m from inductor
15
HF inductor equivalent circuits: simple
T
W S
16
Equivalent circuit model equations: simple
Cao Y. et al., JSSC March 2003
6 0 n2 d2avg
L (see t-line-over-substrate equations) L≈
11d−7davg
n = number of turns
d = outer diameter of inductor
davg = arithmetic mean of inner and outer diameter
0 = 4 10-13 H/m is the permeability of vacuum
l
Rs has DC and AC (frequency dependent) terms RDC =
Wt
s is the conductivity of the metal l
R AC=
=
1
f
W 1−exp
−t
17
Equivalent circuit model equations (ii): simple π
1 ox
Coxi (oxide capacitance) Cox= l W
2 h
2 ox
Cp (overlap capacitance) Cp=n W hM9−M8
18
HF inductor equivalent circuit: 2-π
19
Parameter extraction (2-terminal circuit)
● At low frequency (0.5 GHz to 1 GHz) extract directly:
−1
ℑ[−Y 12 ] R=ℜ[−Y12−1 ]
L=
−1
Rsub1=ℜ[Y 11Y12 ] Rsub2=ℜ[Y 22Y12 −1 ]
−1 −1
[−ℑ[Y 11Y12 ]] [−ℑ[Y 22 Y12 −1 ]]−1
COX1= COX2=
r 0×Rsu
Csi=
Rsubi
20
Parameter extraction (2-terminal circuit)
21
Scaling of inductors to mm-wave frequencies
Scale size and frequency: f->f×S, W->W/S, l->l/S, d->d/S, h-
2
>h/S, t=ct.
L≈
2 2
6 0 n davg
11d−7davg
L
≈
[ ]
60 n 2 davg
S
S d davg
11 −7
Small footprint to minimize loss in silicon S S
1 ox Cox 1 l W ox
Cox= lW =
2 h S 2S S h
2 S
Cp
Cp=n W 2 ox
hM9−M8 S
=n
W ox
S hM9−M8
S
1 1
SRF≈ S×SRF=
2 LCOXCp
2
L COX Cp
S S
S
Scaling of inductors to mm-wave frequencies
Vertical stacking and magnetic coupling to
Increase inductance/area
reduce loss in substrate
Outcome
Inductors/transformers can be as small and inexpensive as
transistors
As in MOSFETs, series resistance does not scale
Q remains the same, but at fS l
l S
l R AC=
S
RDC =
Wt
RDC =
W
S
t
W
S
1−exp
−t
140 pH Planar Spiral Inductor in 90-nm CMOS
d = 29 m, n = 2.25
S = 2 m, W = 2 µm
t = 3 m Measured vs. ASITIC simulated Leff
and Qeff
Slide 24
3-terminal inductor layout
25
3-terminal inductor equivalent circuit
P3
Rt
CP Lt
k
P1 P2
C OX1 C OX1C OX2 C OX2
2 2 2
M
k=
L11× L22
Coxi, Rsubi, Csi are extracted from the 2-terminal equivalent.
27
Single-ended vs. diff.-mode inductance
Ldiff =L11L222M=2.2 nH
Lsingle=L11=L22=0.67nH
28
HF inductor layout design
High SRF: narrow metal, wide spacing, minimum diameter
29
High Q & high SRF inductor design tips
Small diameter
Narrow (narrower in inner turns), (W)
thick, (T)
widely spaced (S)
top metal -only (stacked structure for peaking inductors)
windings on
thick dielectric (h)
with low permittivity (OX)
30
i1
Transformers
i 2
n1 : n2
M
v1 L L2 v2 20 µm
1
2.5 µm
width
P2+
P1+ P1 -
31
3-D stacked transformer modelling
ASITIC modeling
procedure
1. Use “pix” on bottom coil
alone to find COX, CSUB, 20 µm
RSUB, R2, L2 2.5 µm
width
2. Calculate CSUB
3. Use “pix” on top coil
alone to find R1 and L1
4. Use “pix” on top coil
with bottom coil
grounded to get C12
5. Use “k” command on
both coils together to
find coupling. 32
Transformers in SiGe BiCMOS and 90nm CMOS
1:1
vertically 34 µm 1:1 vertically
stacked stacked
SiGe transformer in
BiCMOS 90-nm CMOS
transformer n=2, W= 2µm,
n=2, t=3µm S=2µm, t=3µm
Baluns (symmetrical transformers)
P2+ P2-
COX21 COX22 COX23
Inductors
Transmission lines
Varactors
MIM Capacitors
Resistors
35
Transmission lines
M8
Oxide
M1
Si substrate
µ-strip
M8
Oxide
Si substrate
CPW
36
Interconnect as Transmission Lines
Passivation
M8 Signal M8
M7 W=10um M7
M6 M6
M5 IMD M5
M4 M4
M3 M3
M2 M2
M1 M1
FOX
Si substrate ground
38
Transmission line params and models
Most important HF performance parameters:
Characteristic impedance: Z0
Attenuation (/mm):
40
T-line param. extraction from ABCD matrix
Impedance of line of
characteristic Z L j ZO tan d
impedance Z0 Zin =ZO where = j
Z O j ZL tan d
terminated on ZL
∣ ∣ ∣ ∣∣ ∣∣ ∣
csh d Z O sh d csh d ZO sh d
∣ ∣
A B=
C D
sh d
ZO
csh d
v1
i1
= sh d
ZO
csh d
v
× 2
−i2
Z O=
B
C
=
acshA
d
or =
ash BC
d
where d = 1 mm
2
41
Simple lumped ckt. model without skin effect
− 1 cosh −1 ( A )
2
L B
Signal line = LC ≈ 2
C C ω
GND
P1 P2
C OX
Rs Cs
P1 Z1 P2
Z1
Z2
L/2 R/2 L/2 R/2
P1 P2
Gd Cd
Extracting the lumped circuit parameters
Simulate (in HFSS) a line with l>=10m to find ABCD params.
or measurements
3.6mm long
46
Outline
Inductors
Transmission lines
Varactors
MIM Capacitors
Resistors
47
Variable capacitance devices: Varactors
Figures of merit
capacitance ratio:
CMAX/CMIN
quality factor Q
linearity
Applications
VCO
Implementation
p-n junction
accumulation-mode MOS
capacitor
Common-sense rules
Accumulation-mode MOS (AMOS) varactors have higher Q
and larger tuning range than pn junction varactors
If varactor model is not available, build a rudimentary model:
use MOSFET with S/D tied together
Add gate resistance externally, as for MOSFET
Calculate CMAX= COX×W×L + 2Cov
CMIN = CMAX/2
Smaller varactors (W and Wf) have higher Q's at a given
frequency
Extraction of simplified equivalent circuit
gate
n+ n+ p+
STI STI STI
p-well
n-well
p- substrate
−1 −1
Cvar =
[ ℑ[−Y 12 ]]
Cnw=
−1
[ℑZ21 ]
R=RGRCH=ℜZ11Z22−Z12−Z21 Rsub =ℜZ21
50
Meas. vs. sim. Cvar(V) for 1.2V, 130nm device
51
90nm AMOS varactors: Ceff
10x2µm L=0.25µm
L=0.25µm
10x2µm
112×700nm×45nm
Q-Factor
2.0 Q 100 CTM
CBM
Metal 7
DA-MiM
1.5 10
Metal 6
C
Csub Rsub
° SUB
Equivalent circuit used for MiM_Cap
model
HF MIM capacitor equiv. ckt.
use reversed-
biased n-well
for good
substrate
isolation
58
MOM capacitor
CT CB
C OX
Rs Cs
CT CB
Z1
Z2
L R C
CT C OX CB
−1 −1
Cmim =
[ ℑ[−Y 12 ]]
R=RTOPRBO =ℜZ11Z22−Z12−Z21
Rs Cs
−1
[ ℑZ21 ] Rsub =ℜZ21
COX=
60
HF resistor equivalent circuit
STI
63
Using ASITIC to calculate HF equiv. ckt.
parasitic elements of passive components
MIM caps, poly resistors, varactors have identical substrate
network (Rsub, Csub)
MIM caps and poly resistors are realized in the oxide, above the
silicon substrate
width and length and located at the same distance from the
substrate as the MIM cap or poly resistor
64
Summary
Inductors and transformers: main design components available to
HF circuit designers
Unlike transistors, they are almost insensitive to process variation
Inductors and transformers are scalable to at least 200 GHz
Modelling of passives as critical as the transistor model
In Si HF ICs t-line matching should be avoided < 100 GHz
because of large area
Varactors, capacitors and resistors have RLC parasitics which
must be accurately modelled at HF