: ‫اطراف اﻻﯾﺳﻰ‬

: ‫ طرف ﻛﻣﺎ ﯾﻠﻰ‬16 ‫ﺗﺣﺗوى اﻻﯾﺳﻰ ﻋﻠﻰ‬

/ ‫م‬
‫اﺣ‬
‫ﯾ‬ ‫ﻣد‬
‫وﺳ‬
‫ف‬

αϛΎϋέϳϏϝΧΩϣ ϙΎΑΩϳϓϥέΎϘϣ αϛΎϋέϳϏϝΧΩϣ

ϙΎΑΩϳϓϥέΎϘϣ
‫اﻟﻣ‬

αϛΎϋϝΧΩϣ αϛΎϋϝΧΩϣ

ϙΎΑΩϳϔϟ΍
‫ﺻ‬

ϰόΟέϣϟ΍ΩϬΟϟ΍ΝέΧ

Εϳϣϟ΍ϥϣίϟ΍ ϝϭέΗϧϛϟ΍
Εϳϣϟ΍ϥϣίϟ΍ϥέΎϘϣ
‫رى‬

ΔϳΫϐΗϟ΍ΩϬΟ

ΩΩέΗϟ΍ϑΛϛϣ

ΩΩέΗϟ΍ΔϣϭΎϘϣ ϊϣΟϣ
ΏΫΑΫϣ ϝϭέΗϧϛϟ΍

ϊηϣ
ϰοέ΍

ΝέΧέϭΗγίϧ΍έΗ ϊηϣ
ϊϣΟϣ
 TL494
PULSE-WIDTH-MODULATION CONTROL CIRCUITS

D Complete PWM Power-Control Circuitry D, DB, N, NS, OR PW PACKAGE

D Uncommitted Outputs for 200-mA Sink or

(TOP VIEW)

Source Current 1IN+ 1 16 2IN+

D Output Control Selects Single-Ended or 1IN– 2 15 2IN–
Push-Pull Operation FEEDBACK 3 14 REF
D Internal Circuitry Prohibits Double Pulse at DTC 4 13 OUTPUT CTRL
Either Output CT 5 12 VCC
D Variable Dead Time Provides Control Over RT 6 11 C2
Total Range GND 7 10 E2
D Internal Regulator Provides a Stable 5-V C1 8 9 E1

‫م‬
Reference Supply With 5% Tolerance
D Circuit Architecture Allows Easy
Synchronization

/
description

‫اﺣ‬
The TL494 incorporates all the functions required in the construction of a pulse-width-modulation (PWM) control
circuit on a single chip. Designed primarily for power-supply control, this device offers the flexibility to tailor the
power-supply control circuitry to a specific application.

‫ﻣد‬
The TL494 contains two error amplifiers, an on-chip adjustable oscillator, a dead-time control (DTC)
comparator, a pulse-steering control flip-flop, a 5-V, 5%-precision regulator, and output-control circuits.
The error amplifiers exhibit a common-mode voltage range from –0.3 V to VCC – 2 V. The dead-time control
‫ﯾ‬
comparator has a fixed offset that provides approximately 5% dead time. The on-chip oscillator can be bypassed
‫وﺳ‬
by terminating RT to the reference output and providing a sawtooth input to CT, or it can drive the common
circuits in synchronous multiple-rail power supplies.
The uncommitted output transistors provide either common-emitter or emitter-follower output capability. The
TL494 provides for push-pull or single-ended output operation, which can be selected through the
‫ف‬

output-control function. The architecture of this device prohibits the possibility of either output being pulsed twice
during push-pull operation.
The TL494C is characterized for operation from 0°C to 70°C. The TL494I is characterized for operation from
–40°C to 85°C.
‫اﻟﻣ‬

AVAILABLE OPTIONS
PACKAGED DEVICES
‫ﺻ‬

SHRINK THIN SHRINK

TA SMALL PLASTIC SMALL
SMALL SMALL
OUTLINE DIP OUTLINE
OUTLINE OUTLINE
(D) (N) (NS)
(DB) (PW)
‫رى‬

0°C to 70°C TL494CD TL494CN TL494CNS TL494CDB TL494CPW

–40°C to 85°C TL494ID TL494IN — — —
The D, DB, NS, and PW packages are available taped and reeled. Add the suffix R to device type (e.g.,
TL494CDR).
TL494
PULSE-WIDTH-MODULATION CONTROL CIRCUITS

FUNCTION TABLE
INPUT TO
OUTPUT FUNCTION
OUTPUT CTRL
VI = GND Single-ended or parallel output
VI = Vref Normal push-pull operation

‫ﻣدﺧل اﻟﺗﺣﻛم‬

‫ﻣذﺑذب‬
1D

‫م‬
‫ﻣﻔﺎرن اﻟزﻣن اﻟﻣﯾت‬

/
C1
-
+

‫اﺣ‬
1 ‫ﻣﻘﺎرن ﻓﯾدﺑﺎك‬
‫ﻓﻠﯾب ﻓﻠوب‬
+ ‫ﻣﻘﺎرن اﻟﺗﻌدﯾل‬

‫ﻣد‬
‫ﺟﮭد اﻟﺗﺷﻐﯾل‬
2 ‫ﻣﻘﺎرن ﻓﯾدﺑﺎك‬
+
‫ﯾ‬
‫وﺳ‬
‫ﺟﮭد ﻣرﺟﻌﻰ‬
‫ف‬

‫اﻟﻔﯾدﺑﺎك‬
‫ارﺿﻰ‬
‫اﻟﻣ‬
‫ﺻ‬
‫رى‬
 ‫اﻟﺗرﻛﯾب اﻟداﺧﻠﻰ ﻟﻼﯾﺳﻰ ‪494‬‬

‫‪6‬‬
‫‪8‬‬
‫‪1‬‬
‫‪5‬‬
‫‪2‬‬

‫‪7‬‬

‫م‬
‫‪9‬‬
‫‪3‬‬

‫‪/‬‬
‫اﺣ‬
‫‪4‬‬

‫ﯾ‬ ‫ﻣد‬
‫وﺳ‬
‫‪ -‬ﻧظرﯾﺔ ﻋﻣل اﻻﯾﺳﻰ ‪ 494‬ھﻰ ﻗﯾﺎدة او ﺗﺷﻐﯾل اﻟﺗراﻧزﺳﺗورات ﻋﻠﻰ اﻟﺧرج ﺑطرﯾﻘﺗﯾن ﺣﺳب وﺿﻊ ﻣدﺧل‬
‫ف‬

‫اﻟﻛﻧﺗرول ‪: 13‬‬
‫اﻟﻣ‬

‫‪ -1‬ﻓﻠو ﺗم ﺗوﺻﯾﻠﮫ ﺑﺎﻻرﺿﻰ اﺻﺑﺣت اﺣدى ﻣداﺧل داﺋرة اﻻﻧد ‪ 6‬و ‪ 7‬ﻣﻧﺧﻔض اى رﻗﻣﯾﺎ ‪ 0‬وھذا ﯾﻌﻧﻰ ان‬
‫ﺧرﺟﮭﺎ ﺳوف ﯾﻛون ‪ 0‬ﻣﮭﻣﺎ ﻛﺎﻧت ﻗﯾﻣﺔ اﻟطرف اﻟﺛﺎﻧﻰ ﻟﮭﺎ وھذا ﯾؤدى اﻟﻰ ﻧﺗﯾﺟﺔ ان ﺧرج داﺋرﺗﻰ ‪NOR‬‬
‫ﺻ‬

‫ﺳﺻﺑﺢ طول اﻟوﻗت ‪ 1‬وھذا ﯾﻌﻧﻰ ان اﻟﺗراﻧﺳﺗورﯾن ﺳوف ﯾﻌﻣﻼن ﻣﻌﺎ طوال اﻟوﻗت وﻛﺎﻧﮭﻣﺎ ﺗراﻧزﺳﺗور واﺣد‬
‫وﻟن ﯾﻛون اﺣدھﻣﺎ ﻋﻛس اﻻﺧر زﻟذﻟك ﯾﺗم رﺑطﮭﻣﺎ ﻋﻠﻰ اﻟﺗوازى ﻟﻼﺳﺗﻔﺎدة ﻣن ﺗﯾﺎر اﻋﻠﻰ ﺣﯾث ﻛل ﻣﻧﮭﻣﺎ‬
‫ﯾﺗﺣﻣل ‪ 200‬ﻣم اﻣﺑﯾر‬
‫رى‬

‫‪ -‬ﻣﺣﺻﻠﺔ اﻟﺷرح اﻟﺳﺎﺑﻖ ﯾﺑﯾن اﻧﮫ ﺗم ﻋزل داﺋرﺗﻰ اﻻﻧد ‪ AND‬ﻋن داﺋرة اﻟﻔﻠﯾب ﻓﻠوب وﻟم ﯾﻌد ھﻧﺎك اى‬
‫ﺗﺎﺛﯾر ﻟﮭﺎ وﻛﺎﻧﮭﺎ ﻏﯾر ﻣوﺟودة ﺣﯾث ھﻰ اﻟﻣﺳؤوﻟﺔ ﻋن ﺗوﻟﯾد اﻟﻣوﺟﺔ اﻟﻣرﺑﻌﺔ ﻋﻠﻰ ﻗﺎﻋدة ﻛل ﺗراﻧزﺳﺗور‬

‫‪ -2‬اﻟﺣﺎﻟﺔ اﻟﺛﺎﻧﯾﺔ ‪ :‬ﻟو ﺗم رﺑط اﻟﻣدﺧل ‪ 13‬ﺑﺟﮭد ﻣرﺟﻌﻰ ﻣوﺟب ) ‪ 5‬ﻓوﻟت ( ﺳﯾﺻﺑﺢ اﺣد ﻣداﺧل اﻻﻧد ‪6‬‬
‫و ‪ 7‬رﻗﻣﯾﺎ = ‪ 1‬وھذا ﯾﻌﻧﻰ ان ﺧرﺟﮭﺎ ﻟن ﯾﻛون ‪ 0‬طول اﻟوﻗت وﻟﻛﻧﮫ ﺳﯾﺗﻐﯾر ﺑﯾن ‪ 0‬و ‪ 1‬ﺣﺳب ﺣﺎﻟﺔ‬
‫اﻟطرف اﻻﺧر ‪.....‬ﻓﻠو ﻛﺎن اﻟطرف اﻻﺧر ‪ 1‬ﺳﯾﻛون ﺧرﺟﮭﺎ ‪ 1‬وﻟو ﻛﺎن ‪ 0‬ﺳﯾﻛون ﺧرﺟﮭﺎ ‪ 0‬وﻋﻠﯾﮫ ﺑﺗﻠك‬
‫اﻟطرﯾﻘﺔ ﻛﺎن داﺋرة اﻻﻧد ‪ 6‬او ‪ 7‬اﺻﺑﺣت ﻣﺟرد ﻧﺎﻗل ﻟﺣﺎﻟﺔ اﻟطرف اﻻﺧر ﻟﮭﺎ ﺣﺳب ﻗﯾﻣﺗﮫ وھو اﻟﻘﺎدم ﻣن‬
‫ﺧرج اﻟﻔﻠﯾب ﻓﻠوب وﻋﻠﯾﮫ اﺻﺑﺣت اﻟﻔﻠﯾب ﻓﻠوب ﻓﻌﺎﻟﺔ وﺗﺗﺣﻛم ﻓﻰ ﺗﺷﻐﯾل اﻻﺗﻧﯾن ﺗراﻧﺳﺗور‬
 ‫‪/‬‬ ‫م‬
‫‪ -‬ﻋﻧد رﺑط اﻟطرف ‪ 13‬ﺑﺎﻟﺟﮭد اﻟﻣرﺟﻌﻰ ﺗﺻﺑﺢ اﻻﯾﺳﻰ ﻟﮭﺎ ﺧرﺟﯾن اﺣدھﻣﺎ ﻋﻛس اﻻﺧر اى ﺗﻌﻣل‬

‫اﺣ‬
‫ﺑﻧظﺎم اﻟﺑوش ﺑول ﺑﯾﻧﻣﺎ اذا رﺑط ﺑﺎﻻرﺿﻰ اﺻﺑﺣت ﻟﮭﺎ ﺧرج واﺣد ﻓﻘط‬

‫ﯾ‬ ‫ﻣد‬
‫‪ -3‬اﻟﻧﻘطﺔ اﻟﺛﺎﻟﺛﺔ اﻟﻣﮭﻣﺔ ‪ :‬ان اﻟﺗراﻧزﺳﺗورات ﺳوف ﺗﺗوﻗف ﻟو ﻛﺎن ﺧرج داﺋرة ‪ OR‬ﯾﺳﺎوى ‪1‬‬
‫وﺳ‬
‫وذﻟك ﻻن ﻟو ﺧرﺟﮭﺎ = ‪ 1‬ﺳوف ﯾدﺧل ﻋﻠﻰ داﺋرة ‪ NOR‬وھذا ﯾﺟﻌل ﺧرﺟﮭﺎ ‪ 0‬ﻣﮭﻣﺎ ﻛﺎﻧت ﻗﯾﻣﺔ‬
‫اﻟطرف اﻻﺧر ﻣﺎ ﯾؤدى ﻟوﻗف ﺗراﻧزﺳﺗورات اﻟﺧرج ﻋن اﻟﻌﻣل‬
‫ف‬

‫‪ -‬وﻋﻠﯾﮫ ﻣن ھذا اﻟﻣﻧطﻠﻖ ﺳوف ﻧﺗوﺻل ﻟﻛﯾﻔﯾﺔ ﺗﺣﻛم اﻻﯾﺳﻰ ﻓﻰ اﺗﺳﺎع ﻣوﺟﺔ اﻟﺧرج ﻋﻧد اﻟﻧظر اﻟﻰ‬
‫ﻣداﺧل داﺋرة ‪ OR‬رﻗم ‪ 5‬ﺳﻧﺟد ان اﺣدھم ﻗﺎدم ﻣن ﻣﻘﺎرن اﻟزﻣن اﻟﻣﯾت واﻟطرف اﻻﺧر ﻗﺎدم ﻣن‬
‫اﻟﻣ‬

‫ﻣﻘﺎرن اﻟﺗﻌدﯾل وﻋﻠﯾﮫ ﻧﻔﮭم ﻣن ذﻟك ان ﻣﻘﺎرن اﻟزﻣن اﻟﻣﯾت ﯾﺳﺗطﯾﻊ وﻗف اﻟﺗراﻧزﺳﺗورات واﻟﺗﺣﻛم ﻓﻰ‬
‫اﻟدﯾوﺗﻰ ﺳﯾﻛل ﻋﻧدﻣﺎ ﯾﻛون ﺧرﺟﮫ ﻋﺎﻟﻰ وﻛذﻟك ﺳﯾﻔﻌل ﻣﻘﺎرن اﻟﺗﻌدﯾل وھذا ﯾﻌﻧﻰ اﻧﮫ ﯾوﺟد ﻟدﯾﻧﺎ ‪2‬‬
‫ﻣﻘﺎرن ﺗﻌدﯾل وﻟﻛن اﺣدھﻣﺎ ﺑﻣﺳﻣﻰ اﺧر ﯾﺳﻣﻰ ﻣﻘﺎرن اﻟزﻣن اﻟﻣﯾت ﻻﻧﮫ ﯾﺗم ﺿﺑطﮫ ﻋﻠﻰ ﻗﯾﻣﺔ ﺛﺎﺑﺗﺔ‬
‫ﺻ‬

‫طوال اﻟوﻗت ﻟو اردﻧﺎ دﯾوﺗﻰ ﺳﯾﻛل ﻣﻌﯾن ﺑﯾﻧﻣﺎ ﻣﻘﺎرن اﻟﺗﻌدﯾل اﻟﻔﻌﻠﻰ ﯾﻌﻣل طوال اﻟوﻗت ﻟﯾﺣﺎﻓظ ﻋﻠﻰ‬
‫ﺗﺛﺑﯾت ﺟﮭد اﻟﺧرج ﻋن طرﯾﻖ اﻻﺷﺎرات اﻟﻘﺎدﻣﺔ ﻟﮫ ﻣن ﻣﻘﺎرﻧﺎت اﻟﻔﯾدﺑﺎك اﻟﺗﻰ ﺗﺗﺣﺳس اﻟﺧرج ﺳواء‬
‫رى‬

‫اﻟﺗﯾﺎر او اﻟﺟﮭد‬

‫‪ -‬ﻣﻘﺎرن اﻟزﻣن اﻟﻣﯾت ﺗم ﺿﺑطﮫ ﻋﻠﻰ اﻗل ﻗﯾﻣﺔ ﻋﻧد رﺑطﮫ ﺑﺎﻻرﺿﻰ وذﻟك ﺑوﺿﻊ ﺑطﺎرﯾﺔ ﻗﯾﻣﺗﮭﺎ ‪0.1‬‬
‫ﻓوﻟت ﺣﺗﻰ ﯾﺿﻣن اﻟﻣﺻم ان ھﻧﺎك ﻓﺎرق زﻣﻧﻰ ﺑﯾن ﺗﺷﻐﯾل اﻟﺗراﻧزﺳﺗور اﻟﻌﻠوى واﻟﺳﻔﻠﻰ ﻣﻘداره‬
‫ﺗﻘرﯾﺑﺎ ‪ 3‬ﻓﻰ اﻟﻣﯾﺔ ﻣن اﻟزﻣن اﻟﻛﻠﻰ وﻟو اردﻧﺎ زﯾﺎدة ھذه اﻟﻘﯾﻣﺔ ﻧﻘوم ﺑزﯾﺎدة اﻟﺟﮭد ﻋﻠﻰ ھذا اﻟﻣدﺧل‬
‫ﺑرﺑطﮫ اﻟﻰ ﻣﺻدر ﺟﮭد ﺧﺎرﺟﻰ ﻣﺎﺧوذ ﻣن اﻟﻧﻘطﺔ ‪ 14‬وھﻰ ﻧﻘطﺔ اﻟﺟﮭد اﻟﻣرﺟﻌﻰ‬

‫‪ -‬ﻧﻌود اﻟﻰ ﻣﻘﺎرن اﻟﺗﻌدﯾل ﻟﻧﺟد ان ھﻧﺎك ‪ 3‬ﻣداﺧل ﯾﺗﺣﻛﻣون ﻓﯾﮫ وھم ﺧرج ﻣﻘﺎرﻧﻰ اﻟﻔﯾدﺑﺎك ‪ 1‬و ‪2‬‬
‫واﻟﻣدﺧل رﻗم ‪ 3‬ﻟﻼﯾﺳﻰ ﺣﯾث ﯾﻣﻛن رﺑط ﻣﺟزئ ﺟﮭد ﻋﻠﯾﮫ ورﺑطﮫ اﻟﻰ اﻟطرف ‪ 14‬ﻟﻠﺗﺣﻛم ﻓﻰ ﺗﻌدﯾل‬
‫اﻻﺗﺳﺎع ‪....‬ﺗم وﺿﻊ داﯾودﯾن ﻋﻠﻰ ﺧرج اﻟﻣﻘﺎرﻧﯾن ﻟﻔﺻل ﺧرﺟﮭﻣﺎ ﻋن ﺑﻌض‬
 TL494
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS074D – JANUARY 1983 – REVISED MAY 2002

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 V
Amplifier input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3 V
Collector output voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 V
Collector output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA
Package thermal impedance, θJA (see Note 2 and 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

‫م‬
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

/
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the network ground terminal.

‫اﺣ‬
2. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
3. The package thermal impedance is calculated in accordance with JESD 51-7.

‫ﻣد‬
recommended operating conditions ‫ﻗﯾم اﻟﺗﺷﻐﯾل اﻟﺗﻰ ﯾوﺻﻰ ﺑﮭﺎ‬ ‫ادﻧﻰ‬ ‫اﻋﻠﻰ‬
MIN MAX UNIT
VCC Supply voltage ‫ﻣﺻدر اﻟﺟﮭد‬ 7 40 V
VI Amplifier input voltage
‫ﯾ‬ ‫ﺟﮭد دﺧل اﻟﻣﻛﺑر‬ –0.3 VCC–2 V
‫وﺳ‬
VO Collector output voltage ‫اﻗﺻﻰ ﺟﮭد ﻋﻠﻰ ﻣﺟﻣﻊ اﻟﺗراﻧزﺳﺗور‬ 40 V
Collector output current (each transistor) ‫اﻗﺻﻰ ﺗﯾﺎر ﯾﻣر ﻓﻰ ﻣﺟﻣﻊ ﻛل ﺗراﻧزﺳﺗور‬ 200 mA
Current into feedback terminal ‫اﻗﺻﻰ ﺗﯾﺎر ﯾﻣر ﻓﻰ ﺧط اﻟﻔﯾدﺑﺎك‬ 0.3 mA
fosc Oscillator frequency ‫ﺣدود اﻟﺗردد اﻟﺗﻰ ﺗﻌﻣل ﻋﻠﯾﮭﺎ اﻻﯾﺳﻰ‬ 1 300 kHz
‫ف‬

CT Timing capacitor ‫ﻗﯾم اﻟﻣﻛﺛف‬ 0.47 10000 nF

RT Timing resistor ‫ﻗﯾم اﻟﻣﻘﺎوﻣﺔ‬ 1.8 500 kΩ

TA Operating
O erating free-air temperature
tem erature ‫درﺟﺔ ﺣرارة اﻟﺗﺷﻐﯾل‬ TL494C 0 70
°C
TL494I –40 85
‫اﻟﻣ‬
‫ﺻ‬
‫رى‬
 ‫‪TL494‬‬
‫‪PULSE-WIDTH-MODULATION CONTROL CIRCUITS‬‬

‫‪PARAMETER MEASUREMENT INFORMATION‬‬

‫‪VCC = 15 V‬‬

‫‪12‬‬ ‫‪150 Ω‬‬ ‫‪150 Ω‬‬

‫‪2W‬‬ ‫‪2W‬‬
‫‪VCC‬‬
‫‪4‬‬
‫‪C1‬‬
‫‪8‬‬
‫‪Output 1‬‬ ‫ﺧرج ‪1‬‬
‫‪Test‬‬ ‫‪DTC‬‬
‫‪Inputs‬‬ ‫‪3‬‬ ‫‪9‬‬
‫‪FEEDBACK‬‬ ‫‪E1‬‬
‫‪12 kΩ‬‬
‫‪6‬‬ ‫‪11‬‬
‫‪RT‬‬ ‫‪C2‬‬ ‫ﺧرج ‪Output 2 2‬‬

‫م‬
‫‪5‬‬ ‫‪10‬‬
‫‪CT‬‬ ‫‪E2‬‬
‫‪0.01 µF‬‬

‫‪/‬‬
‫‪1‬‬
‫‪1IN+‬‬
‫ھﻧﺎ ﺗم ﺗﻌطﯾل ﻣﻘﺎرﻧﺎت اﻟﻔﯾدﺑﺎك ﺑرﺑط اﻟﻣداﺧل اﻟﻣوﺟﺑﺔ ﻟﮭﺎ‬ ‫‪2‬‬
‫ﺑﺎﻻرﺿﻰ واﻟﺳﺎﻟﺑﺔ اﻟﻰ ﺟﮭد ﻣرﺟﻌﻰ ﻟﺟﻌل ﻣداﺧﻠﮭﺎ اﻟﺳﺎﻟﺑﺔ داﺋﻣﺎ‬ ‫–‪1IN‬‬ ‫‪Error‬‬
‫‪16‬‬

‫اﺣ‬
‫اﻋﻠﻰ ﻣن اﻟﻣوﺟﺑﺔ ﻟﺿﻣﺎن ﻋدم ﺧروج اﺷﺎرة ﻋﺎﻟﯾﺔ ﻣﻧﮭﺎ‬ ‫‪2IN+‬‬ ‫‪Amplifiers‬‬
‫‪15‬‬
‫–‪2IN‬‬
‫‪13‬‬ ‫‪OUTPUT‬‬ ‫‪14‬‬
‫‪REF‬‬

‫ﻣد‬
‫‪CTRL‬‬
‫‪GND‬‬ ‫ﺗم رﺑط ‪ 13‬ﺑﺎﻟﺟﮭد اﻟﻣرﺟﻌﻰ ﻟﺗﻌﻣل‬
‫‪50 kΩ‬‬ ‫اﻻﯾﺳﻰ ﺑﻧظﺎم ﺧرﺟﯾن‬
‫‪7‬‬

‫ﯾ‬
‫وﺳ‬
‫‪TEST CIRCUIT‬‬

‫‪VCC‬‬
‫اﻟﻣوﺟﺔ ﻋﻠﻰ ﻣﺟﻣﻊ ‪1‬‬ ‫‪Voltage‬‬
‫ف‬

‫‪at C1‬‬
‫‪0V‬‬

‫‪VCC‬‬
‫‪ Voltage‬اﻟﻣوﺟﺔ ﻋﻰ ﻣﺟﻣﻊ ‪2‬‬
‫‪at C2‬‬
‫‪0V‬‬
‫اﻟﻣ‬

‫‪ Voltage‬ﻣوﺟﺔ ﺳن اﻟﻣﻧﺷﺎر ﻋﻠﻰ اﻟﻣﻛﺛف‬

‫‪at CT‬‬
‫ﺻ‬

‫‪Threshold Voltage‬‬
‫اﻟزﻣن اﻟﻣﯾت‬ ‫‪DTC‬‬

‫‪0V‬‬
‫رى‬

‫‪Threshold Voltage‬‬
‫اﻟﻔﯾدﺑﺎك‬
‫‪FEEDBACK‬‬

‫‪0.7 V‬‬
‫‪0%‬‬
‫اﻟدﯾوﺗﻰ ﺳﯾﻛل‬ ‫‪Duty Cycle‬‬ ‫‪0%‬‬
‫‪MAX‬‬

‫‪VOLTAGE WAVEFORMS‬‬

‫‪Figure 1. Operational Test Circuit and Waveforms‬‬

‫ﻣﻠﺣوظﺔ ﻣﮭﻣﺔ ﺟدا ‪ :‬ﺳﺗﻼﺣظ ﻓﻰ ﺷﻛل ﻣوﺟﺔ اﻟﺧرج ﻋﻠﻰ ﻣﺟﻣﻊ اﻟﺗراﻧزﺳﺗور ‪ 1‬و ‪ 2‬ان اﻟﻣوﺟﺗﯾن ﻟﯾﺳت ﻣﺗﻌﺎﻛﺳﺗﯾن ﺗﻣﺎﻣﺎ‬
‫ﻓﻰ اﻟﺷﻛل ﻛﻣﺎ ھو اﻟﺣﺎل ﻣﻊ ﺧرج اﻻﯾﺳﻰ ‪ 4047‬ﺣﯾث ﻛﺎن اﻻﻧﻌﺎﻛس ﻣﺗﻣﺎﺛل ﺗﻣﺎﻣﺎ وذﻟك ﻻن ھﻧﺎ ﯾوﺟد ﻧظﺎم ﺗﻌدﯾل ﻓﻰ‬
‫اﻻﺗﺳﺎع واﻟذى ﯾﻐﯾر ﻣن ﺷﻛل اﻟﻣوﺟﺔ اﻟﺧﺎرﺟﺔ ﻣن اﻟﻔﻠﯾب ﻓﻠوب ﻋن طرﯾﻖ ﺧرج داﺋرة ‪ OR‬ﺣﯾث ﯾذھب ﻣﺑﺎﺷرة اﻟﻰ‬
‫ﻣدﺧﻠﻰ داﺋرﺗﻰ ‪ NOR‬وﯾوﻗف اﻟﺗراﻧزﺳﺗورات ﻓﻰ اى ﻟﺣظﺔ ﯾرﺗﻔﻊ ﻓﯾﮭﺎ ﺟﮭد او ﺗﯾﺎر اﻟﺧرج‬
 ‫ﺗﺗﻛون ﻣن‪:‬‬
‫‪ -‬داﺋرة اﻟﺗﺣﻛم ﻓﻰ ﺟﮭد اﻟﺧرج‬
‫‪ -‬ﻣﻘﺎرن اﻟزﻣن اﻟﻣﯾت ﺑﯾن اﻟﻣوﺟﺗﯾن‬ ‫‪ -‬داﺋرة ﻓﻠﯾب ﻓﻠوب‬

‫‪ -‬داﺋرة ﺟﮭد ﻣرﺟﻌﻰ ‪ 5‬ﻓوﻟت‬ ‫‪ 2 -‬ﻣﻘﺎرن ﻟﻠﺧطﺎ او اﻟﻔﯾدﺑﺎك‬

‫‪ -‬ﻣﻘﺎرن اﻟﺗﺣﻛم ﻓﻰ اﻻﺗﺳﺎع‬ ‫‪ -‬ﻣذﺑذب‬

‫‪ -‬ﺗﻌﻣل ﻋﻠﻰ ﺗردد ﺑﯾن ‪ 1‬ﻛﯾﻠو و ‪ 300‬ﻛﯾﻠو ھﯾرﺗز‬

‫‪ -‬ﻣﻘﺎرن اﻟزﻣن اﻟﻣﯾت ‪ DTC‬ﯾﻌطﻰ ﻧﺳﺑﺔ ‪ %5‬ﻣن اﻟزﻣن اﻟﻣﯾت وﻛل ﻣن ﻣﻘﺎرﻧﻰ اﻟﻔﯾدﺑﺎك ﯾﻌطﯾﺎن‬

‫م‬
‫ﺟﮭد ﻣن ‪ 0.3-‬ﻓوﻟت اﻟﻰ ﺟﮭد اﻟﺗﺷﻐﯾل ﻧﺎﻗص ‪ 2‬ﻓوﻟت ‪Vcc-2‬‬

‫‪/‬‬
‫‪ -‬ﻋﻧد اﻧﺷﺎء ﻣوﺟﺔ ﻣﺛﻠﺛﺔ ﻋﻠﻰ اطراف اﻟﻣﻘﺎوﻣﺔ ‪ RT‬واﻟﻣﻛﺛف اﻟﺧﺎرﺟﻰ ‪ CT‬ﺑواﺳطﺔ اﻟﺟﮭد اﻟﻣرﺟﻌﻰ‬

‫اﺣ‬
‫ﻓﺎن اﻟﻣذﺑذب ﯾﻧﺷﺎ ﻣوﺟﺔ ﻣرﺑﻌﺔ ﻋﻠﻰ اﻟﺧرج‬

‫‪ -‬ﻟﻼﯾﺳﻰ ‪ 494‬ﻋدة اﺳﺗﺧداﻣﺎت ﻋدﯾدة ﻣﺛل ﺑﺎور ﺳﺑﻼى اﻟﻣﯾﻛرو وﯾف واﻟﻛﻣﺑﯾوﺗر واﻟﻐﺳﺎﻻت واﻧﻔرﺗر‬
‫ﯾ‬ ‫ﻣد‬ ‫اﻟﺧﻼﯾﺎ اﻟﺷﻣﺳﯾﺔ وﻛﺎﺷف اﻟدﺧﺎن وﺧﻼﻓﮫ‬
‫وﺳ‬
‫ﻣﻘدﻣﺔ ﻋن اﻻﯾﺳﻰ ‪: TL494‬‬

‫ھﻰ ﻋﺑﺎرة ﻋن اﯾﺳﻰ ﺗﺗﻌﺎﻣل ﻣﻊ ﻛل اﻟدواﺋر اﻟﺗﻰ ﺗﻌﻣل ﺑﻧظرﯾﺔ ﺗﻌدﯾل اﻻﺗﺳﺎع ‪ -PWM‬وھﻰ‬
‫ف‬

‫ﺗﺗﻛون ﻣن ‪ 2‬ﻣﻘﺎرن اﻟﺧطﺎ او ﻣﺎﯾﺳﻣﻰ ﺑﻣﻘﺎرﻧﺎت اﻟﻔﯾدﺑﺎك وﻣذﺑذب وداﺋرة ﻓﻠﯾب ﻓﻠوب وداﺋرة ﻣﻧظم‬
‫ﺟﮭد ﻣرﺟﻌﻰ ‪ 5‬ﻓوﻟت وﻣﻘﺎرن اﻟزﻣن اﻟﻣﯾت وﻣﻘﺎرن ﺗﻌدﯾل اﻻﺗﺳﺎع‬
‫اﻟﻣ‬

‫‪ -‬اﻟﺗردد اﻟذى ﯾﻣﻛن اﻟﺣﺻول ﻋﻠﯾﮫ ﻣن اﻻﯾﺳﻰ ﯾﺗراوح ﺑﯾن ‪ 1‬ﻛﯾﻠو و ‪ 300‬ﻛﯾﻠو ھﯾرﺗز‬
‫ﺻ‬
‫رى‬
 ‫ھﻧﺎك اﻟﻌدﯾد ﻣن ﻣودﯾﻼت ‪ TL494‬ﻣﻧﮭﺎ اﻟﻣودﯾﻼت اﻟﺗﺎﻟﯾﺔ ‪:‬‬

‫م‬
‫ﻣﻌدﻻت اﻟﺟﮭد واﻟﺗﯾﺎر ﻟﻼﯾﺳﻰ ‪: TL494‬‬

‫‪/‬‬
‫اﺣ‬
‫اﻗﺻﻰ ﺟﮭد ﺗﺷﻐﯾل‬

‫اﻗﺻﻰ ﺟﮭد ﻋﻠﻰ اﻟﻣﺟﻣﻊ‬

‫اﻗﺻﻰ ﺗﯾﺎر ﻟﻠﻣﺟﻣﻊ‬
‫ﯾ‬ ‫ﻣد‬
‫وﺳ‬
‫اﻟﻘدرة‬
‫ف‬

‫درﺟﺔ ﺣرارة اﻟﺗﺷﻐﯾل‬

‫اﻟﻣ‬
‫ﺻ‬

‫اﻟﻘﯾم اﻟﻣوﺻﻰ ﺑﮭﺎ ﻟﻠﺗﺷﻐﯾل اﻟﺟﯾد ﻟﻼﯾﺳﻰ ﻣن اﻟداﺗﺎﺷﯾت‬

‫رى‬

‫ﻣﺻدى اﻟﺟﮭد‬
‫ﺟﮭد دﺧل اﻟﻣﻛﺑر‬
‫ﺟﮭد اﻟﻣﺟﻣﻊ‬
‫ﺗﯾﺎر اﻟﻣﺟﻣﻊ‬
‫ﺗﯾﺎر اﻟﻔﯾدﺑﺎك‬
‫ﻣﻛﺛف اﻟﺗوﻗﯾت‬
‫ﻣﻘﺎوﻣﺔ اﻟﺗوﻗﯾت‬
‫ﺗردد اﻟﻣذﺑذب‬
‫ﺣرارة اﻟﺗﺷﻐﯾل‬
 ‫ﻣﺟﻣﻊ ‪1‬‬
‫‪6‬‬ ‫اﻟﺗﺣﻛم ﻓﻰ اﻟﺧرج‬
‫اﻟﻣذﺑذب‬ ‫‪13‬‬ ‫‪8‬‬

‫‪5‬‬ ‫ﺧرج‬
‫داﺗﺎ‬
‫‪9‬‬ ‫ﻣﺷﻊ‪1‬‬
‫ﻓﻠﯾب ﻓﻠوب‬
‫ﻣﻘﺎرن اﻟزﻣن اﻟﻣﯾت‬
‫‪11‬‬ ‫ﻣﺟﻣﻊ‪2‬‬
‫‪4‬‬ ‫ﺳﺎﻋﺔ‬
‫ﻋﻛس اﻟﺧرج‬

‫م‬
‫ﻣﺷﻊ ‪2‬‬
‫‪10‬‬
‫ﻣﻘﺎرن اﻻﺗﺳﺎع‬

‫‪/‬‬
‫ﻣﺻدر اﻟﺗﻐذﯾﺔ‬
‫‪12‬‬

‫اﺣ‬
‫ﻣﻘﺎرن اﻟﻔﯾدﺑﺎك‬
‫‪1‬‬
‫داﺋرة اﻟﺟﮭد اﻟﻣرﺟﻌﻰ‬ ‫ﺟﮭد ﻣرﺟﻌﻰ‬
‫‪2‬‬ ‫‪14‬‬

‫‪16‬‬

‫‪15‬‬
‫ﯾ‬ ‫ﻣد‬ ‫‪7‬‬
‫ارﺿﻰ‬
‫وﺳ‬
‫ﻣﻘﺎرن اﻟﻔﯾدﺑﺎك‬

‫ﻣدﺧل ﻣﻘﺎرن اﻟﺗﻌدﯾل‬

‫اﻟﺗﺣﻛم ﻓﻰ اﻻﺗﺳﺎع‬
‫ف‬

‫ﻣﺧطط داﺧﻠﻰ اﻛﺛر وﺿوﺣﺎ‬

‫اﻟﻣ‬
‫ﺻ‬
‫رى‬
 ‫ﻣﺧطط اﺧر ﻟﻠﺷرح‬

‫‪/‬‬ ‫م‬
‫‪D‬‬ ‫‪Q‬‬
‫‪1.1‬‬

‫اﺣ‬
‫‪f‬‬
‫‪R‬‬ ‫‪C‬‬ ‫‪C‬‬ ‫‪Q‬‬

‫ﯾ‬ ‫ﻣد‬
‫وﺳ‬
‫ﻣﻧظم اﻟﺟﮭد‬
‫اﻟﻣرﺟﻌﻰ‬

‫ف‬
‫اﻟﻣ‬
‫ﺻ‬
‫رى‬
 ‫ﻣﺧطط اﺧر ﺑﺗرﻛﯾب داﺧﻠﻰ ﻣﺧﺗﻠف‬

‫م‬
‫ﻣدﺧل اﻟﻛﻧﺗرول‬

‫‪/‬‬
‫اﺣ‬
‫ﻟﻠﻣﻘﺎوﻣﺔ‬

‫ﻣد‬
‫اﻟﻣذﺑذب‬ ‫ﻓﻠﯾب ﻓﻠوب‬
‫ﻟﻠﻣﻛﺛف‬

‫ﯾ‬
‫وﺳ‬
‫ﻣﻘﺎرن اﻟزﻣن اﻟﻣﯾت‬
‫‪-‬‬
‫ﺟﮭد ﻣرﺟﻌﻰ‬

‫ف‬
‫ﻣدﺧل اﻟزﻣن اﻟﻣﯾت‬
‫ﻣﻘﺎرن اﻟﺗﻌدﯾل‬

‫ﻣﺻدر ﺗﯾﺎر‬ ‫ﻣﻧظم اﻟﺟﮭد اﻟﻣرﺟﻌﻰ‬ ‫ﺟﮭد اﻟﺗﻐذﯾﺔ‬

‫اﻟﻣ‬
‫ﺻ‬
‫ارﺿﻰ‬

‫ﻣﻘﺎرن ﺗﺣﺳس اﻟﺟﮭد‬

‫رى‬

‫ﻣﻘﺎرن ﺗﺣﺳس اﻟﺗﯾﺎر‬

 ‫ﻣﻠف ﺷرح اﺧر‬

‫اﻋﻠﻰ ﻣن ﺟﮭد اﺷﺎرة اﻟﺗﺣﻛم‬Abstract

‫ﯾﻛون اﻟﺧرج ﻣوﺟود ﻋﻧدﻣﺎ ﺗﻛون ﺟﮭد ﻣوﺟﺔ ﺳن اﻟﻣﻧﺷﺎر‬
In this application report, the TlA94 switching power supply control is discussed
in ‫ﻋﻠﻰ‬
detail.‫ﻣرﺑوط‬ ‫ﺗراﻧزﺳﺗور‬
A general ‫ﺣﯾث ﻛل‬
overview of the‫اﻟﺧرج‬ ‫ﺗراﻧزﺳﺗورى‬
device's ‫ﺗﺷﻐﯾل‬
architecture ‫ﺑﺎﻟﺗﺣﻛم ﻓﻰ‬
presents ‫ﻓﻠوب‬functions
the primary ‫ﺗﻘوم داﺋرة اﻟﻔﻠﯾب‬
‫ﻣﺧرج اﻟﻔﻠﯾب ﻓﻠوب واﻟﻌﺎﻛس ﻟﮫ اى ﻋﻧدﻣﺎ ﯾﻛون اﺣدھﻣﺎ ﺷﻐﺎل ﯾﻛون اﻻﺧر ﻣﺗوﻗف‬
contained in the 16-pin dual-in-line package and its features. An in-depth study of each
of the device's primary building blocks highlights the versatility and limitations of the
control circuit and gives a thorough understanding of their interrelationship. Applying the
control circuit to several basic applications demonstrates the circuits' usefulness and outlines
‫ﻣﻘﺎرﻧﺎت‬
some ‫واﻻﺧرى داﺋرة‬
still unresolved ‫ اﺣدھﻣﺎ داﺋرة اﻟﺗﺣﻛم ﻓﻰ اﻟزﻣن اﻟﻣﯾت‬: ‫ﺗﺎﺗﻰ اﺷﺎرة اﻟﺗﺣﻛم ﻣن ﻣﺻدرﯾن‬
problems.
‫اﻟﺧطﺎ او اﻟﻔﯾدﺑﺎك‬

‫م‬
Introduction

/
Over the past few years, a series of monolithic integrated circuits for the control
‫ﯾﺗم رﺑط ﺟﮭد‬
of switching ‫ﺣﯾث‬supplies
power ‫اﻟزﻣن اﻟﻣﯾت‬ ‫ﻟﻣﻘﺎرن‬
have been ‫اﻟﻣدﺧل اﻻﺧر‬
introduced. One ‫اﻟﻰ‬ ‫ اﻟﻣﯾت‬the
of these, ‫اﻟزﻣن‬ ‫ﻣدﺧل‬combines
TlA94, ‫ ﯾﺗم ﻣﻘﺎرﻧﺔ ﺟﮭد‬-

‫اﺣ‬
many of the features previously requiring several control circuits. The TlA94 simplifies
many design problems with its unique architecture. ‫اﻟﻣدﺧل‬
It is the‫ھذا‬ ‫ﻓوﻟت ﻋﻠﻰ‬
purpose ‫ﻣم‬application
of this 100 ‫ﺑطﺎرﯾﺔ ﻗﯾﻣﺗﮫ‬
report to give the reader a thorough understanding of the TlA94, its features, its

‫ﻣد‬
‫ ﻋﻧدﻣﺎ ﯾﺗم رﺑط ﻣدﺧل اﻟزﻣن اﻟﻣﯾت اﻟﻰ اﻻرﺿﻰ ﻓﺎن اﺷﺎرة ﺗﺧرج ﻣن اﻟﻣﻘﺎرن ﺗوﻗف اﻟﺧرج ﻓﻰ‬-
performance characteristics, and its limitations.

‫ وھذا ﯾﺟﻌل ﻧﺳﺑﺔ اﻟزﻣن اﻟﻣﯾت‬The‫ ﻓوﻟت‬Basic

‫ ﻣم‬110Device
‫اﻟﻔﺗرة اﻟﺗﻰ ﯾﻛون ﻓﯾﮭﺎ ﻣوﺟﺔ ﺳن اﻟﻣﻧﺷﺎر اﻗل ﻣن‬
‫اﻻﯾﺳﻰ ﻋﻠﯾﮭﺎ‬ ‫ ﻣن اﻟزﻣن اﻟﻛﻠﻰ ﻟﻣوﺟﺔ اﻟﺧرج وھﻰ اﻗل ﻧﺳﺑﺔ ﺗوﻗف ﻟﻠﺧرج ﯾﻣﻛن ﺑرﻣﺟﺔ‬3 % ‫ﻗﯾﻣﺗﮭﺎ‬
‫ﯾ‬
‫وﺳ‬
The design of the TlA94 not only incorporates the primary building blocks required
for‫اﻟﻰ‬
the0control
‫ﺟﮭد ﻣن‬of a‫ﺑﻣﺟزئ‬ ‫اﻻرﺿﻰ‬
switching ‫ﻣن‬supply
power ‫ﺧﺎرﺟﻰ ﺑدﻻ‬
but also‫ﺟﮭد‬ ‫اﻟﺧرج ﻋﻠﻰ‬
addresses many‫ﺑرﺑط‬
basic‫اﻟﻧﺳﺑﺔ‬ ‫ ﺗﻠك‬and
problems ‫وﯾﻣﻛن زﯾﺎدة‬
reduces the amount of additional circuitry required in a total design. Figure 1 shows ‫ﻓوﻟت‬
a 3.3
block diagram of the TlA94.
‫ف‬

Principle of Operation
‫ ﯾﻘوم اﻟﻣﻘﺎرن ﺑﻣﻘﺎرﻧﺔ اﺷﺎرة اﻟﻔﯾدﺑﺎك اﻟﻘﺎدﻣﺔ ﻋﻠﻰ ﻣدﺧﻠﮫ اﻟﻣوﺟب ﻣن ﺛﻼﺛت اﺗﺟﺎھﺎت ﻣﻊ‬-
‫اﺷﺎرة ﺳن اﻟﻣﻧﺷﺎر ﻟﻠﻣذﺑذب‬
The TlA94 is a fixed-frequency pulse-width-modulation (PWM) control circuit.
‫اﻟﻣ‬

Modulation of output pulses is accomplished by comparison of the sawtooth waveform,

created by the internal oscillator on the timing capacitor (CT), to either of two control
: ‫ھم‬ ‫اﻟﺗﻌدﯾل‬
of ‫ﻟﻣﻘﺎرن‬ ‫اﻟﻣوﺟب‬ ‫اﺗﺟﺎھﺎت ﻟﻣدﺧل‬
voltage ‫ اﻟﺛﻼث‬-
‫ﺻ‬

signals. The output stage is enabled during that portion time when the sawtooth
is greater than the control signals. As the control signals increase, the period of time the
sawtooth input is greater decreases; therefore, the output pulse duration decreases. A pulse-
3 two
‫اﻟﻔﯾدﺑﺎك‬
output‫ﻣدﺧل‬ ‫ ﻣﺑﺎﺷر ﻣن‬- 1
‫رى‬

steering flip-flop alternately directs the modulated pulse to each of the transistors.
Figure 2 illustrates the relationship between the pulses 1 and
‫ رﻗم‬signals.
( ‫ ﺧرج ﻣﻘﺎرن اﻟﻔﯾدﺑﺎك ) اﻟﺧطﺄ‬- 2
The control signals are derived from two sources: the dead-time (off-time) control
circuit and the error amplifier circuit. The dead-time-control input2is‫رﻗم‬ ‫اﻟﻔﯾدﺑﺎك‬directly
compared ‫ﺧرج ﻣﻘﺎرن‬ -3
by the dead-time-control comparator. This comparator has a fixed 100-mV offset. With
the control input biased to ground, the output is inhibited during the portion of time the
sawtooth waveform is below 110 mV. This provides a preset dead time of approximately
3%, which is the minimum dead time that can be programmed. The PWM comparator
compares the control signal created by the error amplifiers. One function of the error

1
‫‪ -‬ﻓﻰ اﻟﺑداﯾﺔ ﻋﻧدﻣﺎ ﺗﺑدء اﻻﯾﺳﻰ اﻟﻌﻣل ﯾﻛون ﺟﮭد اﺷﺎرة ﺳن اﻟﻣﻧﺷﺎر اﻟﺧﺎرﺟﺔ ﻣن اﻟﻣذﺑذب وداﺧﻠﺔ ﻋﻠﻰ اﻟﻣدﺧل اﻟﻌﺎﻛس اﻗل ﻣن ‪ 0.1‬ﻓوﻟت‬
‫ﯾﻛون ﺧرج اﻟﻣﻘﺎرن ‪ A‬ﻋﺎﻟﻰ ﻣﻣﺎ ﯾﺟﻌل اﻟﻔﻠﯾب ﻓﻠوب ﯾﻌﻣل وﺗﻛون ااﻻﺷﺎرات ﻋﻠﻰ ﻣداﺧل اﻟﺗراﻧزﺳﺗورﯾن ‪ 0‬اى ﻣﺗوﻗﻔﺎن‬

‫‪OUTPUT‬‬
‫‪VI‬‬ ‫‪VREF‬‬ ‫‪CONTROL‬‬

‫‪RT‬‬ ‫‪1‬‬ ‫‪0‬‬

‫‪C1‬‬
‫‪eT‬‬ ‫‪osc‬‬ ‫‪REFERENCE‬‬
‫‪FLIP-‬‬
‫‪C‬‬ ‫‪Q1‬‬
‫‪FLOP‬‬ ‫‪E1‬‬

‫‪0‬‬ ‫‪0‬‬ ‫‪C2‬‬

‫‪A‬‬ ‫‪D‬‬ ‫‪Q2‬‬
‫‪-‬‬ ‫‪1‬‬
‫‪0.1V‬‬ ‫‪1‬‬ ‫‪1‬‬ ‫‪E2‬‬
‫‪DEAD-TIME‬‬ ‫‪+‬‬
‫‪CONTROL‬‬
‫‪-‬‬

‫م‬
‫‪B‬‬
‫‪AMPLIFIER‬‬
‫‪ERROR AMPS‬‬ ‫‪+‬‬
‫‪INPUTS‬‬
‫‪GND‬‬

‫‪/‬‬
‫اﺣ‬
‫‪2‬‬

‫ﻣد‬
‫‪FEEDBACK‬‬

‫‪Figure 1. TL494 Block Diagram‬‬

‫ﯾ‬
‫وﺳ‬
‫‪~ ~u_u‬‬
‫‪...____.‬‬ ‫[ _ _ ‪______u_l.‬‬
‫‪ -‬ﻋﻧدﻣﺎ ﯾرﺗﻔﻊ ﺟﮭد اﺷﺎرة ﺳن اﻟﻣﻧﺷﺎر ﻋن ‪ 0.1‬ﻓوﻟت ﯾﺻﺑﺢ ﺧرج اﻟﻣﻘﺎرن ‪ A‬ﻣﻧﺧﻔض وﻟن ﯾﺗﻐﯾر ﺷﯾﺊ ﻓﻰ اﻟﻔﻠوب ﻓﻠوب‬
‫‪01‬‬ ‫واﯾﺿﺎ ﻻﯾزال اﻟﻣﻘﺎرن اﻟﺳﻔﻠﻰ ﺧرﺟﮫ ‪ 0‬ﻟﻌدم وﺟود اﺷﺎرة ﻗﺎدﻣﺔ ﻣن اﻟﻔﯾدﺑﺎك ﻋﺑر ﻣﻘﺎرﻧﺎت اﻟﻔﯾدﺑﺎك‬
‫ف‬

‫‪02‬‬
‫‪I‬‬ ‫‪11‬‬ ‫‪u‬‬ ‫‪u‬‬
‫‪0‬‬
‫‪11‬‬
‫اﻟﻣ‬

‫‪1‬‬
‫‪C‬‬
‫‪0‬‬ ‫‪0‬‬
‫‪1‬‬ ‫‪0‬‬
‫‪D‬‬
‫ﺻ‬

‫‪-‬‬
‫‪0‬‬ ‫‪0‬‬
‫‪+‬‬
‫‪0‬‬ ‫‪0‬‬
‫‪-‬‬
‫‪CONTROL‬‬
‫‪+‬‬
‫رى‬

‫‪SIGNAL‬‬

‫‪Figure 2. TL494 Modulation Technique‬‬

‫‪ -‬ﺧرج داﺋرة ‪ OR‬ھو ‪ 0‬ﺳﯾﺟﻌل اﻟﻔﻠﯾب ﻓﻠوب ﯾﺗﻐﯾر اﻟﻰ ﺧرج ‪ 0‬وﺧرج ﻋﺎﻛس ‪ 1‬وﺳﯾﺻﺑﺢ ﺧرج داﺋرة ‪ C‬اﻟﻌﻠوﯾﺔ ھو ‪1‬‬
‫ﻓﺗﻘوم ﺑﺗﺷﻐﯾل اﻟﺗراﻧزﺳﺗور ‪ Q1‬ﺑﯾﻧﻣﺎ اﻟﺗراﻧزﺳﺗور ‪ Q2‬ﻣﺗوﻗف ﻻن ﺧرج ‪ D‬ھو ‪0‬‬

‫‪2‬‬
 ‫ﻋﻧدﻣﺎ ﯾزﯾد ﺟﮭد اﻟﺧرج ﺳوف ﯾرﺳل اﺷﺎرة اﻟﻰ ﻣﻘﺎرن اﻟﻔﯾدﺑﺎك ‪ 1‬او ‪ 2‬ﺣﯾث ﺗﺧرج اﺷﺎرة ﻋﺎﻟﯾﺔ اﻟﻰ ﻣدﺧل ﻣﻘﺎرن اﻟﺗﻌدﯾل‬
‫ﺗﻐﯾر اﻟﻔﻠﯾب ﻓﻠوب وﺗوﻗف اﻟﺗراﻧزﺳﺗور اﻟﺷﻐﺎل‬

‫‪1‬‬
‫‪0‬‬
‫‪1‬‬
‫‪0‬‬
‫‪0‬‬
‫‪-‬‬ ‫‪0‬‬ ‫‪1‬‬
‫‪+‬‬
‫‪1‬‬

‫‪-‬‬ ‫‪1‬‬

‫م‬
‫‪+‬‬

‫‪/‬‬
‫اﺣ‬
‫ﯾ‬ ‫ﻣد‬
‫‪ -‬ﺑﺎﺳﺗﻣرار ارﺗﻔﺎع ﺟﮭد ﻣﻛﺛف اﻟﻣذﺑذب وھﻰ ﻣوﺟﺔ ﺳن اﻟﻣﻧﺷﺎر ﺣﺗﻰ ﺗﺻل اﻟﻰ ‪0.7‬ﻓوﻟت ﺳﺗﺟﻌل اﻟﻣﻘﺎرن‬
‫اﻟﺳﻔﻠﻰ ﺧرﺟﮫ ‪ 0‬ﻟﻛﻰ ﯾﻌﻣل اﻟﺗراﻧزﺳﺗور اﻟﺳﻔﻠﻰ وھﻛذا ﯾﺣدث ﺗﺑﺎدل ﺑوش ﺑول‬
‫وﺳ‬
‫ف‬

‫‪ -‬ﻣﻧظم اﻟﺟﮭد اﻟﻣرﺟﻌﻰ ‪ :‬ﯾﻘوم ﺑﺗﻐذﯾﺔ ﺟﮭد ﺛﺎﺑت ﻗﯾﻣﺗﮫ ‪ 5‬ﻓوﻟت اﻟﻰ دواﺋر اﻟﻛﻧﺗرول اﻟﻠوﺟﯾك وداﺋرة اﻟﻔﻠﯾب‬
‫ﻓﻠوب وداﺋرة اﻟﻣذﺑذب وداﺋرة ﻣﻘﺎرن اﻟزﻣن اﻟﻣﯾت وداﺋرة ﻣﻘﺎرن ﺗﻌدﯾل اﻻﺗﺳﺎع‬
‫اﻟﻣ‬

‫‪ -‬ھﻧﺎك ﻣﺻدر ﺗﯾﺎر ﻗﯾﻣﺗﮫ ‪ 10‬ﻣم اﻣﺑﯾر ﻟﺗﻐذﯾﺔ اﻟدواﺋر ﺑﺗﯾﺎر اﺿﺎﻓﻰ‬
‫ﺻ‬
‫رى‬

‫ﻣﻠﺣوظﺔ ‪ :‬اﻟرﺳم اﻟﺗﺧطﯾطﻰ ﻟﻼﯾﺳﻰ ھﻧﺎ ﻏﯾر واﺿﺢ ﻛﻣﺎ ﻓﻰ اﻟﻣﻠﻔﺎت اﻟﺳﺎﺑﻘﺔ ﻓﻧﺻﯾﺣﺔ ﺗﺎﺑﻊ‬
‫اﻟﺷرح ﻣن ھﻧﺎك اﻓﺿل‬
‫ ﻓوﻟت ﺛم ﯾﺗوﻗف اﻟﺷﺣن وﺗﺑدء اﻟﺗﻔرﯾﻎ ﻣرة اﺧرى ﻟﺗﻧﺷﺎ ﻣوﺟﺔ ﺳن اﻟﻣﻧﺷﺎر‬3 ‫ ﯾﺗم ﺷﺣن اﻟﻣﻛﺛف اﻟﻰ‬: ‫داﺋرة اﻟﻣذﺑذب‬
‫ﻋﻠﻰ اﻟﻣﻛﺛف ﺣﯾث ﯾﺗم اﻣدادھﺎ اﻟﻰ ﻣﻘﺎرن ﺗﻌدﯾل اﻻﺗﺳﺎع ﻟﯾﻘﺎرن ﺑﯾﻧﮭﺎ وﺑﯾن اﺷﺎرات ﻣﻘﺎرﻧﺎت اﻟﺗﺣﻛم ﻓﻰ اﻟﻔﯾدﺑﺎك‬
Operation Frequency
The frequency of the oscillator is programmed by selection of the timing components
‫ ﻣﻘﺎوﻣﺔ اﻟﺷﺣن‬/ ‫ ﻓوﻟت‬3 ‫ﯾﺗم ﺗﻌﯾﯾن ﺗﯾﺎر اﻟﺷﺣن ﺑﻘﺳﻣﺔ اﻟﺟﮭد‬
RT and CT. The oscillator charges the external timing capacitor, CT, with a constant current
- the value of which is determined by the external timing resistor, RT. This produces
a linear-ramp voltage waveform. When the voltage across CT reaches 3 V, it is discharged
by the oscillator circuit and the charging cycle is re=initiated.
‫اﻟﻣﻧﺷﺎر ﻟﻠﻣﻛﺛف‬ ‫ﻟﻣوﺟﺔ ﺳن‬current
The charging ‫اﻟزﻣن اﻟﻛﻠﻰ‬
is
determined by the formula :
3V

‫م‬
ICHARGE = -
RT : ‫ﺗردد داﺋرة اﻟﻣذﺑذب ﻓﻰ ﺣﺎﻟﺔ اﻟﺧرج اﻟﻔردى‬

/
The period of the sawtooth is:

‫اﺣ‬
t
3 V•CT
= ---...::.._
‫ ﺗردد اﻟﻣذﺑذب‬1/2 = ‫ﻓﻰ ﺣﺎﻟﺔ اﻟﺧرج اﻟﻣزدوج او اﻟﺑوش ﺑول ﻓﺎن ﺗردد ﺧرج اﻻﯾﺳﻰ‬
ICHARGE

‫ﻣد‬
The frequency of the oscillator then becomes:

‫ھﯾرﺗز‬fosc = -‫اﻟﻰ‬
‫ ﻛﯾﻠو‬300 -- ‫ ﻛﯾﻠو ھﯾرﺗز‬1 ‫ ﯾﺗم ﺑرﻣﺟﺔ ﺗردد اﻻﯾﺳﻰ ﺑﻣﻘﺎوﻣﺔ وﻣﻛﺛف ﺧﺎرﺟﻰ ﻟﺗﻌطﻰ ﺗردد ﻣن‬-
‫ﯾ‬
‫وﺳ‬
‫اﻟﻰ‬oscillator
The ‫ ﺑﯾﻛو ﻓﺎراد‬frequency,
470 ‫ﻣﻛﺛف ﻣن‬ ‫ اوم ﻣﻊ‬is‫ﻛﯾﻠو‬
however, 500
only ‫ﻟﻐﺎﯾﺔ‬to‫ﻛﯾﻠو‬
equal the 1 ‫ﺗﺑدء ﻋﻧد‬
output ‫ھذا اﻟﻣﻌدل‬
frequency for‫ﺗﻌطﻰ‬ ‫ اﻟﻣﻘﺎوﻣﺔ اﻟﺗﻰ‬-
single-ended
‫ﻣﯾﻛرو ﻓﺎراد‬10
applications; for push-pull applications, the output frequency is one-half the oscillator
‫ف‬

frequency:
1
Single-ended applications: f = ---
RT•CT : ‫ ﻛﯾﻠو ھﯾرﺗز‬150 ‫ﻋﻣل اﻟﻣذﺑذب ﻋﻧد ﺗردد اﻋﻠﻰ ﻣن‬
‫اﻟﻣ‬

1
Push-pull applications: f=---
‫ ﻣﯾﻛرو ﺛﺎﻧﯾﺔ‬6.67
2RT·CT= ‫ ﻛﯾﻠو ﻓﺎن زﻣن اﻟﻣوﺟﺔ‬150 ‫ ﻋﻧد ﻋﻣل اﻟﻣذﺑذب ﻋﻧد ﺗردد‬-
‫ﺻ‬

‫ﺛﺎﻧﯾﺔ‬
The‫ﻧﺎﻧو‬oscillator
200 ‫ﺑزﻣن‬ ‫ﻣﻌطﯾﺎ اﺷﺎرة ﻣﯾﺗﺔ‬
is programmable ‫اﻟﻛﻠﻰ‬
over ‫ اﻟزﻣن‬from
a range ‫ ﻣن‬3 1%kHz
= ‫ﺑﺎﻻرﺿﻰ‬ ‫ﻣدﺧﻠﮫ‬Practical
to 300kHz. ‫ ﻋﻧد رﺑط‬values
‫ اﻟزﻣن اﻟﻣﯾت‬-
‫رى‬

for RT and CT range from 1 kO to 500 kO and 470 pF to 10 J!F , respectively. A plot
‫ﺻﺣﯾﺢ‬R‫ﺑﺷﻛل‬
of the oscillator frequency versus T and‫ﻓﻠوب‬
CT‫اﻟﻔﻠﯾب‬ ‫اﺷﺎرات‬
is shown in ‫ﺗﻌﻣل‬ ‫ﻟﻛﻰ‬6.‫ﻣﻘﺑول‬
Figure The ‫زﻣن‬ ‫ھو اﻗل‬
stability of‫اﻟزﻣن‬
the ‫وھذا‬
oscillator, for free-air temperature variations from 0 oc to 70 oc for various ranges of RT
and CT,3is%also‫اﻛﺛر ﻣن‬ ‫اﻟﻣﯾت اﻟﻰ‬
indicated ‫ﻓﺗرة اﻟزﻣن‬
in Figure 6. ‫ ﻛﯾﻠو ھﯾرﺗز ﻓﺎﻧﮫ ﯾﻔﺿل زﯾﺎدة‬150 ‫ ﺑﺎﻟﻧﺳﺑﺔ ﻟﻠﺗرددات اﻋﻠﻰ ﻣن‬-

Operation Above 150 kHz

At an operation frequency of 150kHz, the period of the oscillator is 6.67 J.LS . The
dead time established by the internal offset of the dead-time comparator ( == 3 % period)
yields a blanking pulse of 200 ns. This is the minimum blanking pulse acceptable to assure
proper toggling of the pulse-steering flip-flop. For frequencies above 150kHz, additional

5
 ‫اﻟﻌﻼﻗﺔ ﺑﯾن ﺗردد اﻟﻣذﺑذب واﻟﻣﻘﺎوﻣﺔ ﻋﻧد ﻗﯾم ﻣﺧﺗﻠﻔﺔ ﻟﺳﻌﺔ ﻟﻣﻛﺛف‬

‫‪1 M‬‬
‫اﻟﻣﻘﺎوﻣﺔ‬ ‫‪c:‬‬
‫‪I‬‬
‫‪w‬‬
‫)(‬
‫‪z‬‬
‫‪et 100 k‬‬
‫‪I-‬‬
‫)‪CI‬‬
‫‪Cii‬‬
‫‪w‬‬
‫‪a:‬‬
‫‪0‬‬
‫‪z‬‬ ‫‪10 k‬‬
‫~‬

‫م‬
‫‪I-‬‬
‫‪I‬‬
‫‪l-‬‬
‫‪a:‬‬ ‫‪-4%‬‬

‫‪/‬‬
‫‪1k‬‬
‫‪10‬‬ ‫‪100‬‬ ‫‪1 k‬‬ ‫‪10 k‬‬ ‫‪100 k‬‬ ‫‪1M‬‬

‫اﺣ‬
‫‪f - FREQUENCY- Hz‬‬

‫‪NOTE: The percent of oscillator frequency variation over the 0 °C to‬‬

‫ﻣد‬
‫‪70 °C free-air temperature range is represented by dashed lines.‬‬

‫‪Figure 6. Oscillator Frequency vs RTICT‬‬

‫ﯾ‬
‫‪dead time (above 3%) is provided internally to assure proper triggering and blanking of‬‬
‫اﻟﺗردد ‪the internal pulse-steering flip-flop.‬‬
‫وﺳ‬
‫‪Figure 7 shows the relationship of internal dead time‬‬
‫‪(expressed in percent) provided for various values of RT and CT.‬‬
‫ف‬

‫‪1 M‬‬
‫‪c:‬‬ ‫اﻟﻌﻼﻗﺔ ﺑﯾن ﻣﻘﺎرن اﻟزﻣن اﻟﻣﯾت وﻣﻘﺎرن ﺗﻌدﯾل اﻻﺗﺳﺎع ‪:‬‬
‫‪I‬‬
‫‪w‬‬
‫)(‬

‫ﺟﮭد ~‪z‬ﺗﻐذﯾﺔ اﻟدواﺋر‬

‫ﻓﺻل ‪100‬‬ ‫ﯾﺗﻐذى اﻟﻣﻘﺎرن ﻋﻠﻰ ﺟﮭد ‪ 5‬ﻓوﻟت ﻣن ﻣﻧظم اﻟﺟﮭد اﻟﻣرﺟﻌﻰ اﻟداﺧﻠﻰ وھذا ﯾﻌطﻰ ﻣﯾزة‬
‫اﻟﻣ‬

‫‪k‬‬
‫)‪Cl‬‬
‫)‪(i‬‬
‫اﻟداﺧﻠﯾﺔ ﻋن ﻣﺻدر اﻟﺟﮭد اﻟﺧﺎرﺟﻰ ﻟﻼﯾﺳﻰ ﻣﻣﺎ ﯾﻌطﻰ ﺛﺑﺎت ﻓﻰ اﻟﺗﺷﻐﯾل وﺗﺣﺳﯾن ﻓﻰ اﻻداء‬
‫‪w‬‬
‫‪a:‬‬
‫ﺻ‬

‫ﻣن ﺟﮭد‬ ‫~اﻟﻘرﯾﺑﺔ‬

‫‪0‬‬ ‫اﻟﻣزﯾﻔﺔ‬
‫‪10 k‬‬
‫‪ -‬اﻟﻣﻘﺎرن ﻻﯾﻘﺑل اى اﺷﺎرات ﺑﮭﺎ ﺗﺷوﯾش او ﻧوﯾز وﻟذﻟك ﯾﺟب اﻟﺣذر ﻣن اﺷﺎرات اﻟﻘدح‬
‫~‬ ‫اﻟﻌﺗﺑﺔ ﻟﻠﻣﻘﺎرن‬
‫=‪i‬‬
‫رى‬

‫‪I‬‬
‫‪l-‬‬
‫اﻟﺧرج‬ ‫ﺗراﻧزﺳﺗورات‬
‫‪a:‬‬ ‫‪ -‬ﺳرﻋﺔ اﻻﺳﺗﺟﺎﺑﺔ اﻟزﻣﻧﯾﺔ ﻟﻠﻣﻘﺎرن ﻟﻼﺷﺎرات اﻟﻘﺎدﻣﺔ ﻣن دواﺋر اﻟﻛﻧﺗرول اﻻﺧرى اﻟﻰ‬
‫‪1k‬‬
‫‪10‬‬ ‫‪100‬‬ ‫‪1k‬‬ ‫‪10 k‬‬ ‫‪100 k‬‬ ‫‪1 M‬‬
‫ﺣواﻟﻰ ‪ 400‬ﻧﺎﻧو ﺛﺎﻧﯾﺔ‬

‫‪f- FREQUENCY- Hz‬‬

‫طرﯾﻘﺔ رﺑط اﻟﻣداﺧل ﻓﻘط‬ ‫اﺧﺗﻼف‬

‫‪Figure‬‬ ‫اﻻﺗﺳﺎع وﻟﻛن‬
‫‪7. Variation‬‬ ‫‪ Time‬ﺗﻌدﯾل‬
‫‪of Dead‬‬ ‫دور‪vs‬ﻣﻘﺎرن‬ ‫‪ -‬ﯾﻘوم ﻣﻘﺎرن اﻟزﻣن اﻟﻣﯾت ﺑﻧﻔس‬
‫‪RTICT‬‬

‫‪6‬‬
 : PWM ‫ ﻣﻘﺎرن اﻟﺗﻌدﯾل ﻋﻠﻰ اﺗﺳﺎع اﺷﺎرة اﻟﺧرج‬-

Dead-Time Control
‫ ﯾﻘوم ﻣﻘﺎرن اﻟﺗﻌدﯾل ﻋﻠﻰ اﻻﺗﺳﺎع ﺑﻣﻘﺎرﻧﺔ اﺷﺎرة ﺳن اﻟﻣﻧﺷﺎر اﻟﺧﺎرﺟﺔ ﻣن اﻟﻣذﺑذب ﻣﻊ اﺷﺎرات اﻟﻛﻧﺗرول‬-
The dead-time-control input provides control of the minimum dead‫اﻟﻔﯾدﺑﺎك‬ ‫ﻣﻘﺎرﻧﺎت‬
time (off time).‫اﻟﺧﺎرﺟﺔ ﻣن‬
The output of the comparator inhibits switching transistors Q 1 and Q2 whenever the voltage
at its input is ‫ﺳن‬ ‫اﺷﺎرة‬than
greater ‫اﻋﻠﻰ ﻣن‬ ‫اﻟﻣﻘﺎرن‬
the ramp ‫اﺷﺎرة ﺧرج‬
voltage of the‫ﺗﻛون‬ ‫(ﯾﺟب ان‬see
oscillator ‫ﻣﻌﻧﺎه اﻧﮫ‬
Figure‫اﻟﺧطﺎ‬
28).‫ﻣﻘﺎرن‬ ‫ ﺑرﺑط داﯾود ﻋﻠﻰ‬-
An internal
offset of 110 mV assures a minimum dead time of ~3% with the dead-time-control input
‫ ﻓوﻟت وھذا ﯾﺿﻣن اﻟﺣﺻول ﻋﻠﻰ اﻗﺻﻰ دﯾوﺗﻰ ﺳﯾﻛل ﺑدون اﻟﺣﺎﺟﺔ اﻟﻰ‬0.7 ‫اﻟﻣﻧﺷﺎر ﻟﻣﻛﺛف اﻟﻣذﺑذب ب‬
grounded. Additional dead time can be imposed by applying a voltage to the dead-time-
‫ﺷﺎرة ﺗﺣﻛم اﻟﻔﯾدﺑﺎك‬
control input. This provides a linear control of the dead time from its minimum of 3%
to 100% as the input voltage is varied from 0 V to 3.3 V, respectively. With full range
‫ﻋﻧدﻣﺎ ﯾﺗﻐﯾر اﻟﺟﮭد اﻟﻣوﺟود ﻋﻠﻰ ﺧرج‬% 0 ‫ اﻟﻰ اﻟﻘﯾﻣﺔ‬% 97 ‫ اﺗﺳﺎع ﻣوﺟﺔ اﻟﺧرج ﺗﺗﻐﯾر ﻣن ﻗﯾﻣﺔ‬-

‫م‬
control, it allows control of the output from external sources without disrupting the error
‫ ﻓوﻟت‬3.5 ‫ ﻓوﻟت اﻟﻰ‬0.5 ‫ﻣﻘﺎرن اﻟﺧطﺎ ﻣن‬
amplifiers. The dead-time-control input is a relatively high-impedance input
(11 = < 10 J1..A) and should be used where additional control of the output duty cycle is

/
required. The input, however, must be terminated2 for ‫ و‬1proper
‫اﻟﻣﻘﺎرﻧﯾن‬ ‫ﺧرج‬An
control. ‫ﺗداﺧل‬ ‫ﻟﻣﻧﻊ‬
open ‫ اﻟداﯾودات‬-
circuit

‫اﺣ‬
is an undefined condition.

Pulse-Width Modulation

‫ﻣد‬
The comparator also provides modulation control of the output pulse width. For
this, the ramp voltage across timing capacitor CT is compared to the control signal present
‫ﯾ‬
at the output of the error amplifiers. The timing capacitor input incorporates a series diode
‫وﺳ‬
that is omitted from the control signal input. This requires the control signal (error amplifier
output) to be ~ 0. 7 V greater than the voltage across CT to inhibit the output logic, and
assures maximum duty cycle operation without requiring the control voltage to sink to
‫ف‬

a true ground potential. The output pulse width varies from 97% of the period to 0 as
the voltage present at the error amplifier output varies from 0.5 V to 3.5 V, respectively.

Error Amplifiers
‫اﻟﻣ‬

A schematic of the error amplifier circuit is shown in Figure 9. Both high-gain error
amplifiers receive their bias from the VI supply rail. This permits a common-mode input
‫ﺻ‬

voltage range from -0.3 V to 2 V less than VJ. Both amplifiers behave characteristically
of a single-ended single-supply amplifier in that each output is active high only. This allows
each amplifier to pull up independently for a decreasing output pulse-width demand. With
‫رى‬

both outputs ORed together at the inverting input node of the PWM comparator, the
amplifier demanding the minimum pulse out dominates. The amplifier outputs are biased
low by a current sink to provide maximum pulse width out when both amplifiers are biased
off.

8
 5-V REF REGULATOR

OUTPUT __,_________r----.------.
CONTROL

e----4---------TOQ1
-------4----~--------TOQ2

/ ‫م‬
OUTPUT TRANSISTOR
HIGH OFF
LOW ON

‫اﺣ‬
‫ﻣد‬
COMPARATOR __._________________________________
-=- ~

OUTPUT

Figure 15. Pulse-Steering Flip-Flop

‫ﯾ‬
‫وﺳ‬
Output Transistors
There are two output transistors available on the TL494. The output structure is
illustrated in Figure 16. Both transistors are configured open collector/open emitter and
‫ف‬

each is capable of sinking or sourcing up to 200 mA of current. The transistors e~ibit

a saturation voltage of less than 1. 3 V in the common-emitter configuration and less than
2.5 V in the emitter-follower configuration. The outputs are protected against excessive
‫اﻟﻣ‬

power dissipation to prevent damage but do not employ sufficient current limiting to allow
them to be operated as current-source outputs.
‫ﺻ‬
‫رى‬

FLIP-FLOP
OUTPUT ----'V\1\~
COMPARATOR--~~~
OUTPUT

Figure 16. Output Transistor Structure

13
 Applications of the Dead-Time Control
The primary function of the dead-time control is to control the minimum off-time
exhibited by the output of the TIA94. The dead-time-control input provides control from
5% to 100% dead time, as illustrated in Figure 28.

r -
osc
OUTPUT

‫م‬
CONTROL
LOGIC
I ---

/
DEAD-
TIME --f I I
CONTROL

‫اﺣ‬
L - - - .J

5% DEAD TIME

‫ﻣد‬
CONTROL
‫ اﺷﺎرة ﻣدﺧل ﻣﻘﺎرن اﻟزﻣن اﻟﻣﯾت‬INPUT ‫ﯾ‬
‫اﻟﺳﻔﻠﻰ‬
‫وﺳ‬
‫اﺷﺎرة ﺳن اﻟﻣﻧﺷﺎر ﻋﻠﻰ اﻟﻣﻛﺛف‬
‫ف‬

‫ ﺧرج ﻣﻘﺎرن اﻟزﻣن اﻟﻣﯾت‬OUTPUT

‫اﻟﻣ‬

Figure 28. Dead-Time-Control Characteristics

‫ﺻ‬

The TIA94 can therefore be tailored to the specific power transistor switches that
are used to assure that the output transistors never experience a common on-time. The
‫رى‬

bias circuit for the basic function is shown in Figure 29. The dead-time control can be
used for many additional control signals.

21
 ‫اﺳﺗﺧدام ﻣدﺧل ﻣﻘﺎرن اﻟزﻣن اﻟﻣﯾت ﻟﻠﺑدء اﻟﻧﺎﻋم ﻟﻼﯾﺳﻰ‬

R1 To - RT CT (0.05 + 0.35 R2)

D.T.C. R2 in kO.
----- IN R1 + R2 = 5 kO
R2

Figure 29. Tailored Dead Time

‫م‬
Soft Start

/
With the availability of the dead-time control, input implementation of a soft-start
circuit is relatively simple; Figure 30 shows one example. Initially, capacitor Cs forces

‫اﺣ‬
the dead-time-control input to follow the 5-V reference regulator that disables both outputs,
i.e.,‫ورﺑطﮭم‬
100%‫اﻟﻣدﺧل‬
dead'‫ھذا‬ ‫ﻋﻠﻰ‬As
time. ‫وﻣﻘﺎوﻣﺔ‬ ‫ﺑﺗرﻛﯾب ﻣﻛﺛف‬
the capacitor ‫ وذﻟك‬through
charges ‫اﻟﻧﺎﻋم ﻟﻼﯾﺳﻰ‬
Rs, ‫ﻟﻠﺑدء‬ ‫اﻟزﻣن اﻟﻣﯾت‬
the output pulse‫ﻣدﺧل‬ ‫اﺳﺗﻐﻼل‬
slowly
‫ﺗﺣﻛم اﻟﺟﮭد‬
until‫ﺣﯾث‬ ‫ﺷﺣن اﻟﻣﻛﺛف‬
loop ‫ﻣﻊ‬ ‫ﺑﺑطﺊ‬ ‫وظﮭور اﻟﺧرج‬ ‫اﻻﯾﺳﻰ اﻟﻌﻣل‬ ‫ﺳﺗﺑدء‬is‫ﺣﯾث‬ ‫اﻟﻣرﺟﻌﻰ‬ ‫اﻟﻰ اﻟﺟﮭد‬

‫ﻣد‬
increases the control takes command. If additional control to be introduced
‫ﻣﻣﺎ‬input,
at this Rs ‫اﻟﻣﻘﺎوﻣﺔ‬ ‫ﻋﺎﻟﻰ ﻋﻠﻰ‬
a blocking diode‫اﻟﺟﮭد‬ ‫اﻟﺗﺷﻐﯾل‬
should ‫ﺑداﯾﺔ‬to‫ﻓﻰ‬isolate
be used ‫ﺳﯾﻛون‬the
‫ﺣﯾث‬soft‫اﻟﺧرج‬
-start‫ﺟﮭد‬ ‫ﺗﺣدﯾد‬If‫ﻓﻰ‬soft
circuit. ‫اﻟﻣﻛﺛف‬
start ‫ﻋﻠﻰ‬
‫ﺑﻧﺳﺑﺔ ﺗﺗﻧﺎﺳب‬
is desired ‫وﯾظﮭر اﻟﺧرج‬
in conjunction ‫اﻟﻣﻛﺛف‬
with ‫ﺑدء ﺷﺣن‬
a tailored dead‫ﻣﻊ‬time,
‫ﺑﺎﻻﻧﺧﻔﺎض‬ ‫ﯾﺑدء اﻟﺟﮭد‬
the circuit ‫ﺗﻣﺎﻣﺎ ﺛم‬29‫ﻣﺗوﻗف‬
in Figure can be‫اﻟﺧرج‬
used‫ﯾﺟﻌل‬
‫ﯾﺗم‬the
with ‫اﻟﻰ ان‬ ‫اﻟﻣﻛﺛف‬of‫ﺷﺣن‬
addition ‫ﻛﻠﻣﺎ زاد‬CT
capacitor
‫ﯾ‬ ‫ﺑﺎﻟﺗدرﯾﺞ‬
across‫ﯾﻘل‬resistor
‫اﻟﻣﻘﺎوﻣﺔ ﺳوف‬
R1. ‫وﺗزﯾد ﻛﻠﻣﺎ ﺷﺣن اﻟﻣﻛﺛف ﻻن اﻟﺟﮭد ﻋﻠﻰ‬
‫ﺑﻛﺎﻣل طﺎﻗﺗﮭﺎ‬
Not‫ﺷﻐﺎﻟﺔ‬
only ‫اﻻﯾﺳﻰ‬ ‫وﺗﺻﺑﺢ‬ ‫اﻟﻣﻛﺛف ﺗﻣﺎﻣﺎ‬
prevent‫ﺷﺣن‬
‫وﺳ‬
The use of soft-start protection is recommended. does such circuitry
large current surges during power up, it also protects against any false signals which might
be created by the control circuit as power is applied.
‫ف‬
‫اﻟﻣ‬

.....
..
‫ﺻ‬

, DEAD-TIME
•• CONTROL
Rs
‫رى‬

--
Figure 30. Soft-Start Circuit

Overvoltage Protection
The dead-time control also provides a convenient input for overvoltage protection
that may be sensed as an output voltage condition or input protection. Figure 31 employs
a TL430 as the sensing element. When the supply rail being monitored increases to the

‫اﯾﺿﺎ ﯾﻣﻛن اﺳﺗﺧدام ﻣدﺧل اﻟزﻣن اﻟﻣﯾت ﻟﻠﺣﻣﺎﯾﺔ ﻣن زﯾﺎدة ﺟﮭد اﻟﺧرج وذﻟك ﺑرﺑط ﻣﺟزئ ﺟﮭد‬
22 31 ‫ﻋﻠﻰ اﻟﺧرج اﻟﻰ ﻣدﺧل ﻣﻘﺎرن اﻟزﻣن اﻟﻣﯾت ﻛﻣﺎ ﻓﻰ اﻟﺷﻛل‬
TL494, NCV494
SWITCHMODE Pulse Width
Modulation Control Circuit
The TL494 is a fixed frequency, pulse width modulation control
circuit designed primarily for SWITCHMODE power supply control.
• Complete Pulse Width Modulation Control Circuitry
• On−Chip Oscillator with Master or Slave Operation
• On−Chip Error Amplifiers

‫م‬
• On−Chip 5.0 V Reference http://onsemi.com

• Adjustable Deadtime Control MARKING

/
• Uncommitted Output Transistors Rated to 500 mA Source or Sink DIAGRAMS
• Output Control for Push−Pull or Single−Ended Operation 16

‫اﺣ‬
• Undervoltage Lockout SO−16
TL494xD
• NCV Prefix for Automotive and Other Applications Requiring Site 16 D SUFFIX
AWLYWW
CASE 751B
and Control Changes

‫ﻣد‬
1
1
MAXIMUM RATINGS (Full operating ambient temperature range applies,
unless otherwise noted.)
16
Rating Symbol Value Unit
PDIP−16
*
‫ﯾ‬ TL494xN
Power Supply Voltage VCC 42 V N SUFFIX
AWLYYWW
‫وﺳ‬
Collector Output Voltage VC1, 42 V CASE 648
VC2 16 1
Collector Output Current IC1, IC2 500 mA 1
(Each transistor) (Note 1) x = B, C or I
‫ف‬

A = Assembly Location
Amplifier Input Voltage Range VIR −0.3 to +42 V
WL, L = Wafer Lot
Power Dissipation @ TA ≤ 45°C PD 1000 mW YY, Y = Year
Thermal Resistance, Junction−to−Ambient RJA 80 °C/W WW, W = Work Week

Operating Junction Temperature TJ 125 °C *This marking diagram also applies to NCV494.
‫اﻟﻣ‬

Storage Temperature Range Tstg −55 to +125 °C

Operating Ambient Temperature Range TA °C ORDERING INFORMATION
TL494B −40 to +125
Device Package Shipping†
‫ﺻ‬

TL494C 0 to +70
TL494I −40 to +85 TL494BD SO−16 48 Units/Rail
NCV494B −40 to +125
TL494BDR2 SO−16 2500 Tape & Reel
Derating Ambient Temperature TA 45 °C
‫رى‬

1. Maximum thermal limits must be observed. TL494CD SO−16 48 Units/Rail

PIN CONNECTIONS TL494CDR2 SO−16 2500 Tape & Reel

Noninv Noninv TL494CN PDIP−16 25 Units/Rail

Input 1 +
Error 1
+ 16 Input
2 Error TL494IN PDIP−16 25 Units/Rail
Inv Amp Amp Inv
− −
Input 2 VCC
15 Input
NCV494BDR2* SO−16 2500 Tape & Reel
Compen/PWN 5.0 V
Comp Input 3 REF 14 Vref
≈ 0.1 V
Deadtime Output †For information on tape and reel specifications,
Control 4 13 Contro
including part orientation and tape sizes, please
l refer to our Tape and Reel Packaging Specification
CT 5 12 VCC Brochure, BRD8011/D.
Oscillator
RT 6 11 C2 *NCV494: Tlow = −40°C, Thigh = +125°C.
Q2
Guaranteed by design. NCV prefix is for
Ground 7 10 E2
automotive and other applications requiring site
Q1 and change control.
C1 8 9 E1

(Top View)

 Semiconductor Components Industries, LLC, 2004 1 Publication Order Number:

April, 2004 − Rev. 5 TL494/D
 TL494, NCV494

RECOMMENDED OPERATING CONDITIONS ‫اﻟﻘﯾم اﻟﻣوﺻﻰ ﺑﺎﻟﻌﻣل ﺑﮭﺎ‬

Characteristics Symbol Min Typ Max Unit

Power Supply Voltage ‫ﻣﺻدر اﻟﺗﻐذﯾﺔ‬ VCC 7.0 15 40 V
Collector Output Voltage ‫ﺟﮭد اﻟﻣﺟﻣﻊ‬ VC1, VC2 − 30 40 V
Collector Output Current (Each transistor) ‫ﺗﯾﺎر اﻟﻣﺟﻣﻊ‬ IC1, IC2 − − 200 mA
Amplified Input Voltage ‫ﺟﮭد ﻣدﺧل اﻟﻣﻛﺑر‬ Vin −0.3 − VCC − 2.0 V
Current Into Feedback Terminal ‫ﺗﯾﺎر اﻟﻔﯾدﺑﺎك‬ lfb − − 0.3 mA
Reference Output Current ‫ﺗﯾﺎر داﺋرة اﻟﺟﮭد اﻟﻣرﺟﻌﻰ اﻟﺧﺎرﺟﻰ‬ lref − − 10 mA
Timing Resistor ‫ﻣﻘﺎوﻣﺔ اﻟﻣذﺑذب‬ RT 1.8 30 500 k

‫م‬
Timing Capacitor ‫ﻣﻛﺛف اﻟﻣذﺑذب‬ CT 0.0047 0.001 10 F
Oscillator Frequency ‫ﺗردد اﻟﻣذﺑذب‬ fosc 1.0 40 200 kHz

/
ELECTRICAL CHARACTERISTICS (VCC = 15 V, CT = 0.01 F, RT = 12 k, unless otherwise noted.)

‫اﺣ‬
For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted.
Characteristics Symbol Min Typ Max Unit
REFERENCE SECTION
Reference Voltage (IO = 1.0 mA)
Line Regulation (VCC = 7.0 V to 40 V)
Load Regulation (IO = 1.0 mA to 10 mA)
Short Circuit Output Current (Vref = 0 V)
‫ﯾ‬ ‫ﻣد‬ Vref
Regline
Regload
ISC
4.75

15
−
−
5.0
2.0
3.0
35
5.25
25
15
75
V
mV
mV
mA
‫وﺳ‬
OUTPUT SECTION
Collector Off−State Current IC(off) − 2.0 100 A
(VCC = 40 V, VCE = 40 V)

Emitter Off−State Current IE(off) − − −100 A

‫ف‬

VCC = 40 V, VC = 40 V, VE = 0 V)

Collector−Emitter Saturation Voltage (Note 2) V

Common−Emitter (VE = 0 V, IC = 200 mA) Vsat(C) − 1.1 1.3
Emitter−Follower (VC = 15 V, IE = −200 mA) Vsat(E) − 1.5 2.5
‫اﻟﻣ‬

Output Control Pin Current

Low State (VOC  0.4 V) IOCL − 10 − A
High State (VOC = Vref) IOCH − 0.2 3.5 mA
Output Voltage Rise Time tr ns
‫ﺻ‬

Common−Emitter (See Figure 12) − 100 200

Emitter−Follower (See Figure 13) − 100 200
Output Voltage Fall Time tf ns
‫رى‬

Common−Emitter (See Figure 12) − 25 100

Emitter−Follower (See Figure 13) − 40 100

2. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as possible.

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2
 TL494, NCV494

ELECTRICAL CHARACTERISTICS (VCC = 15 V, CT = 0.01 F, RT = 12 k, unless otherwise noted.)

For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted.
Characteristics Symbol Min Typ Max Unit
ERROR AMPLIFIER SECTION
Input Offset Voltage (VO (Pin 3) = 2.5 V) VIO − 2.0 10 mV
Input Offset Current (VO (Pin 3) = 2.5 V) IIO − 5.0 250 nA
Input Bias Current (VO (Pin 3) = 2.5 V) IIB − −0.1 −1.0 A
Input Common Mode Voltage Range (VCC = 40 V, TA = 25°C) VICR −0.3 to VCC−2.0 V
Open Loop Voltage Gain (
VO = 3.0 V, VO = 0.5 V to 3.5 V, RL = 2.0 k) AVOL 70 95 − dB

‫م‬
Unity−Gain Crossover Frequency (VO = 0.5 V to 3.5 V, RL = 2.0 k) fC− − 350 − kHz
Phase Margin at Unity−Gain (VO = 0.5 V to 3.5 V, RL = 2.0 k) m − 65 − deg.

/
Common Mode Rejection Ratio (VCC = 40 V) CMRR 65 90 − dB
Power Supply Rejection Ratio (
VCC = 33 V, VO = 2.5 V, RL = 2.0 k) PSRR − 100 − dB

‫اﺣ‬
Output Sink Current (VO (Pin 3) = 0.7 V) IO− 0.3 0.7 − mA
Output Source Current (VO (Pin 3) = 3.5 V) IO+ 2.0 −4.0 − mA
PWM COMPARATOR SECTION (Test Circuit Figure 11)
Input Threshold Voltage (Zero Duty Cycle)
Input Sink Current (V(Pin 3) = 0.7 V)
DEADTIME CONTROL SECTION (Test Circuit Figure 11)
‫ﯾ‬
Input Bias Current (Pin 4) (VPin 4 = 0 V to 5.25 V)
‫ﻣد‬ VTH
II−

IIB (DT)
−
0.3

−
2.5
0.7

−2.0
4.5
−

−10
mA

A
V
‫وﺳ‬
Maximum Duty Cycle, Each Output, Push−Pull Mode DCmax %
(VPin 4 = 0 V, CT = 0.01 F, RT = 12 k) 45 48 50
(VPin 4 = 0 V, CT = 0.001 F, RT = 30 k) − 45 50
Input Threshold Voltage (Pin 4) Vth V
‫ف‬

(Zero Duty Cycle) − 2.8 3.3

(Maximum Duty Cycle) 0 − −

OSCILLATOR SECTION
Frequency (CT = 0.001 F, RT = 30 k) fosc − 40 − kHz
‫اﻟﻣ‬

Standard Deviation of Frequency* (CT = 0.001 F, RT = 30 k) fosc − 3.0 − %

Frequency Change with Voltage (VCC = 7.0 V to 40 V, TA = 25°C)
fosc (
V) − 0.1 − %
Frequency Change with Temperature (
TA = Tlow to Thigh)
fosc (
T) − − 12 %
‫ﺻ‬

(CT = 0.01 F, RT = 12 k)

UNDERVOLTAGE LOCKOUT SECTION

Turn−On Threshold (VCC increasing, Iref = 1.0 mA) Vth 5.5 6.43 7.0 V
‫رى‬

TOTAL DEVICE
Standby Supply Current (Pin 6 at Vref, All other inputs and outputs open) ICC mA
(VCC = 15 V) − 5.5 10
(VCC = 40 V) − 7.0 15
Average Supply Current mA
(CT = 0.01 F, RT = 12 k, V(Pin 4) = 2.0 V) − 7.0 −
(VCC = 15 V) (See Figure 12)

N
 (Xn − X)2
* Standard deviation is a measure of the statistical distribution about the mean as derived from the formula,  n=1
N−1

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 ‫م‬
‫‪A‬‬

‫‪/‬‬
‫اﺣ‬
‫‪B‬‬

‫ﯾ‬ ‫ﻣد‬ ‫‪ A‬ﻣﻘﺎرن ﺣﻣﺎﯾﺔ ﻣن اﻧﺧﻔﺎض ﺟﮭد اﻟﻣﺻدر‬

‫ﻋن ‪ 4.9‬ﻓوﻟت‬

‫‪ B‬ﻣﻘﺎرن ﺣﻣﺎﯾﺔ ﻣن اﻧﺧﻔﺎض اﻟﺟﮭد اﻟﻣرﺟﻌﻰ ﻋن‬

‫‪ 3.5‬ﻓوﻟت‬
‫وﺳ‬
‫ف‬

‫‪ Capacitor C‬ﻣوﺟﺔ ﺳن اﻟﻣﻧﺷﺎر ﻟﻠﻣﻛﺛف‬

‫‪T‬‬
‫‪ Feedback/PWM Comp.‬اﻟﻔﯾدﺑﺎك وﻣﻘﺎرن اﻟﺗﻌدﯾل‬
‫‪ Deadtime Control‬ﻣوﺟﺔ اﻟزﻣن اﻟﻣﯾت‬
‫اﻟﻣ‬

‫اﺷﺎرة ﺳﺎﻋﺔ اﻟﻔﻠﯾب ﻓﻠوب‬ ‫‪Flip−Flop‬‬

‫‪Clock Input‬‬
‫ﺻ‬

‫‪ Flip−Flop‬اﻟﺧرج اﻟﻌﺎﻛس ﻟﻠﻔﻠﯾب ﻓﻠوب‬ ‫‪1‬‬ ‫‪1‬‬ ‫‪0‬‬ ‫‪1‬‬

‫‪Q‬‬ ‫‪0‬‬ ‫‪1‬‬

‫‪ Flip−Flop‬اﻟﺧرج اﻟﻌﺎدى ﻟﻠﻔﻠﯾب ﻓﻠوب‬

‫رى‬

‫‪0‬‬ ‫‪1‬‬ ‫‪1‬‬ ‫‪1‬‬ ‫‪1‬‬

‫‪Q‬‬ ‫‪1‬‬

‫‪ Output Q1‬اﻟﺧرج ﻋﻠﻰ ﻣﺷﻊ اﻟﺗراﻧزﺳﺗور ‪1‬‬

‫‪Emitter‬‬

‫‪ Output Q2‬اﻟﺧرج ﻋﻠﻰ ﻣﺷﻊ اﻟﺗراﻧزﺳﺗور ‪2‬‬

‫‪Emitter‬‬

‫‪ Output‬اﻟﺟﮭد ﻋﻠﻰ ﻣدﺧل اﻟﺗﺣﻛم ‪13‬‬

‫‪Control‬‬

‫ﻻﺣظ ﺗﺎﺛﯾر اﺷﺎرة اﻟﻔﯾدﺑﺎك ﻋﻠﻰ ﺧرج اﻟﺗراﻧزﺳﺗورات ﻓﻣﻊ ارﺗﻔﺎع ﺟﮭد اﺷﺎرة اﻟﻔﯾدﺑﺎك ﯾﺗم ﺧﻔض اﺗﺳﺎع ﻣوﺟﺔ اﻟﺧرج ﻋﻠﻰ‬
‫اﻟﺗراﻧزﺳﺗورات‬

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‫‪4‬‬
 ‫‪TL494, NCV494‬‬

‫ﯾﻣﻛن ﻟﻣﻘﺎرﻧﺎت اﻟﺧطﺄ ﺗﺣﺳس ﺗﯾﺎر اﻟﺧرج او ﺟﮭد اﻟﺧرج ﺣﯾث ﯾﻛون‬
‫اﻟﻣﻘﺎرن اﻟذى ﯾطﻠب ﺗﺧﻔﯾض ﻓﻰ ﺟﮭد او ﺗﯾﺎر اﻟﺧرج ھو اﻟذى ﻟﮫ‬
‫اﻻوﻟوﯾﺔ ﻓﻰ اﻟﺗﺎﺛﯾر ﻋﻠﻰ ﻣﻘﺎرن ﺗﻌدﯾل اﻻﺗﺳﺎع‬
‫‪ TL494‬ھﻰ ﻋﺑﺎرة ﻋن اﯾﺳﻰ ﺗﻌﻣل ﺑﺗردد ﺛﺎﺑت ﺑﻧظﺎم ﺗﻌدﯾل اﺗﺳﺎع ﻣوﺟﺔ‬
‫اﻟﺧرج ﻟﻠﺗﺣﻛم ﻓﻰ ﺟﮭد اﻟﺧرج وﯾﺗم اﻟﺗﺣﻛم ﻓﻰ ﺗردد اﻟﻣذﺑذب اﻟداﺧﻠﻰ ﻣن‬
‫ﺧﻼل ﻣﻛﺛف وﻣﻘﺎوﻣﺔ ﺧﺎرﺟﯾﺔ ﻣن اﻟﻌﻼﻗﺔ اﻟﺗﺎﻟﯾﺔ‬ ‫ﻋﻧدﻣﺎ ﯾﺗم ﺗﻔرﯾﻎ ﻣﻛﺛف اﻟﻣذﺑذب ﻓﺎﻧﮫ ﺗﻛون ھﻧﺎك اﺷﺎرة ﻣوﺟﺑﺔ ﻋﺎﻟﯾﺔ‬
‫ﻋﻠﻰ ﺧرج ﻣﻘﺎرن اﻟزﻣن اﻟﻣﯾت ﺣﯾث ﺗﻌطﻰ ﻧﺑﺿﺔ ﻟﺳﺎﻋﺔ اﻟﻔﻠﯾب ﻓﻠوب‬
‫ﺗوﻗف ﺗراﻧزﺳﺗورات اﻟﺧرج ‪. Q1 , Q2‬ﺣﯾث ﺗﺻﺑﺢ ﺟﻣﯾﻊ ﻣداﺧل‬
‫داﺋرة ‪ NOR‬ﻋﺎﻟﯾﺔ ﻓﯾﻛون ﺧرﺟﮭﺎ ‪ 0‬ﻣﻣﺎ ﯾوﻗف اﻟﺗراﻧزﺳﺗورات‬
‫وﯾﺣدث ھذا ﻣﻊ رﺑط ﻣدﺧل اﻟﻛﻧﺗرول ‪ 13‬اﻟﻰ اﻟﺟﮭد اﻟﻣرﺟﻌﻰ ﺣﯾث‬
‫ﯾﻌﻣل اﻟﻔﻠﯾب ﻓﻠوب ﻋﻠﻰ ﺗﺷﻐﯾل اﻟﺗراﻧزﺳﺗورات ﺑﻣوﺟﺔ ﻣرﺑﻌﺔ ﺣﯾث‬
‫ﺗﺗﻐﯾر اﺷﺎرة ﺧرج اﻟﻔﻠﯾب ﻓﻠوب ﻣﻊ ﻛل ﻧﺑﺿﺔ ﻣن ‪ 0‬اﻟﻰ ‪ 1‬وﻣن ‪ 1‬اﻟﻰ‬

‫م‪/‬‬
‫‪ 0‬وھﻛذا ﻧظرا ﻟوﺟود ﻓﯾدﺑﺎك ﻣن ﺧرج اﻟﻌﺎﻛس ﻟﻠﻔﻠﯾب ﻓﻠوب اﻟﻰ‬
‫ﻣدﺧﻠﮫ‬
‫داﺋرة ‪ NOR‬اﻟﺗﻰ ﺗﺷﻐل ﺗراﻧزﺳﺗورات اﻟﺧرج ﺗﻛون ﻋﺎﻟﯾﺔ ﻓﻘط ﻋﻧدﻣﺎ ﯾﻛون دﺧل اﻟﻔﻠﯾب‬
‫ﻓﻠوب ﻣﻧﺧﻔض ‪ 0‬وھذا ﯾﺣدث ﻓﻘط ﻋﻧدﻣﺎ ﺗﻛون اﺷﺎرة ﺳن اﻟﻣﻧﺷﺎر ﻟﻠﻣذﺑذب اﻋﻠﻰ ﻣن‬ ‫‪ -‬ﻗﯾﻣﺔ ﺗردد اﺷﺎرة اﻟﺧرج ﻋﻠﻰ اﻟﺗراﻧزﺳﺗورات ﻓﻰ ھذه اﻟﺣﺎﻟﺔ =‬

‫ا‬
‫اﺷﺎرات اﻟﻛﻧﺗرول‬ ‫ﻧﺻف ﺗردد اﺷﺎرة اﻟﺳﺎﻋﺔ ﻟﻠﻔﻠﯾب ﻓﻠوب واﻟﺗﻰ ﺗﻌﺗﺑر ھﻰ ﻧﻔﺳﮭﺎ اﺷﺎرة‬

‫ﺣﻣ‬
‫اﻟﻣذﺑذب‬
‫ﻟذﻟك اى زﯾﺎدة ﻓﻰ ﻗﻣﺔ اﺷﺎرة اﻟﻛﻧﺗرول ﺗﺳﺑب اﻧﺧﻔﺎض ﻓﻰ اﺗﺳﺎع اﺷﺎرة اﻟﺧرج‬

‫اﺷﺎرة اﻟﻛﻧﺗرول ھﻰ اﺷﺎرة ﺧﺎرﺟﯾﺔ ﯾﻣﻛن ﺗﻐذﯾﺗﮭﺎ ﻣن ﺧﻼل ﻣدﺧل اﻟزﻣن اﻟﻣﯾت او‬
‫دﯾ‬ ‫‪ -‬ﯾﻣﻛن اﯾﺿﺎ اﻟﺣﺻول ﻋﻠﻰ اﻗﺻﻰ ﻗﯾﻣﺔ ﻟﻠﺧرج ﺑﻧﺳﺑﺔ ‪ 50 %‬اذا ﺗم رﺑط‬
‫ﻣن ﺧﻼل ﻣداﺧل ﻣﻘﺎرن اﻟﺧطﺎ او ﻣن ﺧﻼل ﻣدﺧل اﻟﻔﯾدﺑﺎك ‪3‬‬ ‫اﻟﺗراﻧزﺳﺗورﯾن ﻣﻌﺎ ﻋﻠﻰ اﻟﺗوازى ورﺑط ﻣدﺧل اﻟﺗﺣﻛم اﻟﻰ اﻻرﺿﻰ ﺣﯾﻧﮭﺎ‬
‫ﺗﻌﻣل اﻻﯾﺳﻰ ﻛﺧرج واﺣد ﺗردده ﯾﺳﺎوى ﺗردد اﻟﻣذﺑذب ﻻن اﺷﺎرة اﻟﻣذﺑذب‬
‫ﺗذھب ﻣﺑﺎﺷرة اﻟﻰ ﺗراﻧزﺳﺗورات اﻟﺧرج ﺑدون اى ﺗﺎﺛﯾر ﻟﻠﻔﻠﯾب ﻓﻠوب‬
‫ﻣﻘﺎرن اﻟزﻣن اﻟﻣﯾت ﻟﮫ ﺟﮭد دﺧل ﻓﻌﺎل ﻗﯾﻣﺗﮫ ‪ 120‬ﻣم ﻓوﻟت ﺣﯾث ﯾﺣدد اﻗل ﻗﯾﻣﺔ‬
‫وﺳ‬
‫ﻟﺧرج اﻟزﻣن اﻟﻣﯾت اى اﻟوﻗت اﻟذى ﻋﻧده ﺗﺗوﻗف ﺗراﻧزﺳﺗورات اﻟﺧرج وھﻰ ﺑﻧﺳﺑﺔ‬ ‫ﯾﺗم اﺳﺗﺧدام اﻻﯾﺳﻰ ﻛﺧرج ﻓردى اذا ﻛﺎن ھﻧﺎك ﺣﺎﺟﺔ ﻟﺗﯾﺎر ﺧرج ﻋﺎﻟﻰ‬
‫ﺗﺳﺎوى ﺣواﻟﻰ ‪ %4‬ﻣن اﻟزﻣن اﻟﻛﻠﻰ ﻟﻣوﺟﺔ ﺳن اﻟﻣﻧﺷﺎر ﻣﻣﺎ ﯾﺟﻌل اﻗﺻﻰ دﯾوﺗﻰ‬ ‫ﺣﯾث ﯾﺗم رﺑط اﻟﺗراﻧزﺳﺗورﯾن ﻋﻰ اﻟﺗوازى‬
‫ﺳﯾﻛل ﻣﻣﻛن ان ﯾﺻل اﻟﯾﮭﺎ اﺷﺎرة اﻟﺧرج ﻟﻼﯾﺳﻰ ﺑﻘﯾﻣﺔ ‪ %96‬ﻋﻧدﻣﺎ ﯾﻛون ﻣدﺧل‬
‫اﻟﻛﻧﺗرول ﻣرﺑوط اﻟﻰ اﻻرﺿﻰ واﯾﺿﺎ ﺗﺟﻌﻠﮭﺎ ‪ %48‬ﻋﻧدﻣﺎ ﯾﻛون ﻣوﺻول اﻟﻰ اﻟﺟﮭد‬ ‫ﻣﻧظم اﻟﺟﮭد اﻟﻣرﺟﻌﻰ اﻟداﺧﻠﻰ ﯾﻣد دواﺋر اﻻﯾﺳﻰ اﻟﺧﺎرﺟﯾﺔ ﺑﻣﺻدر‬
‫ف‬

‫اﻟﻣرﺟﻌﻰ ‪ 5‬ﻓوﻟت‬ ‫ﺗﯾﺎر ﻗﯾﻣﺗﮫ ‪ 10‬ﻣم اﻣﺑﯾر‬

‫اﯾﺿﺎ ﯾﻣﻛن اﻟﺗﺣﻛم ﻓﻰ اﻟدﯾوﺗﻰ ﺳﯾﻛل ﺑرﺑط ﻣدﺧل اﻟزﻣن اﻟﻣﯾت اﻟﻰ ﺟﮭد ﻣﺳﺗﻣر ﻣن‬
‫‪ 0‬اﻟﻰ ‪ 3.3‬ﻓوﻟت ﺣﯾث ﯾﻣﻛن ﺗﻐﯾﯾر اﻟزﻣن اﻟﻣﯾت ﻣن ﻗﯾﻣﺔ ‪ %4‬اﻟﻰ ﻗﯾﻣﺔ‬
‫‪ %100‬وھﻰ اﻟﻘﯾﻣﺔ اﻟﺗﻰ ﻋﻧدھﺎ ﺗﻛون اﻻﯾﺳﻰ ﺑدون ﺧرج‬
‫اﻟﻣ‬

‫‪500 k‬‬
‫)‪fosc , OSCILLATOR FREQUENCY (Hz‬‬

‫‪VCC = 15 V‬‬
‫ﻧﺳﺑﺔ ﺗردد اﻟﺧرج اﻟﻰ ﺗردد اﻟﻣذﺑذب ﺣﺳب وﺿﻊ ﻣدﺧل اﻟﺗﺣﻛم‬ ‫‪100 k‬‬
‫‪CT = 0.001 F‬‬
‫ﺻ‬

‫‪Input/Output‬‬ ‫‪fout‬‬
‫‪Output Function‬‬
‫‪Controls‬‬ ‫= ‪fosc‬‬
‫‪0.01 F‬‬
‫‪Grounded‬‬ ‫‪Single−ended PWM @ Q1 and Q2‬‬ ‫‪1.0‬‬ ‫‪10 k‬‬
‫رى‬

‫‪@ Vref‬‬ ‫‪Push−pull Operation‬‬ ‫‪0.5‬‬

‫ﻓﻰ اﻟﺟدول ﯾﺑﯾن اﻟﻌﻼﻗﺔ ﺑﯾن ﺗردد ﺧرج اﻻﯾﺳﻰ وﺗردد اﻟﻣذﺑذب ﺣﺳب ﺣﺎﻟﺔ‬ ‫‪0.1 F‬‬
‫ﻣدﺧل اﻟﺗﺣﻛم ﻓﻌﻧدﻣﺎ ﯾﻛون ﻣرﺑوط ﺑﺎﻻرﺿﻰ ﺗﻌﻣل اﻻﯾﺳﻰ ﻛﺧرج ﻣﺷﺗرك‬ ‫‪1.0 k‬‬
‫وﯾﺻﺑﺢ ﺗرددھﺎ = ﺗردد اﻟﻣذﺑب‬ ‫‪500‬‬
‫‪1.0 k 2.0 k 5.0 k‬‬ ‫‪10 k 20 k 50 k‬‬ ‫‪100 k 200 k‬‬ ‫‪500 k 1.0 M‬‬
‫ﺑﯾﻧﻣﺎ ﻋﻧد رﺑط ﻣدﺧل اﻟﺗﺣﻛم ‪ 13‬اﻟﻰ ﺟﮭد ﻣرﺟﻌﻰ ﻓﺎن اﻻﯾﺳﻰ ﺗﻌﻣل ﻛﺧرج‬ ‫)( ‪RT, TIMING RESISTANCE‬‬
‫ﻣزدوج ) ﺑوش ﺑول ( اى ﻛل ﺗراﻧزﺳﺗور ﯾﻌﻣل ﻣﻧﻔرد ﺑﺗردد = ‪ 0.5‬ﺗردد‬
‫اﻟﻣذﺑذب‬ ‫ﻓﻰ اﻻﻋﻠﻰ اﻟﻌﻼﻗﺔ ﺑﯾن ﺗردد اﻟﻣذﺑذب وﻣﻘﺎوﻣﺔ اﻟﻣذﺑذب ﻋﻧد ﻗﯾم‬
‫ﻣﺧﺗﻠﻔﺔ ﻟﻠﻣﻛﺛف ‪ 0.1‬و ‪ 0.01‬و ‪ 0.001‬ﻣﯾﻛرو وﺟﮭد ﻣﺻدر‬
‫ﻣﻘﺎرن ﺗﻌدﯾل اﻻﺗﺳﺎع ﯾﻘدم وﺳﯾﻠﺔ ﻟﺿﺑط ﺟﮭد اﻟﺧرج اى ﺗﻌدﯾل اﺗﺳﺎع ﻣوﺟﺔ‬ ‫‪ 15‬ﻓوﻟت‬
‫ﺟﮭد اﻟﺧرج ﻣن اﻗﺻﻰ ﻗﯾﻣﺔ ﻟﮭﺎ ﺑﻣﺳﺎﻋدة ﻣدﺧل اﺷﺎرة اﻟزﻣن اﻟﻣﯾت او اﺷﺎرة‬
‫اﻟﺗﺣﻛم اﻟﻰ اﻗل ﻗﯾﻣﺔ ﻟﮭﺎ وھﻰ اﻟﺻﻔر وذﻟك ﻋﻧدﻣﺎ ﯾﻛون ﻣدﺧل اﺷﺎرة اﻟﻔﯾدﺑﺎك‬
‫ﺑﯾن ‪ 0.5‬ﻓوﻟت اﻟﻰ ‪ 3.5‬ﻓوﻟت‬

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‫‪5‬‬
 TL494, NCV494

% DT, PERCENT DEADTIME (EACH OUTPUT)

120 20
A VOL , OPEN LOOP VOLTAGE GAIN (dB)

110 18
VCC = 15 V

φ , EXCESS PHASE (DEGREES)

100

VO = 3.0 V 16
90 RL = 2.0 k 0 CT = 0.001 F
14
80 20
AVOL 12
70 40
60 60 10
50 80 8.0
φ
40 100
6.0
30 120 0.001 F
4.0
20 140
10 160 2.0

‫م‬
0 180 0
1.0 10 100 1.0 k 10 k 100 k 1.0 M 500 k 1.0 k 10 k 100 k 500 k
f, FREQUENCY (Hz) fosc, OSCILLATOR FREQUENCY (Hz)

/
Figure 4. Open Loop Voltage Gain and Figure 5. Percent Deadtime versus
Phase versus Frequency Oscillator Frequency

‫اﺣ‬
% DC, PERCENT DUTY CYCLE (EACH OUTPUT)

50 V CE(sat) , SATURATION VOLTAGE (V) 1.9

1 1.8

‫ﻣد‬
40 VCC = 15 V
2 VOC = Vref 1.7
1.
CT = 0.01 F
30 2.
RT = 10 k 1.6
2.
CT = 0.001 F
2.
RT = 30 k 1.5
‫ﯾ‬
20 1.4
‫وﺳ‬
1.3
10
1.2
0 1.1
‫ف‬

0 1.0 2.0 3.0 3.5 0 100 200 300 400

VDT, DEADTIME CONTROL VOLTAGE (IV) IE, EMITTER CURRENT (mA)
Figure 6. Percent Duty Cycle versus Figure 7. Emitter−Follower Configuration
Deadtime Control Voltage Output Saturation Voltage versus
Emitter Current
‫اﻟﻣ‬

2.0 10
VCE(sat), SATURATION VOLTAGE (V)

9.0
I CC , SUPPLY CURRENT (mA)
‫ﺻ‬

8.0
1.6
7.0
1.4 6.0
‫رى‬

1.2 5.0
1.8 4.0
1.0
3.0
0.8
2.0
0.6 1.0
0.4 0
0 100 200 300 400 0 5.0 10 15 20 25 30 35 40
IC, COLLECTOR CURRENT (mA) VCC, SUPPLY VOLTAGE (V)

Figure 8. Common−Emitter Configuration Figure 9. Standby Supply Current

Output Saturation Voltage versus versus Supply Voltage
Collector Current

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6
 TL494, NCV494

VCC = 15V
150 150
2W 2W
VCC
Error Amplifier Deadtime C1 Output 1
Test
+ Under Test E1
Inputs
Vin Feedback
− RT C2 Output 2
CT E2
Feedback
Terminal (+)
(Pin 3) (−) Error
(+)
+ (−)
Output Ref

‫م‬
Vref − Control Out
Other Error 50k
Amplifier Gnd

/
Figure 10. Error−Amplifier Characteristics Figure 11. Deadtime and Feedback Control Circuit

‫اﺣ‬
15V

Each
C
‫ﯾ‬RL
68

CL
VC
‫ﻣد‬ Each
Output
Transistor
Q
C
15V
‫وﺳ‬
Output Q VEE
15pF E
Transistor
RL CL
E 68 15pF
‫ف‬

90% 90%
90% 90%
VEE
VCC
10% 10%
10% 10%
‫اﻟﻣ‬

Gnd
tr tf
tr tf
‫ﺻ‬

Figure 12. Common−Emitter Configuration Figure 13. Emitter−Follower Configuration

Test Circuit and Waveform Test Circuit and Waveform
‫رى‬

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7
 TL494, NCV494

Vref
VO
To Output
Voltage of
System 1
+
R1 R2
Error
Amp
1 −
+ 2
Error
3
Amp Negative Output Voltage R1
Vref −
2 R1
VO = Vref
Positive Output Voltage R2 VO
R2
R1 To Output
VO = Vref 1 + Voltage of

‫م‬
R2
System

/
Figure 14. Error−Amplifier Sensing Techniques

Output

‫اﺣ‬
Control

Vref R1
Output 4

‫ﻣد‬
Q DT

RT CT
R2
6 5 Vref CS
Output 4
‫ﯾ‬
Q DT
0.001
‫وﺳ‬
30k
RS

80
‫ف‬

Max. % on Time, each output ≈ 45 −

R1
1 +
R2

Figure 15. Deadtime Control Circuit Figure 16. Soft−Start Circuit

‫اﻟﻣ‬

C1 C1
‫ﺻ‬

QC 2.4 V ≤ VOC ≤ Vref

Q1 Q1 1.0 mA to
E1 E1 250 mA
Output Output
Control 1.0 mA to Control
500 mA
‫رى‬

Single−Ended Push−Pull
C2 C2
1.0 mA to
0 ≤ VOC ≤ 0.4 V Q2 Q2
250 mA
E2 E2
QE

Figure 17. Output Connections for Single−Ended and Push−Pull Configurations

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8
 TL494, NCV494

Vref
‫رﺑط ﻣﺻدر اﻟﺟﮭد اﻟﻰ داﺋرة ﺗﺛﺑﯾت ﺑواﺳطﺔ ﺗراﻧزﺳﺗور‬
‫ ﻓوﻟت‬40 ‫وزﯾﻧر ﻋﻧدﻣﺎ ﯾﻛون ﻣﺻدر اﻟﺟﮭد اﻛﺑر ﻣن‬

6
RT
Master RS VCC
5
RT CT
Vin > 40V 12
CT 1N975A
VZ = 39V 5.0V
Vref Ref
270
Gnd
6

‫م‬
RT Slave 7
5 (Additional
CT Circuits)

/
‫اﺣ‬
Figure 18. Slaving Two or More Control Circuits Figure 19. Operation with Vin > 40 V Using
External Zener

‫ﻣد‬
+Vin = 8.0V to 20V
‫ﯾ‬
‫وﺳ‬
12 +VO = 28 V
1 47 1N4934 IO = 0.2 A
+ VCC T1

2 8 Tip 22
− C1
32 L1 k
1M
‫ف‬

33k 3 +
Comp TL494 50
+ 35V
0.01 0.01 15 11
− C2 Tip 50
4.7k +
32 25V
16 50
+ 35V
‫اﻟﻣ‬

OC VREF DT CT RT Gnd E1 E2 47 1.0

1N4934
13 14 4 5 6 7 9 10
+ 240
4.7k 10
‫ﺻ‬

4.7k 15k
10k 0.001
‫رى‬

‫ﺣﺎﻟﺔ ﻋﻣل اﻻﯾﺳﻰ ﺑﺎﺗﻧﯾن ﺧرج ﺑوش ﺑول ﻛوﻧﻔرﺗر راﻓﻊ‬

Test Conditions Results

Line Regulation Vin = 10 V to 40 V 14 mV 0.28% L1 − 3.5 mH @ 0.3 A
T1 − Primary: 20T C.T. #28 AWG
Load Regulation Vin = 28 V, IO = 1.0 mA to 1.0 A 3.0 mV 0.06% T1 − Secondary: 12OT C.T. #36 AWG
Output Ripple Vin = 28 V, IO = 1.0 A 65 mV pp P.A.R.D. T1 − Core: Ferroxcube 1408P−L00−3CB

Short Circuit Current Vin = 28 V, RL = 0.1  1.6 A

Efficiency Vin = 28 V, IO = 1.0 A 71%

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 TL494, NCV494
‫ﻣﻠف اﻟﻛوﻧﻔرﺗر‬
‫ﺗراﻧزﺳﺗور اﻟﻛوﻧﻔرﺗر‬ 1.0mH @ 2A
‫اﻟدﺣل‬ +Vin = 10V to 40V Tip 32A +VO = 5.0 V ‫اﻟﺧرج‬
IO = 1.0 A

47
150
47k

12 0.1
8 11 ‫اﻟﻔﯾدﺑﺎك‬
VCC C1 C2 3 1.0M
Comp
− 2

‫م‬
‫ﻣﻛﺛف اﻟدﺧل‬ 5.1k 5.1k
+ + 1
50
50V TL494 Vref 14

/
+
500
− 15 MR850 10V
16 5.1k
‫داﯾود اﻟﻛوﻧﻔرﺗر‬

‫اﺣ‬
+
CT RT D.T. O.C. Gnd E1 E2 ‫ﻣﻛﺛف اﻟﺧرج ﻟﻠﻛوﻧﻔرﺗر‬
+ 50
5 6 4 13 7 9 10
10V

‫ﻣد‬
150
0.001 47k

0.1
‫ﯾ‬
‫وﺳ‬
‫ ﻛﯾﻠو‬10.6 ‫اﻟﺗردد ﺣواﻟﻰ‬
‫ﻋﻣل اﻻﯾﺳﻰ ﻛﺧرج ﻓردى ﻓﻰ داﺋرة ﻛوﻧﻔرﺗر ﺧﺎﻓض‬
‫ﻻﺣظ ﺗوﺻﯾل ﻣدﺧﻠﻰ اﻟﻛﻧﺗرول واﻟزﻣن اﻟﻣﯾت اﻟﻰ اﻻرﺿﻰ ﻣﻊ ﻣﺷﻊ اﻟﺗراﻧزﺳﺗورﯾن‬
‫ف‬

Test Conditions Results

Line Regulation Vin = 8.0 V to 40 V 3.0 mV 0.01%
‫اﻟﻣ‬

Load Regulation Vin = 12.6 V, IO = 0.2 mA to 200 mA 5.0 mV 0.02%

Output Ripple Vin = 12.6 V, IO = 200 mA 40 mV pp P.A.R.D.
Short Circuit Current Vin = 12.6 V, RL = 0.1  250 mA
‫ﺻ‬

Efficiency Vin = 12.6 V, IO = 200 mA 72%

‫رى‬

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10
 TL494, NCV494

PACKAGE DIMENSIONS

PDIP−16
N SUFFIX
CASE 648−08
ISSUE R

NOTES:
−A− 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
16 9 3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
B

‫م‬
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 8 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
F

/
C L A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
S C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53

‫اﺣ‬
SEATING F 0.040 0.70 1.02 1.77
−T− PLANE G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
H K M J 0.008 0.015 0.21 0.38
J K 0.110 0.130 2.80 3.30
G L

‫ﻣد‬
0.295 0.305 7.50 7.74
D 16 PL
M 0
10
0
10

0.25 (0.010) M T A M S 0.020 0.040 0.51 1.01
‫ﯾ‬
‫وﺳ‬
SO−16
D SUFFIX
CASE 751B−05
ISSUE J
‫ف‬

−A−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
‫اﻟﻣ‬

Y14.5M, 1982.
16 9 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
−B− MOLD PROTRUSION.
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
1 8
0.25 (0.010) M B S PER SIDE.
‫ﺻ‬

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS INCHES
‫رى‬

DIM MIN MAX MIN MAX

F A 9.80 10.00 0.386 0.393
K R X 45
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
C F 0.40 1.25 0.016 0.049
−T− SEATING G 1.27 BSC 0.050 BSC
PLANE J J 0.19 0.25 0.008 0.009
M
K 0.10 0.25 0.004 0.009
D 16 PL M 0
7
0
7

P 5.80 6.20 0.229 0.244
0.25 (0.010) M T B S A S R 0.25 0.50 0.010 0.019

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11
 TL494, NCV494

/ ‫م‬
‫اﺣ‬
‫ﯾ‬ ‫ﻣد‬
‫وﺳ‬
‫ف‬
‫اﻟﻣ‬
‫ﺻ‬
‫رى‬

SWITCHMODE is a trademark of Semiconductor Components Industries, LLC.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
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12