A for loop is initiated as given below, in total how many iterations will be there for the FOR loop?

FOR i IN 0 TO 5 LOOP

a) 3
b) 4
c) 5
d) 6

What is the use of EXIT statement in a loop?

a) For skipping one execution
b) For repeating one statement in the loop
c) For ending the condition and creating infinite loop
d) For ending the loop

The most basic form of behavioral modeling in VHDL is_______

a) IF statements
b) Assignment statements
c) Loop statements
d) WAIT statements
View Answer
Answer: b
Explanation: Assignment statements are used basically in the behavioral modeling. In behavioral
modeling, one needs to describe the value of outputs for various combinations of inputs, so we need
to assign different values to output variables. Therefore, assignment is the most used statement in
behavioral modeling.

SIGNED and UNSIGNED data types are defined in which package?

a) std_logic_1164 package
b) std_logic package
c) std_logic_arith package
d) standard package
View Answer
Answer: c
Explanation: SIGNED and UNSIGNED data types are defined in std_logic_arith package of the ieee
library. These data types are mainly intended for arithmetic operations. This is why they are defined
in arithmetic package.
Dataflow style of architectural modeling is represented as a set of  ___________
assignment statements.

a. Sequential
b. Concurrent
c. Random
d. Combinational
Answer    Explanation  

ANSWER: Concurrent

Which of the following is not a type of VHDL modeling?

a) Behavioral modeling
b) Dataflow modeling
c) Structural modeling
d) Component modeling
View Answer
Answer: d

Which of the following statement is used in structural modeling?

a) portmap()
b) process()
c) if-else
d) case
View Answer
Answer: a

What is the basic unit of behavioral description?

a) Structure
b) Sequence
c) Process
d) Dataflow
View Answer
Answer: c

Refer to the code given below, which type of modeling is used to describe the system?
ARCHITECTURE and_1 OF and_gate IS
begin
process(a, b, y)
begin
IF(a = ‘1’ and b = ‘1’) THEN
y <= ‘1’;
ELSE y <=’0’;
end IF;
END process;
END and_1;

a) Structural
b) Component
c) Dataflow
d) Behavioral
View Answer
Answer: d

Ports are known as _____ to the component.

a) Structure
b) Behavior
c) Function
d) Interface
View Answer
Answer: d
Which of the following is a variable assignment statement?
a) <=
b) :=
c) =>
d) ==
View Answer
Answer: b

If there is more than one process in a VHDL code, How they are executed?
a) One after the other
b) Concurrently
c) According to sensitivity list
d) Sequentially
View Answer
Answer: b
Explanation: All the processes in a design execute concurrently or in a parallel manner. However, at
a given time, only one statement is executed within the process. More than one processes can
execute in a parallel manner, but the same is not true for statements within a process.

Which of the following can be the name of an entity?

a) NAND
b) Nand_gate
c) Nand gate
d) AND
View Answer
Answer: b

 Refer to the code given below, how many input output pins are there in MUX entity?
ENTITY mux IS
Port ( a,b : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END mux;

a) 5
b) 4
c) 3
d) 2
View Answer
Answer: c

What does the architecture of an entity define?

a) External interface
b) Internal functionality
c) Ports of the entity
d) Specifications
View Answer
Answer: b

---------------------------------------------------

The inputs in the PLD is given through ____________

a) NAND gates
b) OR gates
c) NOR gates
d) AND gates
View Answer

Answer: d
Explanation: The inputs in the PLD is given through AND gate followed by inverting & non-inverting
buffer. PLDs are Programmable Logic Devices consisting of logic gates, flip-flops and registers connected
together on a single chip. Thus, it can be categorised into PROM, PAL and PLA.

2. PAL refers to ____________

a) Programmable Array Loaded
b) Programmable Logic Array
c) Programmable Array Logic
d) Programmable AND Logic
View Answer
Answer: c
Explanation: PAL refers to Programmable Array Logic consisting of programmable AND

Outputs of the AND gate in PLD is known as ____________

a) Input lines
b) Output lines
c) Strobe lines
d) Control lines
View Answer

Answer: b
Explanation: Outputs of the AND gate in PLD is known as output lines.

4. PLA contains ____________

a) AND and OR arrays
b) NAND and OR arrays
c) NOT and AND arrays
d) NOR and OR arrays
View Answer

Answer: a
Explanation: Programmable Logic Array is a type of fixed architecture logic devices with programmable
AND gates followed by programmable OR gates. It is a kind of PLD.

5. PLA is used to implement ____________

a) A complex sequential circuit
b) A simple sequential circuit
c) A complex combinational circuit
d) A simple combinational circuit
View Answer

Answer: c

The complex programmable logic device contains several PLD blocks and __________
a) A language compiler
b) AND/OR arrays
c) Global interconnection matrix
d) Field-programmable switches
View Answer

Answer: c
Explanation: The complex programmable logic device contains several PLD blocks and a global
interconnection matrix by which it communicates through several devices. It is also known as Field-
Programmable Gate Arrays (FPGAs).

9. Which type of device FPGA are?

a) SLD
b) SROM
c) EPROM
d) PLD
View Answer

Answer: d

The difference between a PAL & a PLA is ____________

a) PALs and PLAs are the same thing
b) The PLA has a programmable OR plane and a programmable AND plane, while the PAL only has a
programmable AND plane
c) The PAL has a programmable OR plane and a programmable AND plane, while the PLA only has a
programmable AND plane
d) The PAL has more possible product terms than the PLA
View Answer

Answer: b
Explanation: The main difference between a PAL & PLA is that PLA has a programmable OR plane and a
programmable AND plane, while the PAL only has a programmable AND plane and a fixed OR plane.

11. If a PAL has been programmed once ____________

a) Its logic capacity is lost
b) Its outputs are only active HIGH
c) Its outputs are only active LOW
d) It cannot be reprogrammed
View Answer

Answer: d

The FPGA refers to ____________

a) First programmable Gate Array
b) Field Programmable Gate Array
c) First Program Gate Array
d) Field Program Gate Array
View Answer

Answer: b