Design of a Pre-amplifier in Differential Mode

Continuous Comparator
Byung-Hun Yoon, Shin-Il Lim
Dept. of Electronics Engineering
Seokyeong University
Seoul, Korea
silim@skuniv.ac.kr

Abstract— This paper describes how to design a pre-amplifier in

differential mode continuous comparator for the driver IC in
ATE (automatic test equipment) system with 0.18um BCDMOS
technology. While the previous differential mode comparator
which compares the differential signals between two DUTs
(device under test) needs three pre-amplifiers, the proposed pre-
amplifier exploits only one differential difference amplifier
(DDA). It shows less power consumption and less chip area. Also,
it does not need compensation circuits and compensation
capacitors in DDA. It operates up to the frequency range of
800MHz. The chip area is 0.514mm2.
A. Previous Architecture
Fig. 1 (a) shows previous pre-amplifier in high-speed
continuous comparator. It consists of three operational
amplifiers such as DF for differential signal generation, CM for
common mode signal generation and DFF for summing up
these two signals.[2] However, this cascade structure causes
some problems such as instability in high frequency operation,
large chip area due to many components and also large power
dissipation.

Keywords- ATE; High Speed Continuous Comparator; B. Proposed Architecture

Differential Difference Amplifier.
I. INTRODUCTION
For the testing and characterizing AP processor and SoC
(system on a chip), the pin card in high speed ATE (automatic
test equipment) includes the driver IC to force the signal to
DUT (device under test) and to measure the signal from DUT.
[1] In the driver IC, PMU (parametric measurement unit), DAC,
comparators, active load and SPI (serial peripheral interface)
memory resistors are included. This paper describes the new
pre-amplifier design technique in high speed differential mode
continuous comparator to detect both differential signals and
common mode signals from two DUTs. In Fig 1, Channel 0
can be connected to one DUT and Channel 1 can be connected
to another DUT.
The proposed architecture of pre-amplifier is shown in Fig.
1 (b). Only one DDA amplifier [3] is enough for processing all
the differential and common mode signals. Since this proposed
architecture uses only one operational amplifier, it does not
suffer from the instability, mismatches, the cumulated offsets
and the noises of many operational amplifiers. Furthermore, it
shows less power consumption and less hardware area.
II. CIRCUIT IMPLEMENTATION
Fig. 2 shows the inner circuits of DDA. The input stage is
designed for rail-to-rail operation by paralleling the PMOS
input pair and the NMOS input pair. Therefore DUT signals
which swing from GND to VDD can be handled with this
DDA. For high gain and high speed operation, a folded cascade
structure was used. The folded cascade structure inherently
guarantees stability for high frequency operation and it doesn’t
require additional compensation capacitor.

Fig. 1. The Proposed Pre-Amplifier in Continuous Comparator

Fig. 2. Circuits of DDA

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 The output voltage, Vout, includes both the difference of
common mode signals and the difference of differential signals
from Channel 0 (VIP) and Channel 1 (VIN) as expressed in
equation (1), when we use the DDA as shown in Fig. 1(b)
The proposed circuit was implemented with 0.18um
BCDMOS technology. A layout of comparator in driver IC for
ATE is shown in Fig. 5. The driver IC includes the proposed
comparator, SPI resistor, PMU, driver, DAC and so on. The
DDA is the part of comparator, and the area of comparator is
620μm x 830μm.
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III. SIMULATION AND MEASURED RESULTS
A. AC Simulation Results
Fig. 3 shows the AC simulation results of DDA. Unity
gain frequency is very important to operate over 800MHz
signal processing in ATE. The gain of DDA is 32dB and unity
gain frequency of DDA is 1.33GHz. And Phase margin is 65°.
Fig. 3. AC Simulation Results
B. Transient Simulation and Measured Results
Fig. 4 shows the simulated results of proposed DDA in
the left side and also the measured results of proposed DDA in
the right side. As shown in Fig. 4, the differences of the
common mode voltages and the difference of differential
mode voltages are measured correctly as expected in
simulation results. There are three cases of input signals to
verify the correct operation of DDA.
Fig. 4. Transient Simulation & Measured Results
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Fig. 5. Layout of proposed comparator in driver IC for ATE
IV. CONCLUSION
This paper describes new pre-amplifier design technique in
in differential mode continuous comparator for ATE and was
implemented by 0.18μm BCDMOS process. This design used
only one DDA, while the previous pre-amplifier has three
operational amplifiers. A DDA is exploited with minimum
hardware, with less power consumption and with lower noise
to detect the differences of both common mode signals and
differential signals.
ACKNOWLEDGMENT
This research was supported by the MSIP (Ministry of
Science, ICT and Future planning), Korea, under the ITRC
(Information Technology Research Center) support program
(IITP-2015-H8501-15-1010) supervised by the IITP (Institute
for Information & Communication Technology Promotion) and
also supported by the Industrial Core Technology Development
Program(10049009) funded by the Ministry of Trade, Industry
& Energy (MOTIE), Korea.
REFERENCES
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PMU for Automated Test Equipment Systems”, International Journal of
VLSI design & Communication Systems (VLSICS), vol. 5, no.1, pp. 15-
28, Feburary 2014.
[2] Data Sheet of ADATE 318, analog Devices..
[3] E. Säackinger and W. Guggenbüuhl, “A Versatile Building Block : The
CMOS Differential Difference Amplifier,” IEEE Journal of Solide-State
Circuits, pp. 287-294, April, 1987.
[4] G. Nicollini and C. Guadiani, “A 3.3-V 800-nV noise, gain-
programmable CMOS microphone preamplifier design using yield
modeling technique.” IEEE J. Solide-State Circuits, vol. 28. No. 8, pp.
915-920, Aug. 1993.
[5] Baker, R. Jacob, “CMOS : Circuit Design, Layout and Simulation, 3rd
Edition”, IEEE Press Seires on Microelectronics Systems, August
2010.word in a paper title, except for proper nouns and element symbols.
ISOCC 2015
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