A 6 V CMOS Switching Mode Amplifier for

Continuous-Wave Signals from DC to 3 GHz

Robert Bieg, Martin Schmidt, Markus Grözing, Manfred Berroth

Institute of Electrical and Optical Communications Engineering
University of Stuttgart, 70569 Stuttgart, Germany
Abstract—This paper presents a CMOS switching mode am-
plifier in a 65 nm technology with 6 V output voltage swing. 6V
Due to the low breakdown voltage of the transistors, a stacked V6
6V
transistor topology is proposed. Thin-oxide FETs and thick-oxide V65 V65
FETs are used in the output stage to increase output power and 5V P0
reduce circuit complexity. Driven by a continuous-wave (CW)
5V
signal the amplifier can be operated up to 3 GHz. The two on- V5 V5 Thin-oxide-
chip amplifier stages can be operated in differential mode. The P1 p-channe l
measured broadband output power into 50 Ω is 21.3 dBm for MOSFETs

2 GHz and 18.5 dBm for 3 GHz in differential mode. 5V

V45 V45
4V P2
I. I NTRODUCTION 4V
V4

The benefit of switching mode amplifiers (SA) is the P3

3V
theoretical power efficiency of 100 %. Therefore that kind V3 V3
Vout
Thick-oxide-
of amplifiers is attractive compared to linear amplifiers, that MOSFETs

achieve comparably low efficiencies. 2V N3

V2
Advanced CMOS technology nodes offer superior performance
and power efficiency at the price of low breakdown voltages
2V N2
of around 1 V. To increase the impedance level and thus V12 V12
reduce resistive losses transistors can be stacked. A different 1V
approach can be found in recent publications of SA in CMOS 1V
Thin-oxide-
V1 V1 N1 n-channe l
technologies. References [1], [2], [3] use extended drain MOS MOSFETs
(EDMOS) transistors in their output stages. The extended drain
transistors have a higher breakdown voltage and are suitable 1V
V10 V10 N0
for generating a large output power. The drawback is, that the
on-resistance is higher than in conventional MOSFET devices. 0V
V0
Hence the static power loss for an EDMOS is higher than
for stacked transistors when driving a resistive load. Refe- Fig. 1. Stacked MOSFET 6 V output voltage switching stage.
rence [1] presents an EDMOS SA with 50 Ω load. The high
on-resistance leads to a decrease of 1 V for the output voltage
VGS0
swing at 9 V supply voltage. In comparison to that the voltage
VDS0
drop is 200 mV at 6 V supply voltage for the shown stacked 1
VGS1
transistor topology and a 50 Ω load resistance. For driving
Voltage [V]

VDS1
capacitive loads like shown in [2] the output swing is not 0.5 VGS2
reduced by the increased on-resistance. However an increased VDS2
on-resistance increases the power loss over the transistors
0
and reduces bandwidth of the amplifier. Reference [3] uses
EDMOS transistors to drive an LDMOS SA which generates 6 Time [ns] VGS3
large output power. VDS3
This paper presents a stacked SA with digital control of every V
Voltage [V]

out
4
transistor in the stack. In Section II the output stage and the
signal processing are explained. In Section III measurement
2
results are shown. Section IV concludes the paper.
0
II. 6 V S TACKED MOSFET O UTPUT S TAGE T OPOLOGY 2 2.2 2.4 2.6 2.8 3 3.2 3.4
Time [ns]
A. Output Stage
The output stage consists of the nMOS and pMOS Fig. 2. Simulated gate-source and drain-source-voltages of all transistors in
branches already shown in [4] and a thick-oxide inverter in the n-channel branch.

978-1-4673-6853-7/17/$31.00 ©2017 IEEE

 X2 4

Current Starved Inverter

Initial Pulse

Delay Cells: Multiplex

6V Switching Stage
Delayed Pulse
CML-Amplifier

CML2CMOS

Delay Cells:
Vin1 Vout1 3
4 4 4 4

Driver
Vin2 Vout2
2

Voltage [V]
1
Clock Analysis VDelay
Shift Register
Ciruit
Data
0

Fig. 3. Block diagram of the amplifier. -1

VDD -2
P0
Vin Vout
-3
N0 0 200 400 600 800 1000
VC
time [ps]

N1 N4 Fig. 5. Measured initial and delayed output waveforms.

Vin MUX Vout VC,1 VDD

N2 N5
VC,2 lead to weak edges at the output. Therefore delay cells are used
on-chip to equalize temporal alignment of the driving signals.
N3 N6
VC,3
VSS
The analog control circuit in [4] is replaced by a digital control
circuit because of the better driving ability of CMOS inverters.
Fig. 4. left: multiplexed inverter delay cell, right: digital current starved delay Therefore the generated delays are independent of frequency
cell. and the resolution in the delay cells is increased.
The chip consists of two amplifier stages, that can be driven
independently. The necessary control data for the delay cells
between. In case the branch is switched off the 6 V voltage
and analysis circuit can be programmed into the on-chip
drop will be distributed equally on the three 1-V-thin-oxide
configuration register. With the analysis circuit the driving
transistors and the 3-V-thick-oxide transistor. In comparison
signals can be observed.
to thin-oxide transistors the thick-oxide transistor adds more
capacitance at the same on-resistance but it reduces complexity
and power consumption of the driver. The resulting topology C. Delay Cells
is depicted in Fig. 1. Two different kinds of delay cells are used as can be seen
The gate-source and drain-source-voltages of all transistors in Fig. 3. The first delay cell type consists of a multiplexed
in the n-channel branch have been simulated and are shown inverter chain. A piece of the chain can be seen in Fig. 4 (left).
in Fig. 2. Similar simulations can be done for the transistors The delay chain is designed to support delay of a multiple of
in the pMOS branch. The voltages VGS and VDS do not 15 ps up to 225 ps. The circuit adjusts the pulse position of
exceed 1 V for the thin-oxide transistors N0, N1 and N2. the driving signals but it is not possible to change the pulse
The gate length of the thick-oxide transistor N3 is 370 nm width. Therefore current starved inverters depicted in Fig. 4
and has a breakdown voltage of 3.3 V. VGS3 and VDS3 (right) are used in the second part. This delay cell consists
are within the permitted voltage range. Fig. 2 also shows of a CMOS-inverter with MOSFETS N0 and P0. Furthermore
the waveform of the output voltage. The peak-to-peak- transistors N1 to N6 are added to the n-channel branch of
voltage is smaller than 6 V due to the drain-source-voltages the inverter. The transistors N4 to N6 are biased with VDD
of the conducting transistors when driving a 50 Ω load resistor. allowing the output node of the cell to discharge even for N1
to N3 being switched off. With the control voltages VC,1 to VC,3
the fall time of the delay cell can be varied. By cascading two
B. Circuit Overview or more delay cells either rising or falling edge or both can
be delayed by about 2.5 ps to 75 ps in the simulations under
Fig. 3 depicts the block diagram of the whole amplifier. The typical corner conditions.
four driving signals generated in the CML2CMOS amplifier Fig. 5 depicts two measured waveforms of the output voltage
are within four different voltage ranges. The voltage range at a CW-frequency of 1 GHz. First the delay cells were in their
necessary for a driving signal is depicted in Fig. 1. V65 is in default state adding no additional delay to the signals. Second
the voltage range between 6 V and 5 V and V5 is constant at 5 V a delay of about 60 ps was set to all driving signals of the
etc. Since the relative edge positions of the driving signals on amplifier. This delays the pulse of the output voltage by the
different voltage levels are important for the rise and fall times same amount.
of the output signal edges and the unwanted cross-current of
the MOSFET stack, delay cells are necessary for optimization. III. M EASUREMENT R ESULTS
The conversion of signals in the CML2CMOS subcircuits and
mismatch distort the driving signals and lead to bad alignment. The photograph of the measured chip is pictured in Fig. 6.
That could lead to overvoltages on some transistors or could First the results from one channel are shown.
 140 24

135 22

130 20

125 18

120 16

Output power [dBm]

Rise/Fall time [ps]
115 14

110 12

105 10
Fig. 6. Chip photograph with chip dimensions: 1.1 mm X 0.6 mm.
100 8

95 6
A. Rectangular Continuous-Wave Drive Signal with 50 % Duty
Cycle for one channel 90 Output power
4
Rise time
85 2
One channel is driven by a periodic rectangular signal Fall time
whereas the second channel is in a static state. The amplifier 80
0.5 1 1.5 2 2.5 3
0

can be operated up to 3 GHz with reasonable performance. The Signal frequency [GHz]
rise and fall times, broadband output power and efficiency are
discussed. Fig. 7. Measured 10 % - 90 % rise- and fall times and output power vs. the
signal frequency for a periodic drive signal with a 50 % duty cycle.
1) Rise and Fall Times: For a theoretical switching mode
amplifier the rise and fall times are equal to zero. In real 100
IF
devices, the load capacitances on the output node and the load 90 PAE
p
impedance need to be driven. Thus the slew rate of the output ηp
signal is reduced. Fig. 7 depicts the measured 10 % - 90 %

Ideality Factor [%], η p [%], PAE p [%]

80

rise- and fall-times. Similar to [4] the peak-to-peak-voltage 70

decreases for higher signal frequencies and hence the rise- and
fall times decrease. 60

2) Broadband Output Power: The broadband output power 50

takes into account the power of the fundamental and the powers 40
of all harmonics. For a periodic signal it can be calculated by
 T 2 30
1 vout,ac
Pout,ac = · dt , (1) 20
T 0 RL
where Pout,ac is the broadband output power measured at the 10

load resistance RL = 50 Ω with the period T . Fig. 7 shows 0

the measured broadband output power. The maximum power is 0.5 1 1.5 2 2.5 3
Signal frequency [GHz]
22 dBm for 0.25 GHz. At 2 GHz and 3 GHz the output power is
20 dBm and 18.6 dBm, respectively. The loss of output power Fig. 8. Measured efficiency of the switching mode amplifier vs. the signal
can be attributed to the decreasing output voltage swing and frequency for a periodic drive signal with a 50 % duty cycle.
to the increasing percentage of the transition time with regard
to the whole period.
Additionally, the broadband power added efficiency PAEp is
3) Efficiency: The measured broadband output power is
defined as
compared to a theoretical switching mode amplifier with 100% Pout,ac − Pin
efficiency, infinite steep transitions and full output swing. P AEp = . (5)
PDC
In case of an output-swing of 6 V and a load resistance of
RL = 50 Ω the ideal broadband output power is calculated by Pin is calculated in the same way as the output power. ηp
and P AEp are almost equal because of the high gain of the
VRMS
2
32 amplifier chain. Compared to the ideality factor, the broadband
Pout,ac,ideal = = W = 180 mW =  22.55 dBm , (2)
RL 50 efficiency is reduced due to the capacitive power loss in
where VRMS is 3 V and RL is 50 Ω for a single-ended measu- the output stage and the power consumption of the signal
rement. The ideality factor is defined as processing circuits of the chip. There are static losses in the
CML buffers and dynamic losses in the delay cells, analysis
Pout,ac
IF = . (3) circuit and driver. These losses limit the broadband efficiency
Pout,ac,ideal of the switching mode amplifier.
The measured amplifier does not reach this value due to static
and dynamic losses and hence IF < 100 %. Fig. 8 shows the B. PRBS Pulse Train
ideality factor against the signal frequency.
One channel is driven with a PRBS pulse train whereas
For further efficiency analysis the unfiltered broadband effi-
the second channel is static. The resulting uncalibrated eye
ciency ηp is defined as
diagrams are depicted in Fig. 9. The relative vertical eye
Pout,ac Pout,ac opening is over 50 % for all eyes. For 5 Gbit/s the relative
ηp = = . (4)
PDC Pout,ac + Pstat + Pdyn horizontal eye opening is 53 %.
 power combiner, the measured output power with the hybrid
is slightly below the possible calculated values.
4.7 V Fig. 10 shows the measured efficiencies in differential mode.
4.16 V For low frequencies the PAEp increases to 42.5 % compared to
232 ps 158 ps the single-ended measurement because the static power loss is
constant for the differential and single-ended measurements.
Table I summarizes the constant static power loss Pstat,S/D ,
the dynamic power loss Pdyn,S and output power Pout,ac,S for
the single-ended measurement and Pdyn,D , Pout,ac,D for the
differential measurement with the possible calculated values.

IV. C ONCLUSION
3.57 V 3V In this paper, a 6 V switching mode amplifier in 65 nm
108 ps 106 ps
CMOS is presented. A stacked transistors topology with thin-
and thick-oxide FETs is used to prevent breakdown of the
transistors. Therefore EDMOS is not needed in this design. The
measured broadband output power and calculated efficiencies
of the two on-chip amplifiers in single-ended and differential
Fig. 9. Uncalibrated eye diagrams with PRBS 215 − 1 for 3 Gbit/s (upper operation are shown in the CW-frequency range up to 3 GHz.
left), 4 Gbit/s (upper right), 4.5 Gbit/s (lower left) and 5 Gbit/s (lower right). The high bandwidth is also proven by PRBS measurements.
100 25
Compared to the earlier design in [4] the output power is incre-
Output power (hybrid) ased especially in differential mode. The proposed switching
90 Output power (math) 23.5 mode amplifier with stacked transistors can be built in a cheap
80 22 CMOS technology and can be integrated on the same die as
the signal processor. The high bandwidth without the need of
Ideality Factor [%], PAEp [%]

70 20.5
output matching networks make the amplifier applicable for
Output power [dBm]

60 19 different standards and channels. Table II summarizes recent

publications of SA in CMOS technologies.
50 17.5

40 16
TABLE II. S TATE OF THE ART CMOS SWITCHING MODE AMPLIFIER .
f Pout VDD
30 14.5 Ref. Technology
[GHz] [dBm] [V]
PAE p (math)
20
PAE p (hybrid)
13 [1] 65 nm CMOS 0.9-3.6 23.4 9.0
10 IF (math) 11.5
(EDMOS) (@2.1 GHz)
IF (hybrid) [2] 65 nm CMOS 0.5-4 n.a. 10.0
0 10 (EDMOS)
0.5 1 1.5 2 2.5 3
Signal frequency [GHz]
[3] 0.14 μm CMOS 0.45-1 n.a. 5.0
(EDMOS-Driver)
Fig. 10. Measured differential output power and efficiencies in differential LDMOS 0.45-1 41.3-40.3 20.0
mode vs. the signal frequency for a periodic drive signal with a 50 % duty [4] 65 nm CMOS 0.011 -4 14 3.0
cycle. (@3 GHz)
This work 65 nm CMOS 0.011 -3 21.3 6.0
(@2 GHz)
C. Two Channel Differential Measurements 1
Limited by DC-block for measurements.
The two on-chip amplifiers can be operated in differential
mode. A power combiner is used to increase the output power. R EFERENCES
The power combiner is used off-chip and is realized by a 180◦
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