Disposivos Electrónicos MOSFET V10a

Dispositivos Electrnicos
MOSFET
Pontificia Universidad Javeriana 2011

Metal
Estructura del MOSFET Oxide
Semiconductor
Field
Effect
Transistor
Figure 4.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross-section. Typically L = 0.1 to 3 mm, W = 0.2 to
100 mm, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm.
Microelectronic Circuits - Fifth Edition Sedra/Smith 2

MOSFET dibujado con Microwind
3
Photo-Lithographic Process
optical
mask
oxidation
photoresist photoresist coating

removal (ashing)
stepper exposure
Typical operations in a single

photolithographic cycle (from [Fullman]).
photoresist
development
acid etch
process spin, rinse, dry
step
Rabaey
4
5
6
7
Aplicando Voltage en Gate vgs (Compuerta)
Figure 4.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at
the top of the substrate beneath the gate.

Resistencia dependiente de Vgs
Con Vds Pequeo
El valor de vgs requerido para

acumular suficientes electrones
mviles Vt crea Canal
Figure 4.3 An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a resistance whose value is
determined by vGS. Specifically, the channel conductance is proportional to vGS Vt and thus iD is proportional to (vGS Vt) vDS.
Note that the depletion region is not shown (for simplicity).

Con Vds Grande (pero en resistiva)
Figure 4.5 Operation of the enhancement NMOS transistor as vDS is increased. The induced channel
acquires a tapered shape, and its resistance increases as vDS is increased. Here, vGS is kept constant at a
value > Vt.
Microelectronic Circuits - Fifth Edition
10
Sedra/Smith
Curva Caracterstica
del MOSFET (Id Vds)
Figure 4.6 The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated with vGS > Vt.

ox Capacitancia para dx
C ox
ox t ox CoxWdx
Permitividad del dixido de Silicio
tox
Grosor del xido depende del
proceso
mn
Movilidad de los electrones depende
del proceso
Figure 4.8 Derivation of the iDvDS characteristic of the NMOS transistor.

Corriente es la variacin de la carga en el tiempo
La corriente es la misma en todos los puntos, por tanto, corriente en Drain es:
13
La Corriente se mantiene
constante
14
15
Resistencia dependiente de Vgs
16
Vgs
Figure 4.12 The iDvGS characteristic for an enhancement-type NMOS transistor in saturation (Vt = 1 V, kn W/L = 1.0
mA/V2).
17
Figure 4.10 (a) Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol with an
arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n channel). (c)
Simplified circuit symbol to be used when the source is connected to the body or when the effect of the body on device
operation is unimportant.

MOSFET de
ENRIQUECIMIENTO o
MEJORA
El MOSFET tipo Mejora opera en trodo si:

Vgs > Vt
Vd < Vg en al menos Vt
Figure 4.11 (a) An n-channel enhancement-type MOSFET with vGS and vDS applied and with the normal directions of
current flow indicated. (b) The iDvDS characteristics for a device with kn (W/L) = 1.0 mA/V2.

Modelo del Mosfet en los tres estados
20
Figure 4.13 Large-signal equivalent-circuit model of an n-channel MOSFET operating in the saturation region.
21
Figure 4.14 The relative levels of the terminal voltages of the enhancement NMOS transistor for operation in the triode
region and in the saturation region.
22
Modulacin del Canal
Figure 4.15 Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from the drain, thus
reducing the effective channel length (by DL).
23
24
Figure 4.16 Effect of vDS on iD in the saturation region. The MOSFET parameter VA depends on the process technology
and, for a given process, is proportional to the channel length L.
25
Figure 4.17 Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating the output
resistance ro. The output resistance models the linear dependence of iD on vDS and is given by Eq. (4.22).
26
Mosfet Canal P
Figure 4.18 (a) Circuit symbol for the p-channel enhancement-type MOSFET. (b) Modified symbol with an arrowhead on the source
lead. (c) Simplified circuit symbol for the case where the source is connected to the body. (d) The MOSFET with voltages applied and
the directions of current flow indicated. Note that vGS and vDS are negative and iD flows out of the drain terminal.
27
Figure 4.19 The relative levels of the terminal voltages of the enhancement-type PMOS transistor for operation in the triode region
and in the saturation region.
28
Modelo Nmos y Pmos
Table 4.1
29
mA L 1mm
Vgs-Vt mnCox 100
V2 W 32 mm
Vt 0.7V 0
VDS VGS Vt Saturacin
VD VS VG VS Vt
VD VG Vt
VD VG Vt
VDG Vt Disear para ID=0.4mA VD=+0.5V
Figure 4.20 Circuit for Example 4.2.
30
Disear el circuito para ID=80uA. Calcular R en encontrar VD
Mosfet Saturado
31
Si Q1=Q2 y R=25k Calcular Id2 y Vd2
Figure E4.12
32
Vt =1V, Kn(W/L) = 1mA/V
Se quiere que Vd= +0.1V, calcular RD
Vdg = (Vd-Vg)= 0.1V-5V= -4.9V
33
Figure 4.23 (a) Circuit for Example 4.5. (b) The circuit with some of the analysis details shown.
34
35
Figure 4.25 Circuits for Example 4.7.
36
Figure 4.9 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is
formed in a separate n-type region, known as an n well. Another arrangement is also
possible in which an n-type body is used and the n device is formed in a p well. Not shown
Figure E4.16 are the connections made to the p-type body and to the n well; the latter functions as the
body terminal for the p-channel device.

Figure 4.9 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type
region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n device is
formed in a p well. Not shown are the connections made to the p-type body and to the n well; the latter functions as the
body terminal for the p-channel device.

Recta de Carga
Figure 4.26 (a) Basic structure of the common-source amplifier. (b) Graphical construction to determine the transfer characteristic of
the amplifier in (a).

Funcin de Transferencia
rds pequea
Figure 4.26 (Continued) (c) Transfer characteristic

showing operation as an amplifier biased at point Q.

Manejo y Recta de Carga
Figure 4.27 Two load lines and corresponding bias points. Bias point Q1 does not leave sufficient room for positive signal
swing at the drain (too close to VDD). Bias point Q2 is too close to the boundary of the triode region and might not allow for
sufficient negative signal swing.
41
=10V
Kn=1mA/V Ejemplo
Vt=1V
RD=18k
Saturacin-Triodo
Segmento BC - Regin Trodo
Si vds=vo es pequea
Figure 4.28 Example 4.8
45
Figure 4.29 The use of fixed bias (constant VGS) can result in a large variability in the value of ID. Devices 1 and 2
represent extremes among units of the same type.
46
Variabilidad de la polarizacin con el
cambio de dispositivo
Figure 4.30 Biasing using a fixed voltage at the gate, VG, and a resistance in the source lead, RS: (a) basic arrangement; (b)
reduced variability in ID; (c) practical implementation using a single supply; (d) coupling of a signal source to the gate
using a capacitor CC1; (e) practical implementation using two supplies.
47
Algunas formas prcticas de Polarizacin
49
Polarizacin con resistencia de realimentacin
Ejemplo:
VDD=+5V, Kn(W/L)=1mA/V, Vt=1V
Disear para ID=0.5mA
Figure 4.32 Biasing the MOSFET using a large drain-to-gate feedback resistance, RG.
50
Polarizacin con Fuente de Corriente
Figure 4.33 (a) Biasing the MOSFET using a constant-current source I. (b) Implementation of the constant-current source I
using a current mirror.
51
Amplificador de seal pequea
Seal
Polarizacin
Figure 4.34 Conceptual circuit utilized to study the operation of the MOSFET as a small-signal amplifier.
52
Transconductancia para seal pequea
Figure 4.35 Small-signal operation of the enhancement MOSFET amplifier.
53
Trasnconductancia gm
Polarizacin + Seal
Valor instantneo de iD
Polarizacin Seal Distorsin
Para disminuir Distorsin Seal Pequea

Trasnconductancia gm cont
Para seal pequea:

Polarizacin + Seal
Seal
Modelo para seal pequea con =0 y 0
Figure 4.37 Small-signal models for the MOSFET: (a) neglecting the dependence of iD on vDS in saturation (the channel-length
modulation effect); and (b) including the effect of channel-length modulation, modeled by output resistance ro = |VA| /ID.
56
Howe and Sodini 57
Howe and Sodini 58
Para Diseo VLSI
Ganancia de Voltaje
Polarizacin a la
entrada
Limite por
corte
Aproximacin
Polarizacin a la salida Lineal
Es vlida?
Limite por resistiva
Figure 4.36 Total instantaneous voltages vGS and vD for the circuit in Fig. 4.34. 60
.
Manejo con Mosfet - Modelo Real Vs Modelo Ideal

Dada la polarizacin:
Vgs=1.1V @ Id=0.45mA.
Vt=1V
Mos en Saturacin:
Kn(Vgs Vt ) 2 0.45mA Kn0.1V

1 1
Id
2
2 2

0.9mA Kn 0.01V 2 por tanto: 90mA / V 2 Kn
En ese punto de operacin,
gm 2KnId 180mA / V 2 * 0.45mA 9mA / V
Condiciones lmites de Manejo:

Vgs mnimo Vt=1V, con polarizacin de Vgs=1.1V, la seal solo puede bajar 100mVp
La ganancia en el punto de operacin es:

Vds
Av gmR1 9mA / V * 4k 36V / V
Vgs
Por que?
Punto de polarizacin: Q, Vds=3.2V Id=0.45mA
De las formas de onda, ganancia medida
Vds (3.2 2.822)V

Av 37.8V / V
Vgs 0.01V
Diferencia con lo calculado es debida

a que gm real no es una constante.
Paso de saturacin a Triodo: Lmite de

manejo a la salida, en ese punto son tanto
vlidas las ecuaciones de saturacin como de Simulacin con seal pequea.
trodo, usando la ecuacin de saturacin se Vi=10mVp. Arriba Vi, abajo VD
tiene:
1
Id Kn(Vgs Vt ) 2
2
1
y se tiene tambin que: VD VDD Kn(Vgs Vt ) 2 RD
2
VD VDD Id RD
remplazando Id
1
VD VDD Kn(Vgs Vt ) 2 RD
2
para condicin de trodo
VDS VD VGS Vt Vov
1
Vov VDD KnVov RD
2
2
RD
KnVov Vov VDD 0
2
2
Resolviendo la ecuacin cuadrtica:
1 1 2RDVDD K n
Vov
RD K n
Para el caso con Kn=90mA/V, VDD=5V , RD=4k, Vov=0.164V, con Vt=1V
Vgsmax=1.164 o lmite de manejo a la entrada
Funcin de Transferencia Vds Vs Vgs
(Gran Seal)
Funcin de transferencia Vds Vs Vgs (Punto Q Vds=3.2V)

Vgsmax=1.164 pasa a triodo
Igualando el modelo ideal con gm=9mA/V y ajustando la
polarizacin del modelo ideal.
R1
4k
Vt M2
Modelo Real
V1
VOFF = 0 V4 5Vdc
1Vdc Mbreakn
VAMPL = 0.01
FREQ = 1k
1.1Vdc V2
0 0 0 Con seal pequea, V salida Modelo ideal y modelo

real resultan muy similares
R2
4k
0.009*((V(%IN) -1.0495))
Modelo Ideal
Agregando Limitacin de manejo al modelo ideal
R1
4k
Vt M2
V1
VOFF = 0 V4 5Vdc
1Vdc Mbreakn
VAMPL = 0.05
FREQ = 1k
1.1Vdc V2
0 0 0
R2
4k
0.009*((V(%IN) -1.0495)) 5
1
0
R3
1k
0 0
Limitando el modelo ideal Funcin de transferencia Modelo ideal

entre 0 y 5V=Vdd (verde) y Modelo Real (rojo)
Resultado de la simulacin de los dos modelos
con seal grande, pero antes de entrar en limitacin
Ideal en Verde.
Real en Rojo
Antes de que acte el limitador, ya se nota la alinealidad.

Ntese que la seal real es mayor para valores negativos y es menor para
valores positivos.
Ntese como aparentemente la seal ideal en valores positivos an no ha entrado en limitacin,
aunque se nota una fuerte distorsin, en tanto el limitador ideal recorta la seal positiva. De otra
parte, para valores negativos el modelo real aumenta su ganancia y recorta la seal, en tanto que
el modelo ideal an no llega a cero voltios y por tanto no limita.
El modelo real limita valores negativos antes de llegar a cero voltios, pues el MOS entra en
resistiva y por tanto atena.
La seal en Verde, es la ideal sin el limitador, la seal en rojo es la real y la morada

es la ideal, con el limitador.
Ejemplo
Circuito Debidamente Polarizado
iD
Circuito equivalente Modelo para AC
iD g m vgs vds ro
Figure 4.38 Example 4.10: (a) amplifier circuit; (b) equivalent-circuit model.
70
MODELO T
Figure 4.39 Development of the T equivalent-circuit model for the MOSFET. For simplicity, ro has been omitted but can
be added between D and S in the T model of (d).
71
Modelo T y ro
ig=0
Figure 4.40 (a) The T model of the MOSFET augmented with the drain-to-source resistance ro. (b) An alternative
representation of the T model.
72
Efecto Cuerpo (Body Effect)
gmb del orden de 0.1 a 0.3 gm
Figure 4.41 Small-signal equivalent-circuit model of a MOSFET in which the source is not connected to the body.
73
MODELOS y T
Table 4.2
74
El Mosfet como Amplificador
El transistor debe estar

polarizado en Activa o
Saturacin de Corriente !
Figure 4.42 Basic structure of the circuit used to realize single-stage discrete-circuit MOS amplifier configurations.

Ejemplo de Polarizacin
Vt=1.5V
Kn(W/L)=1mA/V
VA=75V
1 'W
Vgs Vt 1mA / V Vov 0.5mA
1
Id kn
2 2 2
2 L 2
El Drain puede bajar hasta Vt=-1.5V

en saturacin (Vg=0V)
gm 2 KnI D 2 1mA / V 2 0.5mA 1mA / V
Microelectronic Circuits - Fifth Edition Sedra/Smith Figure E4.30 76

Parmetros de Amplificadores -- Definiciones Generales
Microelectronic Circuits - Fifth Edition Sedra/Smith Table 4.3 78
Ejemplo de Amplificador (calcular Rin)
Vsig=10mV Se mide:
Para RL vo=90mV
Para RL=10k vo=70mV
Para RL
Rsig=100k Se mide:
vo 90mV
Para RL vi=9mV Avo 10V V
vi 9mV
Para RL=10k vi=8mV vo 90mV
Gvo RL 9V V
vsig 10mV
Ri Ri
Gvo Avo 10V V
Ri Rsig Ri Rsig
Modelo Unilateral Como: Rsig=100k entonces Rin=900k

Ejemplo Continuacin Calcular Ro
Para RL=10k
vo 70mV
Av 8.75V V
vi 8mV
vo 70mV
Gv 7V V
vsig 10mV
Modelo Unilateral
RL
Av Avo 8.75V V
RL Ro
Ro 1.43k
Circuito no unilateral
- RL modifica la R
entrada.
- Rsig Modifica la R
Salida
Circuito unilateral
- RL No modifica la R
entrada
- Rsig No Modifica la R
Salida
Tres configuraciones: SC, DC, GC
SC: Source Comn
DC: Drain Comn
GC: Gate Comn

Amplificador Souce Comn
Figure 4.43 (a) Common-source amplifier based on the circuit of Fig. 4.42. (b) Equivalent circuit of the
amplifier for small-signal analysis. (c) Small-signal analysis performed directly on the amplifier circuit with the
MOSFET model implicitly utilized.

Amplificador Souce Comn Cont
Rout
Amplificador Source Comn con resistencia de source
Con ro despreciable
Figure 4.44 (a) Common-source amplifier with a resistance RS in the source lead. (b) Small-signal equivalent
circuit with ro neglected.

Amplificador Source Comn con resistencia de source cont
RL RD
Av
1 gm RS
Amplificador Source Comn con Rs, efecto Body y de ro (Seccin 6.9.1)
Figure 6.47 (a) A CS amplifier with a source-degeneration resistance Rs. (b) Circuit for small-signal analysis. (c) Circuit with the output open
to determine Avo. (d) Output equivalent circuit. (e) Another output equivalent circuit in terms of Gm.
Microelectronic Circuits - Fifth

87
Edition Sedra/Smith
Amplificador Gate Comn Con ro despreciable
Modelo T
Norton
Figure 4.45 (a) A common-gate amplifier based on the circuit of Fig. 4.42. (b) A small-signal equivalent circuit
of the amplifier in (a). (c) The common-gate amplifier fed with a current-signal input.

Amplificador Gate Comn cont Optimista !!
Amplificador Gate Comn cont
Vd/vg
Vd/vg RL->
Si ro no es despreciable, Rout (ro||RD) si Rsig pequea

Que ocurre con Rout si Rsign no es pequea?
CONCLUSIONES de Gate Comn
Versus Source Comn
Gate Comn con efecto de ro, carga
activa y efecto Body (Seccin 6.7.1)
vsig, tiene un voltaje DC

negativo (polarizacin)
mas seal AC
Figure 6.27 (a) Active-loaded common-gate amplifier. (b) MOSFET equivalent circuit for the CG case in which the body and gate terminals are
connected to ground. (c) Small-signal analysis performed directly on the circuit diagram with the T model of (b) used implicitly. (d) Operation with
the output open-circuited.
92
Edition Sedra/Smith
Gate Comn con efecto de ro,
carga activa y efecto Body cont..
Ganancia de i =1
ii
Rin
vi
Si RL-> => Rin->

Ganancia de circuito Abierto RL-> en CG
Por efecto de ro, Rin se incrementa

en RL/Ao
Ganancia Total de Circuito Abierto RL->
Cmo hacer RL->?

Carga Activa
Efecto de la R de Source en la Impedancia de Salida
Ntese el efecto en Ro si
de alguna manera se
cambia VGS
Variar
-Vs
95
Impedancia de salida GATE COMUN
con Rs
Determinacin de Rout
visto desde Drain
Rout=V/I=30k
Para lograr VGS=2.13

Se comprueba que ID=1mA
Cmo se logra esto?
Ntese como aument

Rout, de 30k a 120k
modificando Vs
Gate Comn con efecto de ro, carga activa y efecto Body cont..
Determinacin de Rout se hace vsig =0
-El circuito no es unilateral- Rs influye en Rout (RoRout)
Figure 6.28 (a) The output resistance Ro is found by setting vi = 0. (b) The output resistance Rout is obtained by setting vsig =0.

99
Edition Sedra/Smith
Figure 6.30 Equivalent circuit of the CG amplifier illustrating its application as a current buffer. Rin and Rout are given in Fig. 6.29, and Gis 5
Avo (Rs/Rout) . 1.

100
Edition Sedra/Smith
Amplificador Drain Comn
Figure 4.46 (a) A common-drain or source-follower amplifier. (b) Small-signal equivalent-circuit model. (c)
Small-signal analysis performed directly on the circuit. (d) Circuit for determining the output resistance Rout of
the source follower.
Amplificador Drain Comn cont
Amplificador Drain Comn cont
Seguidor de Source
RESUMEN
Source comn con R source
Source Comn
Table 4.4

RESUMEN cont
Gate Comn
Seguidor de Source
Concepto de Manejo
Funcin de transferencia Ideal y Real (se aplica una rampa a la entrada entre 0V y 0.9V
Mientras Vin no supere V el transistor est cortado y la salida es la fuente 10V
Se ve la diferencia del modelo ideal que, adems de ser lineal, recorta perfectamente la salida (se aplica la
aproximacin de seal pequea y se extiende linealmente a seal grande). El modelo real de seal grande,
que corresponde a una exponencial para BJT, no llega a recortar la seal (por corte) en este caso, pues la
ganancia disminuye cuando la seal llega a valores cercanos a V
Seales de salida, modelo ideal y real.
Si bien estrictamente ninguna de las dos seales est recortada, se ve claramente que las amplitudes, al llegar a los
extremos de la seal se diferencian bastante, lo que no ocurre alrededor del punto de polarizacin.
Figure 6.36 (a) The MOS cascode amplifier. (b) The circuit prepared for small-signal analysis with various input and output resistances
indicated. (c) The cascode with the output open-circuited.

Figure 6.43 A cascode current-source.

Figure 6.44 Double cascoding.

Figure 6.45 The folded cascode.

Figure 6.58 A cascode MOS current mirror.

Capacitancias Parsitas (Dependen del tamao de MOSfet)
Cox Cov
Capacitancia de Oxido, Capacitancia de Overlap
por unidad de rea por unidad de longitud
Howe Sodini
115
Figure 4.47 (a) High-frequency equivalent circuit model for the MOSFET. (b) The equivalent circuit for the case
in which the source is connected to the substrate (body). (c) The equivalent circuit model of (b) with Cdb
neglected (to simplify analysis).

117
Howe Sodini
Compuertas CMOS Negadora
Figure 4.53 The CMOS inverter.

Figure 4.54 Operation of the CMOS inverter when vI is high: (a) circuit with vI = VDD (logic-1 level, or VOH); (b)
graphical construction to determine the operating point; (c) equivalent circuit.

Figure 4.55 Operation of the CMOS inverter when vI is low: (a) circuit with vI = 0 V (logic-0 level, or VOL); (b)
graphical construction to determine the operating point; (c) equivalent circuit.

Figure 4.56 The voltage transfer characteristic of the CMOS inverter.

Figure 4.57 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output
waveforms; (c) trajectory of the operating point as the input goes high and C discharges through QN; (d)
equivalent circuit during the capacitor discharge.

Figure 4.58 The current in the CMOS inverter versus the input voltage.

(con CMOS tipo Mejora)
Basado en Howe and Sodini 124

Compuerta NOR con CMOS tipo Mejora
Figure 10.12 A two-input CMOS NOR gate.
125
Interruptor Analgico - requiere acceso al Bulk
Mosfet en Resistiva seales positivas y negativas en vi
Mosfet Cortados
cambiando lo Vgate
Editada de Figure 10.29 Operation of the transmission gate as a switch.
126
MOSFET DE AGOTAMIENTO (DEPLETION)
Figure 4.59 (a) Circuit symbol for the n-channel depletion-type MOSFET. (b) Simplified circuit symbol
applicable for the case the substrate (B) is connected to the source (S).

Figure 4.60 The current-voltage characteristics of a depletion-type n-channel MOSFET for which Vt = 4 V and
kn(W/L) = 2 mA/V2: (a) transistor with current and voltage polarities indicated; (b) the iDvDS characteristics; (c)
the iDvGS characteristic in saturation.

Figure 4.61 The relative levels of terminal voltages of a depletion-type NMOS transistor for operation in the
triode and the saturation regions. The case shown is for operation in the enhancement mode (vGS is positive).

Figure 4.62 Sketches of the iDvGS characteristics for MOSFETs of enhancement and depletion types, of both
polarities (operating in saturation). Note that the characteristic curves intersect the vGS axis at Vt. Also note that
for generality somewhat different values of |Vt| are shown for n-channel and p-channel devices.

Amplificadores Diferenciales
Modo Comn
Si Q1 = Q2
Con = 0
Figure 7.1 The basic MOS differential-pair configuration.

Manejo en Modo Comn Polarizacin
Para Q1 y Q2 permanezcan en
saturacin:
Para que la fuente de

corriente se mantenga activa
Vcs voltaje mnimo de la

fuente de I
Figure 7.2 The MOS differential pair with a common-mode input voltage vCM.

Modo Diferencial
Si vid es tal que Id1=I => vgs2=Vt Id2=0
Por tanto:
Entonces para vgs1
Donde:
O sea en polarizacin
Figure 7.4 The MOS differential pair with a differential input signal vid applied. With vid positive: vGS1 vGS2, iD1 iD2, and vD1 < vD2; thus
(vD2 vD1) will be positive. With vid negative: vGS1 < vGS2, iD1 < iD2, and vD1 vD2; thus (vD2 vD1) will be negative.

Modo Diferencial manejo
El valor de vid para que Q1 tenga toda la corriente I
Si vid trata de aumentar, Id1= I permanece constante, por tanto

vgs1 tambin permanece constante
vs debera aumentar (lmite de manejo)

Simtricamente para Q2, por tanto el manejo de entrada sera
Circuito bsico para obtener Funcin de Transferencia
(Gran Seal)
Mientras Q1 y Q2 saturados y =0
Por tanto:
Figure 7.5 The MOSFET differential pair for the purpose of deriving the transfer characteristics, iD1 and iD2 versus vid vG1 vG2.
135
Circuito bsico para obtener Funcin de
Transferencia (Gran Seal) Cont
Pero:
Resolviendo la cuadrtica para ID1
Como: Cuando vid aumenta, aumenta ID,

por tanto solo la raz positiva tiene
sentido
Remplazando:
Elevando al cuadrado
1 W 2 Para ID2 se tiene lo mismo
I D1 2 I D1 I D 2 I D 2 k n ' vid
2 L
Circuito bsico para obtener Funcin de Transferencia (Gran Seal) Cont
En polarizacin vid=0 se tiene
Remplazando e
Funciones de la variacin de ID con vid
Normalizada a
Funcin de Transferencia (Gran Seal)
Figure 7.6 Normalized plots of the currents in a MOSFET differential pair. Note that VOV is the overdrive voltage at which Q1 and Q2
operate when conducting drain currents equal to I/2.

Figure 7.7 The linear range of operation of the MOS differential pair can be extended by operating the transistor at a higher value of VOV.

Figure 7.8 Small-signal analysis of the MOS differential amplifier: (a) The circuit with a common-mode voltage applied to set the dc bias
voltage at the gates and with vid applied in a complementary (or balanced) manner. (b) The circuit prepared for small-signal analysis. (c)
An alternative way of looking at the small-signal operation of the circuit.

Figure 7.9 (a) MOS differential amplifier with ro and RSS taken into account. (b) Equivalent circuit for determining the differential gain.
Each of the two halves of the differential amplifier circuit is a common-source amplifier, known as its differential half-circuit.

Figure 7.10 (a) The MOS differential amplifier with a common-mode input signal vicm. (b) Equivalent circuit for determining the common-
mode gain (with ro ignored). Each half of the circuit is known as the common-mode half-circuit.

Figure 7.11 Analysis of the MOS differential amplifier to determine the common-mode gain resulting from a mismatch in the gm values of
Q1 and Q2.

Figure 7.25 (a) The MOS differential pair with both inputs grounded. Owing to device and resistor mismatches, a finite dc output voltage
VO results. (b) Application of a voltage equal to the input offset voltage VOS to the terminals with opposite polarity reduces VO to zero.

Figure 7.28 (a) The active-loaded MOS differential pair. (b) The circuit at equilibrium assuming perfect matching. (c) The circuit with a
differential input signal applied, neglecting the ro of all transistors.

Figure 7.29 Determining the short-circuit transconductance Gm ; io/vid of the active-loaded MOS differential pair.

Figure 7.30 Circuit for determining Ro. The circled numbers indicate the order of the analysis steps.
147

Disposivos Electrónicos MOSFET V10a

Uploaded by

Document Information

Original Description:

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Disposivos Electrónicos MOSFET V10a

Uploaded by

Copyright:

Available Formats

Dispositivos Electrnicos

Pontificia Universidad Javeriana 2011

Microelectronic Circuits - Fifth Edition Sedra/Smith 2

photoresist photoresist coating

Typical operations in a single

Microelectronic Circuits - Fifth Edition Sedra/Smith 8

El valor de vgs requerido para

Microelectronic Circuits - Fifth Edition Sedra/Smith 9

Microelectronic Circuits - Fifth Edition Sedra/Smith 11

Figure 4.8 Derivation of the iDvDS characteristic of the NMOS transistor.

Microelectronic Circuits - Fifth Edition Sedra/Smith 12

Microelectronic Circuits - Fifth Edition Sedra/Smith 18

El MOSFET tipo Mejora opera en trodo si:

Microelectronic Circuits - Fifth Edition Sedra/Smith 19

VDS VGS Vt Saturacin

Figure 4.21 Circuit for Example 4.3.

Vdg = (Vd-Vg)= 0.1V-5V= -4.9V

Figure 4.22 Circuit for Example 4.4.

Microelectronic Circuits - Fifth Edition Sedra/Smith 37

Microelectronic Circuits - Fifth Edition Sedra/Smith 38

Microelectronic Circuits - Fifth Edition Sedra/Smith 39

Figure 4.26 (Continued) (c) Transfer characteristic

Microelectronic Circuits - Fifth Edition Sedra/Smith 40

Disear para ID=0.5mA

Figure 4.35 Small-signal operation of the enhancement MOSFET amplifier.

Polarizacin Seal Distorsin

Para disminuir Distorsin Seal Pequea

Para seal pequea:

Limite por resistiva

Manejo con Mosfet - Modelo Real Vs Modelo Ideal

Kn(Vgs Vt ) 2 0.45mA Kn0.1V

En ese punto de operacin,

gm 2KnId 180mA / V 2 * 0.45mA 9mA / V

Condiciones lmites de Manejo:

La ganancia en el punto de operacin es:

De las formas de onda, ganancia medida

Vds (3.2 2.822)V

Diferencia con lo calculado es debida

Paso de saturacin a Triodo: Lmite de

VDS VD VGS Vt Vov

Funcin de transferencia Vds Vs Vgs (Punto Q Vds=3.2V)

0 0 0 Con seal pequea, V salida Modelo ideal y modelo

Limitando el modelo ideal Funcin de transferencia Modelo ideal

Antes de que acte el limitador, ya se nota la alinealidad.

La seal en Verde, es la ideal sin el limitador, la seal en rojo es la real y la morada

Circuito Debidamente Polarizado

Circuito equivalente Modelo para AC

gmb del orden de 0.1 a 0.3 gm

El transistor debe estar

Microelectronic Circuits - Fifth Edition Sedra/Smith 75

El Drain puede bajar hasta Vt=-1.5V

gm 2 KnI D 2 1mA / V 2 0.5mA 1mA / V

Microelectronic Circuits - Fifth Edition Sedra/Smith Figure E4.30 76

Modelo Unilateral Como: Rsig=100k entonces Rin=900k

SC: Source Comn

DC: Drain Comn

GC: Gate Comn

Microelectronic Circuits - Fifth Edition Sedra/Smith 83

Microelectronic Circuits - Fifth Edition Sedra/Smith 85

Microelectronic Circuits - Fifth

Microelectronic Circuits - Fifth Edition Sedra/Smith 88

Si ro no es despreciable, Rout (ro||RD) si Rsig pequea

vsig, tiene un voltaje DC